JPH03116840A - Charge transfer device - Google Patents

Abstract

PURPOSE:To contrive a reduction in a parasitic capacity in the terminal part of a charge transfer part by a method wherein an output lead-out part, which terminates at the charge transfer part, and the transistor of an output part, to which a wiring from the output lead-out part is connected, are surrounded with the same element isolation region and are formed within a single element formation region. CONSTITUTION:A CCD 1 has a thick field oxide film 2 formed on a silicon substrate and the film 2 is a thick oxide film, which is formed by a selective oxidation method, and has a tapered part 3 on its periphery. This part 3 is formed in such a way that a single closed curve is drawn, in particular an MQS transistor 6, a floating fusion region 5, a buried channel layer 4, a precharge drain 8 and the like are encircled with the one continued tapered part 3 in such a way that they are formed within the same element formation region. Owing to this, the need that a polycrystalline silicon layer 10 which is used as a gate electrode of the transistor 6 is wired up and down on the slant surface of the tapered part at the end part of the film 2 is eliminated and a parasitic capacity is reduced by the amount of the wiring which becomes unnecessary.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge transfer device having a charge transfer section using a charge coupled device.

[Summary of the invention]

In a charge transfer device in which elements are isolated by an oxide film thicker than a gate oxide film, the present invention provides an output section that terminates a charge transfer section and an output section transistor to which wiring from the output section is connected. By forming it in a single element formation region surrounded by the same element bone N61 region, or by arranging a conductor layer that is used as the source potential of the transistor between the transistor and the output extraction part. , to reduce the parasitic capacitance of the device.

[Conventional technology]

A CCD generally has an output take-out part for taking out the output of a floating diffusion or the like at the end of a charge transfer part (register), and an output signal is sent from the floating diffusion through a source follower-configured buffer or the like. is output. Also, such CC
In D, a thick field oxide film (LOGO5) is formed on the surface of the silicon substrate by selective oxidation in order to isolate each element.

FIG. 5 is a plan view of the terminal end of a register of such a conventional CCD. As shown in FIG. 5, a buried channel layer 102 is formed surrounded by a field oxide film 101 formed on a silicon substrate, and a floating diffusion region 103 is formed at the narrowed end of the buried channel layer 102. It is formed. A precharge gate 104 for precharging (resetting) is adjacent to this floating diffusion region 103, and a precharge drain 105 is formed adjacent to the precharge gate 104. Polysilicon N106 is taken out from the floating diffusion region 103 through a contact hole 108, and this polysilicon layer 106 is used as the gate electrode of the first stage MOS transistor 107 of the output section.

FIG. 6 is a sectional view taken along the line ■--■ in FIG. 5. As shown in FIG. 6, a thick field oxide 8101 is formed on the surface of the silicon substrate 100 by selective oxidation.

The floating diffusion region 103 and the MOS transistor 107 are surrounded by separate field oxide films 101 on a plane, and the field oxide films 10
A channel stopper region 109 is provided at the bottom of the channel 1 .

[Problem to be solved by the invention]

By the way, in order to improve the output gain of a CCD with such a structure, it is necessary to reduce the capacitance (parasitic field) of the output section as a whole.This capacitance includes the capacitance of the floating diffusion region 103 and the precharge gate 104
This includes the capacitance between the floating diffusion region 103 and the MOS transistor 1, as well as the wiring capacitance of the polysilicon layer 106 and the capacitance between the polysilicon layer 106 and the source/drain of the transistor.
By reducing the size of 07, the overall parasitic capacitance can be reduced.

However, the wiring capacitance of the polysilicon layer 106 is formed over the tapered part 110 of the field oxide film 01, and this tapered part 110 cannot be removed even when the area of the field oxide film 101 is reduced. Can not.

Therefore, the wiring capacitance caused by the polysilicon layer 106 has been an obstacle to improving the output gain.

Therefore, the present invention is based on the above-mentioned technical! In view of one problem, an object of the present invention is to provide a charge transfer device that reduces parasitic capacitance at the terminal end of a charge transfer section.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the charge transfer device of the first invention of the present application has an element isolation region formed on a semiconductor substrate by an oxide film thicker than a gate oxide film. In the charge transfer device to be formed, an output take-out part that terminates the charge transfer part and a transistor in the output part to which wiring from the output take-out part is connected are formed as a single element surrounded by the same element isolation region. It is characterized by being formed within a region.

Further, in the charge transfer device of the second invention of the present application, in a charge transfer device in which an element bone region M is formed on a semiconductor substrate by an oxide film that is thicker than a gate oxide film, an output terminal that terminates a charge transfer portion is provided. A take-out part and an output part MIS transistor to which wiring from the output take-out part is connected are formed in a single element formation region surrounded by the same element molecule M Si region, and the output take-out part A conductor layer is formed on the semiconductor substrate between the MfS transistor and the MIS transistor with an insulating film interposed therebetween, and the conductor layer is set to the source potential of the MfS transistor.

Note that the output extraction section is, for example, a structural section such as a floating diffusion region or a floating gate.

[Effect]

In the charge transfer device of the present invention, instead of using an oxide film that is thicker than the gate oxide film to isolate all elements, the output transistor and the output take-out part that terminates the charge transfer part are formed in a single closed curve. By forming the element in the element formation region surrounded by the element bone N9M region, a structure is obtained in which no thick oxide film exists between the transistor of the output part and the output extraction part. This prevents the parasitic capacitance of the wiring from increasing at a portion such as a tapered portion of a thick oxide film, making it possible to reduce the overall capacitance.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment This embodiment is an example of a CCD, in which a wiring layer made of a polysilicon layer is formed from a floating diffusion region as an output extraction section to a transistor in an output section.

First, a plan view of the main parts of the COD of this embodiment is shown in FIG. 1. As shown in FIG. 1, the CCD 1 has a thick field oxide film 2 formed on a silicon substrate.
Surrounded by this field oxide film 2, buried channels FJ4. Floating diffusion region5.
MOS) transistor, precharge gate 7, and precharge drain 8 are formed. The field oxide film 2 is a thick oxide film formed by a selective oxidation method, and has a tapered portion 3 around it. Although this tapered portion 3 breaks at the buried channel layer 4 in the figure, it draws a single closed curve, and in particular, the MOS transistor 6 and the floating diffusion region 5. The buried channel layer 4, precharge drain 8, etc. are surrounded by one continuous tapered portion 3 so as to form the same element formation region.

Here, the buried channel layer 4 is a region where charges are transferred, and although not shown in the figure, a transfer electrode driven by a required transfer lock signal is formed on the buried channel layer 4. Furthermore, an output gate for controlling the timing for transferring charges to the floating diffusion region 5, for example, is also formed at the terminal end.

Furthermore, the floating diffusion region 5 is a region for extracting charges transferred in the H direction in the figure, and is composed of an n-type impurity region. This floating diffusion region 5 has a substantially square pattern, and a polysilicon layer 10 is connected to the substantially center thereof through a contact hole 9.

Further, a precharge gate 7 formed adjacent to this floating diffusion region 5 is an electrode for controlling the timing of precharging. This precharge gate 7 is also formed of a polysilicon layer. Further, the precharge drain 8 is an impurity region to which a precharge voltage is applied.

The polysilicon layer 10 taken out from the floating diffusion region 5 extends in the V direction in the figure,
The 0M0S transistor 6, which is used as the gate electrode of the transistor (MOS) as it is, is made of polysilicon J.
! Source/drain regions 11.11 are provided on both sides of the transistor 10. This MOS transistor 6 has a source follower configuration and functions as a first stage element of the output sofa.

The field oxide film 2 surrounds this MOS transistor, but it surrounds only a part of the periphery of the MOS transistor 6, and the buried channel N4 side of the MOS transistor and the floating diffusion region 5. On the side, the field oxide film 2 is not formed, and therefore the MOS) transistor, the buried channel layer 4 and the floating diffusion region 5 are formed.
There is also no tapered portion 3 between them.

FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1,
As shown in FIG. 2, an n-type impurity region formed on the surface of a silicon substrate 120 is a floating diffusion region 5. A gate oxide film 13 is formed on the surface of the silicon substrate 12, and the gate oxide film 13 has a contact hole 9 above the floating diffusion region 5. A polysilicon layer IO is formed extending from contact hole 9 over gate oxide film 13 , and this polysilicon layer 10 becomes the gate electrode of MOS transistor 6 .

And floating diffusion area 5 and MO
In the region between the S transistors 6, only a channel stopper region 14 made of a p-type impurity region with a relatively low concentration is formed on the surface of the silicon substrate 12, and a thick field oxide film is formed. 2 is not formed, and accordingly, no tapered portion 3 is formed in the region between the floating diffusion region 5 and the MOS l-range star. Therefore, the MOS transistor 6
The polysilicon layer 10, which becomes the gate electrode, does not need to be wired up and down the slope of the tapered part of the end of the field oxide film, and the parasitic capacitance is reduced accordingly.

Second Embodiment This embodiment is an example in which an output section MOS transistor and a floating diffusion region are formed in the element formation region surrounded by the same field oxide film, and the MOS transistor is further surrounded by a floating diffusion region. This is an example in which a conductor layer that is brought to a source potential is formed.

First, a plan view of the main parts of the CCD of this embodiment is shown in FIG. 3. As shown in FIG. 3, the CCD 21 has a thick field oxide film 22 formed on a silicon substrate. Surrounded by this field oxide film 22, a buried channel layer 24. Floating diffusion region 25. MOS transistor 26. Precharge gate 2
7. A precharge drain 28 is formed. The field oxide film 22 is a thick oxide film formed by a selective oxidation method, and has a tapered portion 23 around it. This tapered portion 23 is formed at the end of the field oxide film 22, and in particular, the MOS transistor 2G and the floating diffusion region 25. Buried channel layer 24 and precharge drain 28. The precharge gate 27 is surrounded by the tapered portion 23 so as to form the same element forming area.

Here, floating diffusion region 25, buried channel layer 24 . Precharge drain 28.
The precharge gates 27 are respectively connected to the floating diffusion regions 5 and 5 in the first embodiment. Embedded channel layer 4. Precharge drain8. They are used in the same way as precharge gate 7.

MOS transistor 26 uses polysilicon layer 30 extending from contact hole 29 formed on floating diffusion region 25 as a gate electrode.

A source region 31S is formed on the buried channel M24 side of this polysilicon layer 30, and a drain region 31d is formed on the opposite side. And this MOS
) Polysilicon N34 as conductors 7H and N is formed surrounding transistor 26. This polysilicon layer 34 is formed in a pattern that surrounds the substantially rectangular MOS transistor 26 on a plane, and a portion of the polysilicon layer 34 is formed as a precharge drain 28 . It surrounds the region of precharge gate 27 and extends to the opposite side of floating diffusion region 25 .

This polysilicon layer 34 includes a MOS) transistor 2G
A source potential of is given. Therefore, formation of a channel under the polysilicon layer 34 is prevented.
In the figure, the wiring 35 schematically shown is a MOS) rungis 5.
! 26 source regions 31S and polysilicon layer 34 are electrically connected. The wiring 35 may be formed using a second polysilicon layer, or a contact hole may be formed on the source region 31s, and the polysilicon layer 34 may be superimposed on the contact hole.

4 is a cross-sectional view taken along the rV-mV line in FIG. 3, showing a gate oxide film 33 formed on a silicon substrate 32.
Along the top, a polysilicon layer 30 is formed which will become the gate electrode of the MOS transistor 26. Adjacent to the floating diffusion region 25 made of an n-type impurity region, a polysilicon layer 34 is formed to which a source potential is applied to prevent channel formation.

The polysilicon layer 30 and the polysilicon layer 34 are insulated by an interlayer insulating film 36 covering the polysilicon layer 34.

Since a source potential is applied to the polysilicon layer 34, the floating diffusion region 25 is electrically separated from the channel forming region below the gate of the MOS transistor 26.

Therefore, floating diffusion region 25 and M
Element isolation is possible without the need to provide field oxide film 22 between OS transistors 26, and since field oxide film 22 is not formed in that region, the wiring capacitance of polysilicon layer 30 is increased due to the tapered part. can be suppressed. Therefore, it is possible to improve output 1).

〔Effect of the invention〕

As described above, in the charge transfer device of the present invention, the transistor of the output section and the output extraction section such as the floating diffusion region draw one closed curve (a single element component).
Formed within the 81 area. Therefore, the parasitic capacitance l of the wiring from the output extraction section can be reduced, and as a result, the conversion efficiency from charge to output voltage can be increased, and the output gain can be improved.

[Brief explanation of drawings]

FIG. 1 is a plan view of essential parts of an example of a charge transfer device of the present invention, FIG. 2 is a cross-sectional view of the example along the line ■-■ in FIG. 1, and FIG. 3 is a charge transfer device of the present invention. FIG. 4 is a sectional view taken along the mV-rV line in FIG. 3 showing another example of the above, and FIG. 5 is a plan view of the main portion of an example of a conventional charge transfer device. , Fig. 6 shows an example of the conventional method.
It is a sectional view taken along the line -■. 1, 2 2.2 3.2 4.2 5.2 6.2 10°l...C0D 2...Field oxide film 3...Taper part 4...Buried channel layer 5... Floating Diffusion Yujo 6...MOS
) Transistor 30.34...Polysilicon layer wI area

Claims (2)

[Claims] (1) In a charge transfer device in which an element isolation region is formed on a semiconductor substrate by an oxide film that is thicker than a gate oxide film, an output extraction part that terminates the charge transfer part and wiring from the output extraction part are A charge transfer device characterized in that transistors of an output section to be connected are formed in a single element formation region surrounded by the same element isolation region. (2) A conductive layer is formed via an insulating film on the semiconductor substrate between the output take-out part that terminates the charge transfer part and the MIS transistor in the output part whose gate is connected to the wiring from the output take-out part. 2. The charge transfer device according to claim 1, wherein the conductor layer has a source potential of the MIS transistor.