JP2990288B2 - Gate array - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] A dedicated semiconductor substrate comprising a gate electrode formed on a semiconductor substrate via a gate oxide film and a source / drain region formed of an impurity diffusion layer self-aligned to the gate electrode. An electrode contact window which has a basic cell formed in a structure without a contact region, and which penetrates a part of the source region and exposes a part of the semiconductor substrate in a source region to which the same voltage as that of the semiconductor substrate is applied. Since the gate array is formed in such a structure that the connection to the semiconductor substrate is made by connecting to the wiring body via the flat buried conductive film, a fine semiconductor substrate contact region is not formed. The high integration that can be achieved by the basic cell configuration can be achieved by using the same size electrode contact window and Since the buried conductive layer contact windows high integration and high performance due to the possible formation of connection between the semiconductor substrate and the wiring member to form a gate array of fine elementary cells,
A gate array capable of increasing the speed by reducing the wiring capacitance and the wiring resistance and realizing a multi-functionality by forming a large-scale semiconductor integrated circuit with a high yield.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MIS type semiconductor integrated circuit, and more particularly, to a highly integrated gate array having fine basic cells.

Conventionally, for a basic cell of a gate array using an MIS field-effect transistor, a gate electrode formed through a gate oxide film, a source-drain region including an impurity diffusion layer formed self-aligned with the gate electrode, and a source-drain region. And a dedicated basic contact region made of an impurity diffusion layer formed by insulation isolation. However, in the case of a C-MOS type gate array, four MISs
For each field effect transistor (two P and N channel transistors), one substrate contact region (N
And one P-type substrate contact region), it is difficult to miniaturize the basic cell even if the MIS field-effect transistor is miniaturized, which hinders the enlargement of the gate array. The problem is becoming more pronounced. Therefore, there is a need for a means that can form a basic cell that can be connected to a semiconductor substrate without requiring a surface layout area of a dedicated semiconductor substrate contact region.

[Prior Art] FIGS. 3 (a) and 3 (b) are schematic diagrams of a conventional gate array, where (a) is a plan view, (b) is a part of a side sectional view in the channel length direction, and 51 is p- Type silicon substrate, 52 is a p-type impurity well region, 53 is a p + type channel stopper region, and 54 is n
+ Type source / drain region, 54a is an n + type source region to which the same voltage as the p type impurity well region is applied, 54b is an n + type source region to which a voltage different from the p type impurity well region is applied, 54c is n + type drain region , 55 are p + type source / drain regions, 56 is a field oxide film, 57 is a gate oxide film, 58 is a gate electrode, 59 is an impurity blocking oxide film, 60
Is a phosphor silicate glass (PSG) film, 61a is a region where an electrode contact window can be formed, 61b is an electrode contact window, 62 is a p + type impurity well contact region, 63 is an n + type impurity well contact region, 64 is an Al wiring, and 65 is a basic wiring. Shows a cell.

In the figure, two N-channel transistors (gate electrode 58, n + type source / drain region 54, p type impurity well region 52, p + type impurity well contact region 6)
2,) and two P-channel transistors (gate electrode 5)
8, a part of a gate array having a basic cell including a p + type source / drain region 55, an n type impurity well region, and an n + type impurity well contact region 63). (This shows two basic cells.) This gate array is formed by appropriately changing wiring and electrode contact windows.
In the plan view (a), the electrode contact window shows all the formable regions 61a, and the Al wiring 64 is omitted for easy understanding of the drawing. As is clear from the plan view (a) and part (b) of the side sectional view in the channel length direction, n +
A p + type impurity well contact region 62 is provided insulated from the type source / drain region 54, and an n + type impurity well contact region 63 is provided insulated from the p + type source / drain region 55, respectively. There is a disadvantage that a cell cannot be formed.

[Problems to be Solved by the Invention] The problems to be solved by the present invention are, as shown in the conventional example, insulated from the respective source / drain regions and opposite to those requiring a surface layout area. This is because a high-integration gate array could not be formed because it was necessary to form a basic cell in which a conductive impurity contact region was formed.

[Means for Solving the Problems] The above problems are caused by a gate electrode provided on a semiconductor substrate via a gate insulating film, and an impurity diffusion layer provided on the semiconductor substrate in self-alignment with the gate electrode. And a source / drain region comprising a basic cell without a dedicated semiconductor substrate contact region, and penetrating a part of a source region to which the same voltage as the semiconductor substrate is applied, and a part of the semiconductor substrate. The gate array according to the present invention has a structure in which a connection to the semiconductor base is formed by an electrode contact window exposing the conductive film, a conductive film embedded in the electrode contact window, and a wiring body connected to the conductive film.

[Operation] In other words, the gate array of the present invention comprises a gate electrode formed on a semiconductor substrate via a gate oxide film, and a source / drain region composed of an impurity diffusion layer formed self-aligned with the gate electrode. An electrode contact having a basic cell formed in a structure without a semiconductor substrate contact region and having a source region to which the same voltage as the semiconductor substrate is applied, penetrating a part of the source region and exposing a part of the semiconductor substrate. A gate array formed to have a structure in which a window is connected to a wiring body through a flat buried conductive film to make connection to a semiconductor substrate. Therefore, high integration by forming a fine basic cell that does not require the surface layout area of the dedicated semiconductor substrate contact region is realized by using an electrode contact window formed in a part of the source region and connected to the source region. By embedding a conductive film in an electrode contact window of the same size, which is extended until a part of the semiconductor substrate is exposed, high integration and high performance by forming a connection between the semiconductor substrate and the wiring body can be achieved by fine basics. Since a gate array composed of cells can be formed, the speed can be increased by reducing the wiring capacitance and the wiring resistance, and the multi-function can be realized by forming a large-scale semiconductor integrated circuit with high yield. That is, an extremely high-speed, high-performance, multifunctional, highly integrated gate array can be obtained.

[Examples] Hereinafter, the present invention will be described specifically with reference to illustrated examples. 1 (a) and 1 (b) are schematic views of one embodiment of the gate array of the present invention, and FIGS. 2 (a) to 2 (f) are cross-sectional views showing the steps of one embodiment of the manufacturing method of the gate array of the present invention. It is.

 The same objects are denoted by the same reference numerals throughout the drawings.

FIG. 1 shows an embodiment of a gate array of the present invention using a p-type silicon substrate, wherein 1 is a p-type silicon substrate of about 10 ¹⁵ cm ^−3.
A-type silicon substrate, 2 is a p-type impurity well region of about 10 ¹⁶ cm ^-3 , 3 is a p + -type channel stopper region of about 10 ¹⁷ cm ^-3 , 4 is an n + -type source / drain region of about 10 ²⁰ cm ^-3 ,
4a is an n + type source region to which the same voltage as the p-type impurity well region is applied, 4b is an n + type source region to which a voltage different from the p-type impurity well region is applied, 4c is an n + type drain region, and 5 is 10 ²⁰ cm ^{About -3} p + type source / drain region, 6
Is a field oxide film of about 600 nm, 7 is a gate oxide film of about 18 nm, 8 is a gate electrode of about 300 nm, 9 is an oxide film for impurity blocking of about 35 nm, 10 is a phosphor silicate glass (PSG) film of about 600 nm, 11a Is a region where an electrode contact window having a diameter of about 800 nm can be formed, 11b is an electrode contact window including a connection to a semiconductor substrate having a diameter of about 800 nm, and 12 is a buried conductive film (selective chemical vapor deposition tungsten silicide film) having a thickness of about 1.5 μm. , 13 indicate an Al wiring of about 1 μm, and 14 indicates a basic cell.

In the figure, two N-channel transistors (gate electrode 8, n + -type source / drain region 4, p-type impurity well region 2) and two P-channel transistors (gate electrode 8, p + -type source / drain region 5, n-type impurity) 2 shows a part of a gate array having a basic cell including a well region. (Two basic cells are shown.)
This gate array is formed by appropriately changing the wiring and the electrode contact window. In the plan view (a), the electrode contact window shows all the formable regions 11a, and
The wiring 13 is omitted for easy viewing of the drawing. As is clear from the plan view (a), there is no semiconductor substrate contact region (p + -type impurity well contact region and n + -type impurity well contact region) requiring a surface layout area, and an extremely highly integrated basic cell. Is configured. Part (b) of side sectional view in the channel length direction
As apparent from the above, an electrode which penetrates the n + type source region 4a and exposes a part of the p type impurity well region 2 is provided in a part of the n + type source region 4a to which the same voltage as that of the p type impurity well region is applied. A contact window 11b is formed, and the conductive film 12 buried in the electrode contact window 11b allows p
-Type impurity well region 2 and n + type source region 4a and Al wiring
13 and form a connection. This electrode contact window 11b
The size of the electrode contact window on the surface is exactly the same as the electrode contact window of the other area, and the electrode contact window of the same size allows the connection of all areas, so that the basic cell without the dedicated semiconductor substrate contact area Gate array can be configured. Therefore, high integration by forming a fine basic cell that does not require a surface layout area of a dedicated semiconductor substrate contact region is required.
In a part of the source region, an electrode contact window formed for connection with the source region is used, and a conductive film is buried in an electrode contact window of the same size which is extended until a part of the semiconductor substrate is exposed. The high integration and high performance due to the formation of the connection with the wiring body can be attained by the high speed and high yield due to the reduction of the wiring capacitance and the wiring resistance because the gate array composed of the fine basic cells can be formed. Multi-functionality can be realized by forming a large-scale semiconductor integrated circuit.

Next, an embodiment of a method of manufacturing a gate array according to the present invention will be described with reference to FIGS. 2 (a) to 2 (f) and FIG. Generally, a gate array is formed using multilayer wiring, but the present invention does not relate to multilayer wiring, and therefore, a manufacturing method using single-layer wiring will be described here.

FIG. 2 (a) By applying a normal technique such as an element isolation technique by LOCOS, an n-type impurity well region (not shown), a p-type impurity well region 2,
An n + type channel stopper region (not shown), a p + type channel stopper region 3, and a field oxide film 6 are formed.

FIG. 2 (b) Next, a gate oxide film 7 of about 18 nm is grown. Next, a polycrystalline silicon film of about 300 nm containing impurities is grown by a chemical vapor deposition method. Next, the gate electrode 8 is formed by selectively etching the polycrystalline silicon film using a resist (not shown) as a mask layer by using a normal photolithography technique. Next, the resist is removed.

2 (c) Next, arsenic is ion-implanted using a resist (not shown), a gate electrode 8 and a field oxide film 6 as a mask layer by using a normal photolithography technique, and n + type source / drain regions (4a, 4b, 4c). Next, the resist is removed. Then, boron is ion-implanted in the same manner to define a p + type source / drain region (not shown).

FIG. 2 (d) Next, unnecessary portions of the gate oxide film 7 are removed by etching. Next, the impurity blocking oxide films 9 and 60 of about 35 nm are formed.
A phosphor silicate glass (PSG) film 10 of about 0 nm is grown. Next, high-temperature heat treatment is performed to control the activation and depth of each impurity region.

FIG. 2 (e) Then, using a normal photolithography technique, using a resist (not shown) as a mask layer, a phosphor silicate glass (PSG) film 10, an impurity blocking oxide film 9, and n +
Part of the p-type impurity well region 2 and the p-type impurity drain region 4a is etched to form an electrode contact window 11b. Next, the resist is removed. (Although not shown, an electrode contact window for connecting the n-type impurity well region is also opened at the same time.) FIG. 2 (f) Next, the selective chemical vapor deposition tungsten silicide film 12
Is grown, and the electrode contact window 11b is buried flat.
Next, although not shown, a normal photolithography technique is used to selectively etch the phosphosilicate glass (PSG) film 10 and the impurity blocking oxide film 9 using a resist as a mask layer to form a normal electrode contact window. . Next, the resist is removed.

FIG. 1 Next, an Al film of about 1 μm is grown. Next, using an ordinary photolithography technique, the Al film is selectively etched using the resist as a mask layer to form an Al wiring 13. Next, the resist is removed to complete the gate array.

As described in the above embodiment, according to the gate array of the present invention, high integration by forming a fine basic cell that does not require a surface layout area of a dedicated semiconductor substrate contact region can be achieved by a part of the source region. By using an electrode contact window formed for connection with the source region and embedding a conductive film in an electrode contact window of the same size that is extended until a part of the semiconductor substrate is exposed, the connection between the semiconductor substrate and the wiring body is achieved. A large-scale semiconductor integrated circuit having a high speed and a high yield due to a reduction in wiring capacitance and wiring resistance because a gate array composed of fine basic cells can be formed because high integration and high performance due to the formation of a semiconductor device can be realized. Can be made multifunctional.

[Effects of the Invention] As described above, according to the present invention, in a highly integrated gate array having a fine basic cell, a basic cell formed in a structure without a dedicated semiconductor substrate contact region is provided, and In a source region to which the same voltage as that of the semiconductor substrate is applied, an electrode contact window that penetrates a part of the source region and exposes a part of the semiconductor substrate is connected to a wiring body through a flat buried conductive film. , A gate array formed in a structure to be connected to the semiconductor substrate is formed, so that high integration by forming a fine basic cell without forming a dedicated semiconductor substrate contact region can be realized (compared to the conventional example). , The basic cell area is about 75%.), And an electrode contact window and an electrode contact window of the same size penetrating the source region are buried in a part of the source region. Higher integration and higher performance due to the connection between the semiconductor substrate and the wiring body can be formed by the conductive film. Higher speed due to the lowering of wiring capacitance and wiring resistance because a gate array composed of fine basic cells can be formed. A large-scale semiconductor integrated circuit with high integration and high yield can be formed, so that multifunctionality can be realized. That is,
An extremely high speed, high performance, multifunctional and highly integrated gate array can be obtained.

[Brief description of the drawings]

1 (a) and 1 (b) are schematic views of one embodiment of the gate array of the present invention, and FIGS. 2 (a) to 2 (f) are process cross-sectional views of one embodiment of the manufacturing method of the gate array of the present invention. 3 (a) and 3 (b) are schematic diagrams of a conventional gate array. In the figure, 1 is a p- type silicon substrate, 2 is a p-type impurity well region, 3 is a p + type channel stopper region, 4 is an n + type source / drain region, and 4a is n + to which the same voltage as the p-type impurity well region is applied. The source region 4b is applied with a voltage different from that of the p-type impurity well region.
+ Type source region, 4c is n + type drain region, 5 is p + type source / drain region, 6 is field oxide film, 7 is gate oxide film, 8 is gate electrode, 9 is oxide film for impurity block, 10 is phosphosilicate glass (PSG) film, 11a is a region where an electrode contact window can be formed, 11b is an electrode contact window including connection to a semiconductor substrate, 12 is a buried conductive film (selective chemical vapor deposition tungsten silicide film), 13 is Al wiring, and 14 is Indicates a basic cell.

Claims (2)

(57) [Claims] A gate electrode provided on a semiconductor substrate via a gate insulating film; and a source / drain region formed of an impurity diffusion layer provided on the semiconductor substrate in self-alignment with the gate electrode. A basic cell having a structure in which a side surface of the source region and an upper surface of the semiconductor substrate are directly connected to the same potential in a part of the source region without providing the semiconductor substrate contact region is arranged in a matrix. Gate array featured. 2. An electrode contact window penetrating a part of the source region to which the same voltage as the semiconductor substrate is applied and exposing a part of the semiconductor substrate, a conductive film embedded in the electrode contact window, 2. The gate array according to claim 1, wherein a connection to the semiconductor substrate and the source region is formed by a wiring body connected to the conductive film.