JPS632368A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To elevate the density of a large-scale integrated circuit and increase working speed thereof by transmitting an input signal over a semiconductor region (e) under the state in which supply voltage is applied to a semiconductor region (a), a semiconductor region (d) is grounded and fixed voltage is applied to a semiconductor region (c). CONSTITUTION:A vertical type MISFET using a semiconductor region (e) as a gate electrode and a section along the inner wall of a groove in a semiconductor region (a) as a channel and a vertical type JFET employing a semiconductor region (c) as a gate electrode and a region, which forms one part of the semiconductor region (a) and the periphery of which is covered with the semiconductor region (c), as a channel are shaped, and the two FETs are connected in a semiconductor region (b), thus forming a signal inversion circuit using the vertical type MISFET as a drive transistor and the vertical type JFET as a load transistor. When input voltage is at a 'high level', the channel 11 in the vertical type MISFET 15 is brought to a conductive state, currents flow through a drain electrode 5-a channel region 13-a source electrode (a drain electrode) 6-channel regions 12, 11-a source electrode 7, and output voltage (a 'low' level) determined by the ON resistanc ratio of the vertical type MISFET 15 and the vertical type JFET is acquired as output voltage.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to vertical insulated gate field effect transistors (hereinafter referred to as vertical MISFETs) and vertical junction gate field effect transistors (hereinafter referred to as vertical JFETs). The present invention relates to a semiconductor device that realizes a signal inversion function by combining the following functions (referred to as "1") and a method for manufacturing the same.

[Conventional technology]

Conventionally, in order to configure the signal inversion function, nMOS, which is known to be advantageous for high density and high speed, has been used.
Taking the E/D configuration as an example, it has been realized with a structure as shown in FIGS. 7 and 8. That is, the enhancement type MOS transistor 71 is used as a drive transistor, and the depletion type MO3) transistor is used as a load transistor, which is connected as shown in the equivalent circuit shown in FIG. 7(c). When a signal is applied to the gate 77 of the EMO3T71, an inverted signal appears at the connection point between the source 74 of the transistor 70 and the drain 76 of the transistor 71.

[Problem that the invention seeks to solve]

However, in a configuration using such a planar MO3FET, the load transistor and the drive transistor occupy a large element area, and there is a limit to high density. Also, n
In the MOS E/D configuration, since the output terminal is connected to both the gates of the n-junction load transistor, the parasitic load capacitance is large and there is a limit to increasing the speed.

[Means for solving problems]

The semiconductor device of the present invention has been made in view of the above-mentioned problems, and includes a semiconductor region a of a first conductivity type, and a highly doped semiconductor region of the first conductivity type formed on the surface of the semiconductor region a.
a groove that surrounds at least a portion of the semiconductor region at the upper end and whose bottom reaches inside the semiconductor region a; and a second conductivity type semiconductor region C formed in the semiconductor region a at the bottom of the groove.
, a semiconductor region d formed in the semiconductor region C along the bottom of the trench, and a conductive layer e formed on the inner surface of the trench with an insulating film interposed therebetween. In addition, in order to realize such a structure, the method for manufacturing a semiconductor device of the present invention includes forming a semiconductor region of the second conductivity type on the main surface of the semiconductor region a of the first conductivity type, and then forming the semiconductor region all over the main surface of the semiconductor region a of the first conductivity type. A trench whose planar pattern is closed from the surface to the inside of the semiconductor region a is formed, and then an insulating layer is formed on the inner surface of the trench and the main surface of the semiconductor region a, and the semiconductor region a at the bottom of the trench is A semiconductor region C of the second conductivity type and a semiconductor region d of the first conductivity type are formed therein, and then a conductor layer e is formed on the insulating layer on the inner side surface of the trench.

[Effect]

By adopting such a configuration, a vertical MISFET with the semiconductor region e as the gate electrode and a channel along the inner wall of the groove of the semiconductor region a, and a vertical MISFET with the semiconductor region C as the gate electrode and a part of the semiconductor region a as the channel. A vertical JFET whose channel is a region surrounded by a semiconductor region C.
is formed. These two FETs are connected in the semiconductor region, and form a signal inversion circuit in which the vertical MISFET is used as a drive transistor and the vertical JFET is used as a load transistor. That is, a power supply voltage is applied to semiconductor region a, semiconductor region d is grounded, and semiconductor region C
With a fixed voltage applied to the semiconductor region e, the input signal is
By applying the inverted signal to the semiconductor region, an inverted signal can be extracted from the semiconductor region.

By using the manufacturing method of the present invention, such a semiconductor device can be realized.

〔Example〕

Hereinafter, the present invention will be described in detail along with examples.

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG.
1 is a plan pattern diagram, and FIGS. 3(b) and 3(c) are a BB′ cross-sectional view and a cc′ cross-sectional view, respectively, in FIG. 2(a). FIG. 2 is a circuit diagram showing an equivalent circuit of the semiconductor device of FIG.
ISFET15 and vertical JFE as load transistor
T16 is connected as shown.

1 is a semiconductor substrate containing n-type impurities, and constitutes a semiconductor region a. 2 is vertical MISFET15
The gate insulating film has a planar pattern formed all around the inner side surface of the groove 8 formed in the shape of a frame. 3 is vertical MI
A conductive layer e such as phosphorus-doped polycrystalline silicon, which is the gate electrode of the SFET 15 and is formed on the gate insulating film 2.
Consists of. 4 is the gate electrode of the vertical JFET 16;
? A semiconductor region C containing p-type impurities is formed in a semiconductor substrate l so as to surround the bottom of a semiconductor substrate l8. In addition,
This semiconductor region C does not necessarily have to be continuous along the groove 8, and may be partially divided as long as it is formed so as to substantially surround a region 13, which will be described later. 5
is the drain electrode of the vertical JFET 16, and is a semiconductor region containing n-type impurities.

6 is the source electrode of vertical JFET16 and vertical MISF
It also serves as the drain electrode of the ET 15 and consists of a semiconductor region containing n-type impurities.

7 is a source electrode of the vertical MISFET 15, which is a semiconductor region d containing n-type impurities formed in the semiconductor region C.
Consists of. 9 is an extraction electrode made of a conductor (polycrystalline silicon) containing p-type impurities, and 10 is an extraction electrode made of a conductor (polycrystalline silicon) containing n-type impurities. 11 and 12 are channel regions of the vertical MISFET 15, of which region 12 functions as an absorption region that weakens the voltage of the drain 6. 13 is vertical JFE
This is the channel region of T16.

In a semiconductor device with such a structure, vertical JFE71
The drain electrode 5 of 6 is the power supply terminal, and the vertical MISFET 15
The extraction electrode 10 of the source electrode 7 is the ground terminal, and the vertical type M
Drain electrode of ISFET15, that is, vertical JFET1
By using the source electrode 6 of the vertical MISFE 715 as an output terminal, the gate electrode 3 of the vertical MISFE 715 as an input terminal, and the extraction electrode 9 of the gate electrode 4 of the vertical JFET 16 as a fixed voltage application terminal, the vertical JFET 16 can be used as a load transistor or a DS A
(Diffusion Self-Aligned)
A signal inversion circuit using a vertical MI 5FET 15 as a drive transistor can be realized.

Next, the operation of this embodiment will be explained. Vertical JFET16
A fixed voltage is applied to the gate electrode 9, so that it is always in a conductive state. When the input voltage applied to the gate electrode 3 is the ground voltage (“low” level), the vertical MISFET 1
The channel 11 of the vertical JFET 16 is cut off, and the output voltage appearing at the drain electrode 6 of the vertical JFET 16 becomes a power supply voltage ("high" level) at the same potential as the semiconductor substrate 1. - On the other hand, when the input voltage is at the "high" level, the channel 11 of the vertical MrSFET 15 becomes conductive, and the "drain electrode 5 - channel region 13 - source electrode (drain electrode) 6 - channel region 12.11 - source electrode 7, a current flows, and an output voltage ("low" level) determined by the on-resistance ratio of the vertical MISFET 15 and the vertical JFET 16 is obtained.

That is, the signal inversion function can be realized by this embodiment.

Note that if the voltage applied to the extraction electrode 9, which is a fixed voltage application terminal, is zero or negative, all pn junctions (for example, the extraction electrode 9 and the source electrode 7, the gate electrode 4 and the semiconductor substrate 1, etc.) are reversed. Since it is in a bias state,
No wasteful through current occurs in the pn junction, which is effective in reducing power consumption.

Further, the semiconductor substrate 1 can also be a well region containing n-type impurities, in which case the power supply terminal can be taken from the semiconductor surface.

FIG. 3 shows another embodiment of the semiconductor device of the present invention, in which (a) is a plane pattern diagram, and (b) and (C) are B-B in FIG. 'Cross-sectional view, c-c' cross-sectional view. Further, FIG. 4 is a circuit diagram showing an equivalent circuit of the semiconductor device of FIG. 3. In this embodiment, the fixed voltage of the vertical MISFET 15 is set to the ground voltage in the embodiment shown in FIG. Metal or its silicide is buried so that it can be connected to both sides of the semiconductor region 7 containing impurities. In this embodiment, since the extraction electrodes from the semiconductor regions 4 and 7 at the bottom of 1B can be shared by the extraction electrode 14 as shown in the figure, higher density can be achieved. Note that the extraction electrode 14 is necessary for applying a voltage to the semiconductor region 4.7 at the bottom of the groove 8 when a narrow groove is used with the aim of increasing the density. This is not essential if a wide trench is used that allows connection with metal wiring.

The operation of this embodiment is similar to that of the embodiment shown in FIG.
When the input terminal is at “low” level, the vertical MISFET
When the channel 11 of No. 15 is disconnected and the output voltage becomes the same as the power supply voltage, that is, the "high" level, and the input terminal is at the "high" level, the channel 11 becomes conductive and the output voltage becomes "high".
Low level.

As can be seen from the above two embodiments, since the output terminal consists of only the small-area semiconductor region 6 containing n-type impurities, the parasitic load capacitance is lower than that of the output terminal of the conventional n-MOS E/D structure. Decrease. Further, since the gate pattern dimensions of the vertical MISFET can be determined without being subject to dimension restrictions in the lithography process, extremely fine dimensions can be set. Furthermore, since all four sides of the convex region surrounded by the frame-shaped square 8 can be used as a channel, the channel width can be set large. Therefore, the load driving force is improved and the device can be operated at extremely high speed.

Next, an embodiment of the method for manufacturing a semiconductor device of the present invention will be described. FIGS. 5(a) to 5(q) are process cross-sectional views showing the method for manufacturing the semiconductor device in FIG.
A portion corresponding to the B' cross-sectional view is shown.

First, in the processing step (a), element isolation regions A are formed. This element isolation process can be performed using any isolation method such as field isolation, selective oxidation isolation, oxide film buried isolation, trench isolation, etc.

In the treatment step (b), a thin silicon oxide film 21 of about 1100 nm is formed on the surface of the semiconductor substrate 1 by thermal oxidation, and arsenic or phosphorus ions are implanted to form an n-type surface diffusion layer 22. Note that this surface n-type layer 22 can also be formed after the gate electrode processing, which will be described later.

In the treatment step (c), a multilayer film of a 1100 nm silicon nitride film 23 and a 900 nm phosphosilicate glass film (PSG film) 24 is deposited by chemical vapor deposition (CVD).
A groove pattern is formed in the resist 25 by a lithography process. This groove pattern is formed to have a frame-like planar shape as shown in FIG. 1(a).

In the treatment step (d), using this resist pattern as a mask, the multilayer film consisting of the PSG film 24, silicon nitride film 23, and silicon oxide film 21 is subjected to reactive ion etching (RI).
The resist 25 is removed by etching according to step E).

In the treatment step (e), using the processed multilayer film as a mask, R
The substrate silicon 1 is etched using IE to form a trench B with a depth of approximately 1 μm.

In the treatment step (f), an oxide film 26 is deposited by a known deposition method such as CVD so that the trench is not completely filled.

In the treatment step (g), the oxide film 26 at the bottom of the groove is removed while leaving the oxide film 26 at the side surface of the groove by etchback using the anisotropy of RIE etching.

Next, using the trench side oxide film 26 as a protective film, p-type and n-type impurities are introduced only into the trench bottom by boron and arsenic ion implantation, thereby forming a p-type semiconductor region C and an n-type semiconductor region d. .

In the treatment step (h), after completely removing the PSG film 24 on the substrate surface and the oxide film 26 on the inner surface of the trench by wet etching, in order to remove contamination and damaged layers by RIE,
5Q the silicon surface inside the groove with a mixture of hydrofluoric acid and nitric acid.
Etch about nm.

In the subsequent treatment step (i), a silicon oxide film 27 that will become a gate insulating film is formed with a thickness of 10 to 20 nm by thermal oxidation, and a monosilane gas (SiH4) doped with phosphine (PH1) is formed.
) is used to form a polycrystalline silicon film 2 containing n-type impurities, which will become the gate electrode of the vertical MISFET.
Deposit 8. At this time, by controlling the mixing ratio of the raw material gases, the thickness is approximately 700 nm on the main surface of the silicon substrate and approximately 30 Q nm on the inner surface of the groove. In addition, in the part of the groove (not shown) that is formed parallel to the paper surface,
Polycrystalline silicon 28 is completely buried.

In the treatment step (j), the polycrystalline silicon film 28 is etched by an etch-back method using RIE to remove the polycrystalline silicon at the bottom of the trench while leaving the polycrystalline silicon on the main surface of the substrate. Note that in the groove portion where the polycrystalline silicon 28 is completely buried, that is, in the groove portion (not shown) formed parallel to the plane of the paper, only the upper polycrystalline silicon is etched, similar to the substrate surface.

In the treatment step (k), a silicon oxide film 2 is formed on the surface of the polycrystalline silicon 28 by wet oxidation at about 600 to 650°C.
form 9. At this time, by utilizing the difference in growth rate between the silicon substrate and the phosphorus-containing polycrystalline silicon film, a 153 nm silicon oxide film was formed on the surface of the polycrystalline silicon film.
A silicon oxide film of about 10 nm is formed on the surface of the silicon substrate at the bottom of the trench.

In the processing step (1), the silicon oxide film 29 at the bottom of the trench and the silicon substrate 1 are etched using the silicon oxide film 29 on the surface of the polycrystalline silicon as a mask using an etch bath using RIE. The etching depth at this time is set to be slightly greater than the depth of the n-type impurity implanted region d.

In the treatment step (m), a desired gate electrode is patterned by a lithography step, and the gate electrode is processed.

Subsequently, in a treatment step (n) and a treatment step (0), p-type polycrystalline silicon 30 and n-type polycrystalline silicon 31 for extraction electrodes for the n-type layer and the p-type layer are embedded in desired grooves through a lithography process. , perform patterning of the extraction electrode.

Finally, in the processing step (p) and the processing step (q), a PSG film 32 is formed as an insulating film between the eyebrows, and after reflowing, a contact hole is formed and processed, and a wiring metal 3 such as AI is formed.
3 is deposited, and a desired electrode wiring pattern is formed through a lithography and etching process.

FIGS. 6(a) to 6(g) show another embodiment of the method for manufacturing a semiconductor device of the present invention. In FIG. 5, the groove forming process was performed by etching. In contrast, in this embodiment, a groove pattern is formed on the surface of a semiconductor substrate through a lithography process, and the grooves are formed by selectively epitaxially growing silicon in other regions.

According to this embodiment, impurities can be easily introduced into the groove bottom.

In the treatment step (a), 1 is first applied to the surface of the substrate by thermal oxidation.
A thin silicon oxide film 21 of about 100 nm is formed. Subsequently, a polycrystalline silicon film 41 of about 1 μm is deposited using the CVD method, and the resist 2 is removed using a lithography process.
A groove pattern is formed in 5.

In the treatment step (b), using this resist pattern as a mask, the polycrystalline silicon 41 is etched by RIE, and p-type and n-type impurities are introduced only into the groove bottoms by boron and arsenic ion implantation. A semiconductor region C and an n-type semiconductor region d are formed.

Subsequently, in the processing step (C), the resist 25 is removed and P
The SG film 42 is deposited and the PSG film 4 is etched back only in the recessed region of the polycrystalline silicon corresponding to the groove pattern.
Embed 2.

In the treatment step (d), the polycrystalline silicon 41 and the thermal oxide film 21 thereunder are removed.

In the treatment step (e), silicon is selectively epitaxially grown to a thickness of about 1 μm in a region other than the groove region where the PSG film 42 remains.

In the processing step (f), element isolation regions A are formed. This element isolation process can be performed using any isolation method such as field isolation, selective oxidation isolation, oxide film buried isolation, trench isolation, etc. Next, arsenic or phosphorus ions are implanted into the semiconductor surface to form an n-type surface diffusion layer 22. Note that this surface n-type layer 22 can also be formed after the gate electrode is processed.

Subsequently, in the processing step (g), after removing the PSG film 42 in the trench by wet etching, the silicon surface in the trench is etched by about 50 nm using a mixed solution of hydrofluoric acid and nitric acid to form a trench B. The subsequent steps are similar to those shown in FIG.

The embodiments shown in FIGS. 5 and 6 are both methods for manufacturing the semiconductor device shown in FIG. By burying a high melting point metal or a silicide thereof into the groove, it is possible to produce a semiconductor device shown in FIG. 3 in which the lead electrodes from the semiconductor regions C and d at the bottom of the groove are shared.

In the above embodiments, an n-type conductive carrier was used as an example, but by reversing the polarity, a p-type conductive carrier semiconductor device can be obtained.

〔Effect of the invention〕

As explained above, the semiconductor device of the present invention includes a vertical MISFET in which the semiconductor region e is used as a gate electrode and a portion along the inner wall of the groove in the semiconductor region a is used as a channel;
A vertical JPET is formed in which the gate electrode is a part of the semiconductor region a and the region surrounded by the semiconductor region C is a channel, and these two FETs are connected in the semiconductor region A. , vertical MISFET
This is a signal inversion circuit that uses a vertical JFET as a drive transistor and a vertical JFET as a load transistor. That is, since the output terminal is only a small semiconductor region surrounded by a groove, the parasitic load capacitance is smaller than that of the output terminal of the conventional nMOS E/D structure. Furthermore, since the drive transistor is a MISFET with a vertical structure, the dimensions of the gate pattern can be determined without being constrained by dimensions in the lithography process, so that it can be set to extremely fine dimensions. Furthermore, since all four side surfaces of the convex region surrounded by the groove can be used as a channel, the channel width can be set large even within a limited device plane area. Therefore, the load driving force is improved and the device can be operated at extremely high speed. Therefore, the semiconductor device of the present invention is very effective in increasing the density and speed of large-scale integrated circuits. Moreover, according to the manufacturing method of the present invention, such an effective semiconductor device can be easily manufactured without using any special process.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a semiconductor device of the present invention;
FIG. 2 is an equivalent circuit diagram thereof, and FIG. 3 is a semiconductor device 1 of the present invention.
A configuration diagram showing another embodiment, FIG. 4 is an equivalent circuit diagram thereof,
FIG. 5 is a manufacturing process diagram showing one embodiment of the manufacturing method of the present invention, FIG. 6 is a manufacturing process diagram showing another embodiment of the manufacturing method of the present invention, and FIGS. 7 and 8 are signal inversion diagrams, respectively. nMOS E/D, which is a conventional semiconductor device with functions
FIG. 2 is an explanatory diagram showing the structure. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Gate insulating film of vertical MISFET, 3... Gate electrode of vertical MISFET, 4
... Gate electrode of vertical JFET, 5... Vertical JFE
Drain electrode of T, 6... Source electrode of vertical JFET and drain electrode of vertical MISFET, 7... Vertical M
Source electrode of ISFET, 8... Groove region, 9°10.
14...Extraction electrode, 11.12...Vertical MIS
Channel region of FET, 13... Channel region of vertical JFET, 15... Vertical MISFET, 16... Vertical JFET. Figure 3 Figure 5 Figure 6 (C1) (e) (b) (f
') (C) (9)

Claims (2)

[Claims] (1) A semiconductor region a of a first conductivity type, a highly doped semiconductor region b of the first conductivity type formed on the surface of the semiconductor region a, and a semiconductor region surrounding at least a part of the semiconductor region b at the top end and having a bottom part as a semiconductor region. a second conductivity type semiconductor region c formed in the semiconductor region a at the bottom of the trench; a semiconductor region d formed in the semiconductor region c along the trench bottom; A semiconductor device having a conductive layer e formed on the inner surface of the groove with an insulating film interposed therebetween. (2) forming a semiconductor region b of a second conductivity type on the main surface of the semiconductor region a of the first conductivity type, and forming a groove extending from the surface of the semiconductor region b to the inside of the semiconductor region a;
forming a groove having a planar pattern surrounding at least a portion of the semiconductor region a; forming an insulating layer on the inner surface of the groove and the main surface of the semiconductor region a; a step of forming a semiconductor region c of a first conductivity type within the semiconductor region c; and a step of forming a conductor layer e on the insulating layer on the inner surface of the trench. Method of manufacturing the device.