JPH02156664A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce an occupied area by a method wherein a MOS transistor constituting an FF circuit is formed of a pillar-shaped semiconductor layer formed by a groove on a semiconductor substrate, a gate electrode is formed on its side face via a gate insulating film and a source layer and a drain layer are formed individually at the bottom of the groove. CONSTITUTION:An NMOS sense amplifier part constituted of an FF circuit composed of two N-channel MOS transistors Q1, Q2 are formed; a P-type well region 2 is formed on an Si substrate 1; a plurality of pillar-shaped Si layers 41 to 44 protruding to be island-shaped by surrounding grooves 3 are formed in the region. Out of them, the transistor Q1 is formed in the layer 43 and the transistor Q2 is formed in the layer 2; in both cases, a gate insulating film 5 is applied to an outer periphery face of a layer 4; gate electrodes 6 composed of polycrystalline Si are formed on it. In addition, N<+> type layers 7, 8 are formed inside the grooves 3; bit lines 91, 92 forming a pair are arranged and installed on the layers 42, 43 via the N<+> type layer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to an improvement of a flip-flop circuit, which is one of the basic circuits of an integrated circuit.

(Prior Art) Semiconductor integrated circuits, especially integrated circuits using MOS transistors, are becoming increasingly highly integrated. With this increase in integration, the MOS transistors used therein are being miniaturized to the submicron region. As the MOS transistors constituting two circuits in a flip-flop circuit, which is a basic circuit of an integrated circuit, become smaller, various problems arise. First, when the gate size of an IMOS transistor becomes smaller, punch-through occurs between the source and drain due to the so-called short channel effect, making it difficult to suppress leakage current.

As a result, the leakage current of the flip-flop circuit increases,
cause malfunction. Second, the internal electric field of the MOS transistor becomes higher, and the hot carrier effect causes fluctuations in the threshold value and mutual conductance of the transistor.
Deterioration of transistor characteristics and circuit characteristics (operating speed,
operation margin, etc.). Thirdly, even if the gate length becomes shorter due to miniaturization, the gate width must be greater than a certain level in order to secure the necessary amount of current, and as a result, the area occupied by the flip-flop circuit must be made sufficiently small. difficult to do. For example, dynamic RAM
In (DRAM), memory cell miniaturization technology is making remarkable progress.

The area ratio of bit line sense amplifiers made up of flip-flops that detect cell information is increasing.
Miniaturization of the DRAM chip as a whole is being hindered.

In addition, in static RAM (SRAM), the memory cell itself (consisting of flip-flop circuits, so if the flip-flop circuit cannot be made smaller), SRAM
It is not possible to miniaturize the entire chip.

(Question 8 that the invention attempts to solve) As mentioned above, with conventional MOS integrated circuit technology.

There have been problems in that it is difficult to suppress leakage current in flip-flop circuits, reliability is lowered due to hot-carrier effects, and it is difficult to reduce the area occupied by the circuit due to the need to secure the necessary amount of current.

An object of the present invention is to provide a semiconductor device including a flip-flop circuit that solves such problems.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, a MOS transistor forming a flip-flop circuit is formed using a columnar semiconductor layer formed by a groove on a semiconductor substrate. The MOS transistor according to the present invention has a structure in which a gate electrode is formed on the side surface of a columnar semiconductor layer via a gate insulating film so as to surround it, and a source layer and a drain layer are formed on the top surface of the columnar semiconductor layer and the bottom of the groove, respectively. do.

(Function) In the structure of the present invention, the subthreshold characteristic of the MOS transistor is steep, and the subthreshold swing is extremely small. this is.

This is due to the strong controllability of the gate over the channel. Therefore, leakage current of the flip-flop circuit is effectively suppressed. Further, the side walls of the columnar semiconductor layer serve as the channel region, and there is no part where the channel region contacts the field region as in a normal planar MOS transistor. Therefore, the high electric field at the edge of the field does not affect the channel region.

Hot carrier effects are suppressed. In addition, the height of the columnar semiconductor layer can be increased without increasing the occupied area.

That is, the channel length can be increased by increasing the depth of the groove, which is also effective in suppressing the hot carrier effect. By suppressing this hot carrier effect, a highly reliable flip-flop circuit can be obtained. Furthermore, since the channel region is provided to surround the columnar semiconductor layer, a large gate width can be realized within a small occupied area.

This is especially effective in reducing the occupied area in parts that require a certain amount of current. Furthermore, since the depletion layer extends from the periphery of the columnar semiconductor layer toward the center, depending on the dimensions of the columnar semiconductor layer, the center may become depleted, or even if it is not depleted, the resistance becomes high, and the dependence on substrate bias is extremely small. characteristics are obtained. This also greatly contributes to improving the reliability of the circuit.

(Example) Hereinafter, nine embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view taken along the line AA of the bit line sense amplifier section of a DRAM according to an embodiment. FIGS. 2(a) and 2(b) show the structure of one of the MOS transistor sections.

FIG. 3 shows an equivalent circuit of the bit line sense amplifier.

Shown in FIG. 1 are two low-channel MOS transistors Q1. This is an NMOS sense amplifier section composed of a flip-flop circuit consisting of Q2. A p-type well 2 is formed in a silicon substrate 1, and within this p-type well 2, a plurality of columnar silicon layers 4 protrude in an island shape surrounded by a groove 3.
(4,.

42,...) are formed. The Mos transistor Ql uses one of the silicon layers 43.

Further, the other MOS transistor Q2 is constructed using another silicon layer 42, respectively.

That is, a gate insulator [5] is formed on the outer peripheral surface of the silicon layer 4, and a gate electrode 6 made of a polycrystalline silicon film is formed to surround this outer peripheral surface. Silicon layer 42.43
Drain on the top surface of and groove 3.

N-type layers 7 and 8 which serve as sources are formed.

Paired bit lines 9. ．． Reference numeral 92 designates the drains of the MOS transistors Q1+Q2, that is, the silicon layers 4□, 4. It is disposed in contact with the n+ diffusion layer 7 on the upper surface of the . MOS transistor Q
The gate electrode 6 of l.

In the layout of FIG. 1(a), the bit line 9□ is taken out to the top of the silicon layer 44 located diagonally below and to the right, and the bit line 9□ is brought into contact with the gate electrode 6 here.

M O:i The gate electrode 6 of the transistor Q2 is the first
Silicon layer 41 located diagonally on the upper left in the layout of figure (a)
It is taken out to the top, and the bit line 91 is brought into contact with this gate electrode 6 here. That is.

The columnar silicon layers 41 + 44 are not provided to form a MOS transistor, but are provided as pedestals to ensure bit line contact when connecting the bit line to the gate electrode. This is because by taking out the gate electrode on these silicon layers 41+44, the drain layer and the gate electrode contact portion become substantially on the same plane, and the depth of the contact hole of the bit line can be made uniform.

The source diffusion layer 8 formed at the bottom of the groove 3 has two MOS
Transistor Q1. This is a source node common to Q2, and the Aj7 wiring 10 is in contact with it. Although this common source node is not shown in FIG. 1, it is connected to the ground potential VSS via the activation MO3 transistor Q3, as shown in the equivalent circuit of FIG.

Although not shown in the figure, a PMOS sense amplifier using p-channel MOS transistors is formed along the same bit line pair with a similar structure and layout.

For comparison, a layout example of a conventional DRAM bit line sense amplifier using planar transistors according to the same design rules as this embodiment is shown in FIG. In this embodiment, the gate width W of the MOS transistor is a dimension surrounding the outer periphery of the columnar silicon layer 4 (see FIG. 2), and therefore the first
Compared to the conventional structure shown in FIG. 2, the chip area occupied by the gate width is particularly small, and the overall circuit area is approximately half that of the conventional structure.

Further, in this embodiment, the depletion layer 30 extends from the periphery of the silicon layer 4 toward the center, as shown in FIG. Therefore, by selecting the dimensions, impurity concentration, etc. of the silicon layer 4, the center of the silicon layer 4 can be depleted, and even if it is not completely depleted, the resistance of the silicon layer 4 when viewed in the vertical direction can be made sufficiently large. As a result, a flip-flop operation that is resistant to substrate noise can be obtained.

FIGS. 5(a) and 5(b) show the subthreshold characteristics of a conventional planar structure p-channel MOS transistor and an embodiment p-channel MOS transistor, respectively. Both channel width/channel length are W/L-8,0
a m is 10.8 μm. The relationship between channel width W and channel length in this embodiment is as shown in FIG. The gate oxide film is also 200, the measurement conditions are drain voltage Vd--0.05V, substrate bias is V
The voltage was changed to sub -0°2.4.6V. The transistor of this embodiment clearly has a steeper subthreshold characteristic than the conventional structure. Also that swing S
(-dVg/d(log Id)) is 98 mV/decade in the conventional structure, whereas it is very small at 72mV/decade in this embodiment. This shows that in this example, the controllability of the gate over the channel is strong. Due to this subthreshold characteristic, leakage current of the flip-flop circuit is suppressed in this embodiment, and malfunctions are prevented. As is clear from the comparison between FIGS. 5(a) and 5(b), in this embodiment, the substrate bias V s in the region where the drain current rises, that is, the region where channel inversion occurs.
There is no variation due to UB. This is the case in this embodiment as explained in FIG.

This is because the substrate region below the channel region is substantially electrically isolated from the substrate region below it. As a result, a bit line sense amplifier with strong resistance to substrate noise can be obtained.

FIGS. 6(a) and 6(b) show the n-channel MO in this embodiment.
Regarding S transistor, mutual conductance deterioration amount ΔGm/G when hot carrier effect stress is applied
0 and drain current deterioration amount ΔI ds/I ds
The stress time dependence of
It is shown in comparison with an S transistor. From this data, it can be seen that in the structure of this example, the amount of deterioration in characteristics is small and reliability is improved. This is due to the fact that the channel region is not in contact with the field as in conventional structures. A flip-flop circuit using such highly reliable transistors is advantageous in terms of operating speed and operating margin.

FIGS. 7(a) and 7(b) compare and show the static characteristics of transistors with a conventional structure and a structure of the present invention. Channel width W and channel length are W/L-4.0μm10.8a
m, the gate oxide film thickness is Tox-200, and the substrate bias voltage is Vsub-OV, and as shown in FIG. -12 μm2. As described above, even if the transistor area of the present invention is 1/2 or less, the same drain current as that of the conventional structure can be obtained, and the device has high driving ability.

Therefore, according to this embodiment, it is possible to obtain a highly reliable DRAM bit line sense amplifier that occupies an extremely small area per circuit, has low leakage current, and is not affected by hot carrier effects or substrate noise.

An embodiment in which the present invention is applied to an SRAM will be described below. M
In a typical SRAM using OS transistors, the memory cells are constructed by flip-flops, and the MOS transistors constituting the flip-flops can have a vertical structure using columnar silicon as in the above embodiment. can.

FIG. 9 is a plan view of the SRAM cell portion of the embodiment,
FIG. 10 shows its equivalent circuit. By forming grooves in the silicon substrate in the same manner as in the previous embodiment, columnar silicon layers 11 (111, 112 degrees, . . . ) are formed in an array. Transfer gate MOS transistors T1 and T2 are formed using silicon layers 111 and 112. Its structure is similar to the previous embodiment, with a drain diffusion layer formed on the upper surface of the silicon layer and a source diffusion layer formed in the groove.

A gate electrode 12 □ made of a polycrystalline silicon film is formed to surround the silicon layer 11 .

Gate electrode 12. are two MOS transistors T, ,T
Continuously patterned about 2.

Configures word line WL. One driver MOS transistor T3 is formed using the silicon layer 113.

The other driver MOS transistor T4 is formed using the silicon layer 116, respectively.

The structure of these transistors is also similar to the others.

The gate electrode 12□ of the MOS transistor T3 is.

It extends to the silicon layer 114 as a pedestal.

A polycrystalline silicon wiring 132 connecting the drains of MOS transistors T2 and T4 is brought into contact with the gate electrode 122 here. Similarly, MOS transistor T4
The gate electrode 123 is.

It extends to the silicon layer 115 as a pedestal.

A polycrystalline silicon wiring 131 connecting the drains of MOS transistors T1 and T3 is brought into contact with the gate electrode 123 here. Drain wiring 13. ．． 132 are high-resistance polycrystalline silicon films 1 as load resistors, respectively.
41r 142, it is connected to a power supply (Vcc) wiring 133 made of a polycrystalline silicon film. Data lines (D, D) 151, 152 made of AI film and ground (
Vs s ) line 153 is shown cut in the middle.

Data line 15. ．． 152 are arranged in contact with the source diffusion layer formed in the groove of the MOS transistor T I + T 2 through contacts [161 and 162, respectively. The ground line 153 is connected to the MOS transistor T.
3 r T4 is provided in contact with the source diffusion layer common to T4 through a contact portion 163 . A region 17 surrounded by a dashed line in the figure indicates an element region.

For comparison, a conventional SRAM using planar transistors
FIG. 13 shows an example of the cell layout.

The gate electrodes 211 of the transfer gate MO3 transistors T1 and T2 are arranged continuously to form a word line WL. The gate electrode 212 of one of the driver MOS transistors T3 is in direct contact with the diffusion layer of the MOS transistor T2 at the shaded area 221, and connected to the VCC wiring 212 through the high-resistance polycrystalline silicon film 231 serving as a load.
It is connected to the. The gate electrode 213 of the other driver MO3 transistor T4 makes direct contact with the diffusion layer of the MOS transistor T1 at the shaded area 222, and connects to VCC through the high resistance polycrystalline silicon film 232 serving as the load.
It is connected to the wiring 24. Data line 25. ．． 252 are contact portions 26. , 262 make contact with the diffusion layer of MOS transistors T1+T2, and the ground line 2
53 is a contact portion 263, which is a MOS transistor T3+
It is in contact with the common source diffusion layer of T4. A region 27 surrounded by a dashed line in the figure indicates an element region.

This embodiment also allows the SRAM cell to be made smaller. However, in the case of an SRAM cell, there is no need for a gate width as large as that of a DRAM bit line sense amplifier. Therefore, the effect of reducing the occupied area is not as great as in the case of the bit line sense amplifier described above. Other effects are obtained in the same manner as in the previous embodiment.

Driver MO of the flip-flop shown in the above embodiment
The S transistor uses the top surface of the columnar silicon layer as the drain, because it is easier and more reliable to contact the node wiring that handles data signals in the process compared to using the drain in the diffusion layer in the deep trench. It is.

However, this is not an essential condition in the present invention, and it is also possible to conduct wiring using the upper surface of the columnar silicon layer as a source. In this case, the way the depletion layer grows during operation of the MOS transistor is as shown in FIG. 11, which is different from that shown in FIG. 4. That is, the depletion layer 30 extending from the trench-side diffusion layer 8 used as a drain provides a floating state electrically isolated from the p-type head region below even if the columnar silicon layer 4 is not depleted. Specifically, for example, if the impurity concentration of the columnar silicon layer 4 is 3xlO''/cI11', the width is 1.um, and the gate oxide film is 120 layers, these conditions are easily satisfied. The gate MOS transistor T 1 + 72 is
In operation, the drain and source are not fixed, so either the state shown in FIG. 4 or the state shown in FIG. 11 occurs.

In the embodiment, a case was explained in which a high resistance polycrystalline silicon load was used as the SRAM, but the SRAM uses a completely 0 MO8 type flip-flop.

SRAM with E/E type flip-flop.

The present invention can be similarly applied to SRAMs having E/D type flip-flops. Furthermore, the present invention can be applied to various MOS integrated circuits using flip-flops as well as DRAM sense amplifiers and SRAM cells.

[Effects of the Invention] As described above, according to the present invention, by using a vertically structured MOS transistor whose channel is the side wall of a columnar semiconductor layer, it is possible to obtain a flip-flop circuit with a significantly reduced occupied area. . Furthermore, since the channel region is not in contact with the field, a flip-flop circuit with strong resistance to hot carrier effects and excellent single-circuit characteristics can be obtained. Furthermore, leakage current can be significantly reduced by improving subthreshold characteristics.

[Brief explanation of the drawing]

1(a) and 1(b) are a plan view showing a DRAM bit line sense amplifier circuit according to an embodiment of the present invention and its A-A cross-sectional view, and FIGS. 2(a) and 2(b) are one thereof. Figure 3 is an equivalent circuit diagram of the bit line sense amplifier, and Figure 4 is the same (showing how the depletion layer grows during operation of the MOS transistor). Figures. Figures 5(a) and 5(b) are diagrams showing the subthreshold characteristics of the p-channel MOS transistor of the example in comparison with the conventional structure, and Figures 6(a) and (b) are also characteristics due to hot carrier effect stress. Figures 7(a) and 7(b) show the static characteristics compared with the conventional structure, and Figure 8 shows the area of the transistor of the present invention prototyped for testing. FIG. 9 is a plan view showing an SRA cell according to another embodiment of the present invention, and FIG. 10 is a diagram showing a comparison with a conventional structure.
The figure shows the equivalent circuit diagram, Figure 11 shows how the depletion layer grows when the trench side diffusion layer is used as the drain, corresponding to Figure 4, and Figure 12 shows the conventional DRAM bit line sense amplifier. FIG. 13 is a plan view showing an example of the structure of a conventional SRAM cell. 1... Silicon substrate, 2... P-type well, 3...
groove. 4... Columnar silicon layer, 5... Gate oxide film, 6...
...Gate electrode, 7, 8...n-type drain, source diffusion layer, 9...bit line, 10...common source wiring. 11... Columnar silicon layer, 12... Gate electrode. 13... Polycrystalline silicon wiring, 14... High resistance polycrystalline silicon load, 15... Al wiring, 16... Contact portion, 17... Element region. Applicant's agent Patent attorney Takehiko Suzue (a) Fig. 2 (b) Fig. Embodiment d of Example d (a) Fig. No. 5 Bundle Ida U Tukyouiro 17! J 5X2.412μm” Fig. 8 SS Fig. 10 Fig. 11

Claims (3)

[Claims] (1) In a semiconductor device including a flip-flop circuit configured using a MOS transistor, the MOS transistor constituting the flip-flop circuit has a gate insulated so as to surround the side surface of a columnar semiconductor layer formed by a groove in a semiconductor substrate. 1. A semiconductor device having a structure in which a gate electrode is formed through a film, and source and drain layers are formed on the top surface of the columnar semiconductor layer and the bottom of the trench, respectively. (2) In a dynamic semiconductor memory device in which a flip-flop circuit configured using MOS transistors is used as a bit line sense amplifier, the MOS transistors constituting the flip-flop circuit are formed in a columnar semiconductor layer formed by a groove in a semiconductor substrate. A dynamic semiconductor having a structure in which a gate electrode is formed via a gate insulating film so as to surround the side surface of the columnar semiconductor layer, and a source layer and a drain layer are formed on the top surface of the columnar semiconductor layer and the bottom of the groove, respectively. Storage device. (3) In a static semiconductor memory device in which a memory cell is a flip-flop circuit constructed using a MOS transistor, the MOS transistor constituting the flip-flop circuit is formed on a side surface of a columnar semiconductor layer formed by a groove in a semiconductor substrate. A static semiconductor memory device having a structure in which a gate electrode is formed surrounding the columnar semiconductor layer via a gate insulating film, and a source layer and a drain layer are respectively formed on the top surface of the columnar semiconductor layer and the bottom of the groove. .