JPH07193086A - Junction-type field effect semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a junction-type field effect semiconductor device which facilitates a fine structure and a high breakdown voltage without providing an element isolation region and its manufacturing method. CONSTITUTION:A gate (p<+>-type diffused layer 14), a source (n<+>-type diffused layer 12) and a drain (n<+>-type diffused layer 13) are buried in an insulating layer (SiO2 layer 11) as a base layer and, further, a channel layer (n-type Si layer 16) is formed so as to cover the layers 14, 12 and 13. The insulating layer itself functions as a region isolation layer which isolates the gate, source and drain from each other and, further, functions as an element isolation region which isolates the layers 14, 12 and 13 and other elements from each other. With this constitution, it is not necessary to provide an additional element isolation region for the element isolation and the region and element isolation like the conventional constitution and, further, a sufficiently high breakdown voltage can be obtained. Moreover, as the additional element isolation region is not necessary, a minute device size can be realized easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly to a junction field effect semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art There is a so-called field effect transistor (FET) as a voltage control type transistor. This transistor controls carriers that move in the channel existing between the source and drain by the voltage applied to the gate.However, this transistor has a higher input impedance than other types of transistors, so・
In addition to being used in AC high input impedance circuits, it is also widely used in various amplifiers by taking advantage of its wide frequency characteristics.

The FET is a junction type FET (hereinafter referred to as JF
ET), MOS type FET, thin film FET, and the like. Here, the junction type FET will be described.

FIG. 5 shows a cross-sectional structural view of a conventional n-channel J-FET. In this figure, p ⁺ type Si
On the (silicon) substrate 21, an n-type epitaxial Si layer 32 to be a channel portion is formed, and p ⁺ diffusion layers 33 and 34 for element isolation from other epitaxial Si layers (not shown). Are formed. On the surface side of the epitaxial Si layer 32, ap ⁺ type diffusion layer 37 serving as a surface gate is formed, and an n ⁺ type diffusion layer 35 serving as a source and an n ⁺ type diffusion layer 36 serving as a drain are formed on the surface side.
^{The +} type diffusion layer 37 is formed so as to sandwich it. The p ⁺ type diffusion layer 37, which is the surface gate, and the p ⁺ type Si substrate 21 are short-circuited at the side surface.

[0005]

In the conventional J-FET having such a structure, it is difficult to miniaturize the device for the following reasons.

That is, in the above structure, the element isolation diffusion layers (p ⁺ diffusion layers 33 and 34) for isolating the channel portion from other semiconductor devices are indispensable, and J-F is correspondingly required.
The chip size of ET becomes large.

Further, in the case of the structure shown in FIG. 5, J-FE
The breakdown voltage of the T element is mainly the impurity concentration n of the epitaxial Si layer 32, and the n ⁺ type diffusion layer 36 and the p ⁺ type S.
Depending on the distance h from the i substrate 21, the breakdown voltage can be increased by increasing the impurity concentration n or increasing the distance h. However, when the impurity concentration n is increased, the resistance of the channel portion is increased and the parasitic capacitance is also increased, so that the device characteristics are deteriorated. Further, in order to increase the interval h, the epitaxial S
If the i layer 32 is thickened, the p ⁺ type diffusion layer 37 serving as a gate is formed.
Since the channel width d (usually 1 μm) in the lower region has a large influence on the device characteristics, it is necessary to deepen the depth of the p ⁺ type diffusion layer 37 and set the channel width d to an appropriate value. . However, if the p ⁺ type diffusion layer 37 is deeply formed, the lateral diffusion of this layer also becomes large. To solve this, for example, Japanese Patent Laid-Open No. 57-15471 discloses source / drain diffusion layers (n ⁺ type diffusion layers 35, 3).
There has been proposed a method of increasing the distance h without decreasing the depth of the gate (p ⁺ type diffusion layer 37) by decreasing the depth of 6). In this method as well, the element is miniaturized. In order to do so, the impurity concentration n of the epitaxial Si layer 32 must be increased, and as a result, the above-mentioned problem, that is, the increase in the resistance of the channel portion and the increase in the parasitic capacitance, deteriorates the device characteristics.

The present invention has been made to solve the above problems, and it is an object of the present invention to obtain a junction type field effect semiconductor device having a high breakdown voltage, which can be easily miniaturized, without providing an element isolation region. To aim.

[0009]

According to another aspect of the present invention, there is provided a junction field effect semiconductor device comprising: (i) an insulating layer serving as a base layer; and (ii) a high-performance embedded in the insulating layer and functioning as a gate. A first conductivity type diffusion layer having an impurity concentration, and (iii) embedded in the insulating layer with the first conductivity type diffusion layer interposed between the first conductivity type diffusion layer and the first conductivity type diffusion layer with a predetermined distance therebetween. The two high-impurity-concentration second-conductivity-type diffusion layers, and (iv) the first-conductivity-type diffusion layer and the two second-conductivity-type diffusion layers are provided so as to cover the first and second diffusion layers.
It is characterized by comprising a conductive type diffusion layer and a second conductive type diffusion layer which are connected to each other and which functions as a channel layer and has a low impurity concentration second conductive type diffusion layer.

According to a second aspect of the present invention, there is provided a method for manufacturing a junction field effect semiconductor device, comprising: (i) forming three recesses on an insulating layer as a base layer; and (ii) forming a semiconductor material in the recesses. A step of filling, (iii) a step of injecting an impurity into the semiconductor material filled in the central concave portion of the three concave portions to form a high-concentration first-conductivity-type diffusion layer functioning as a gate, (iv) ) A step of injecting an impurity into the semiconductor material filled in the two recesses on both sides of the three recesses to form a second-conductivity-type diffusion layer having a high impurity concentration and functioning as a source or a drain, respectively. Forming a low-concentration second-conductivity-type diffusion layer that functions as a channel layer so as to cover the first-conductivity-type diffusion layer and the two second-conductivity-type diffusion layers. .

[0011]

In the junction field-effect semiconductor device according to the first aspect of the present invention, the insulating layer itself as a base layer has a gate (first conductivity type diffusion layer having a high impurity concentration) and a source or a drain (two high impurity concentration). Second diffusion layer of the second conductivity type), and also functions as an element isolation layer for isolating the element from other elements. On the other hand, the low impurity concentration second conductivity type diffusion layer provided so as to cover these functions as a channel.

[0012]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows an n-channel junction field effect transistor according to an embodiment of the present invention. This J-FET has an insulating SiO ₂ film as a base layer.
It has a layer 11. A p ⁺ type diffusion layer 14 as a gate is embedded in the SiO ₂ layer 11, and an n ⁺ type diffusion layer 12 as a source and an n ⁺ type diffusion layer 13 as a drain are embedded with the layer sandwiched therebetween. ing. An n-type Si layer 16 forming a channel portion is formed on the three diffusion layers and the SiO ₂ layer 11 so as to cover them.

According to this structure, since the base layer itself for forming the J-FET element is the insulating layer (SiO ₂ layer 11), it is possible to separate it from other elements, which is conventionally required. Element isolation region (p ⁺ diffusion layers 33, 3 in FIG. 5)
The element isolation breakdown voltage can be sufficiently increased without specially providing 4).

Further, since the n ⁺ type diffusion layers 12 and 13 as the source, the drain and the gate and the p ⁺ type diffusion layer 14 are all separated by the insulating SiO ₂ layer 11, there is a gap between the regions in the device. It is possible to secure a sufficiently large withstand voltage.

Although the size of each region is limited by the etching accuracy of the SiO ₂ layer 11 and the alignment accuracy of the lithography process, for example, the sizes of the n ⁺ type diffusion layers 12 and 13 and the p ⁺ type diffusion layer 14 are, for example. The buried depth and each width should be about 1 μm, the source-gate spacing and the gate-drain spacing should be about 0.5 μm, and the thickness of the n-type Si layer 15 should be about 0.4 μm. Is possible.

Next, a method of manufacturing the J-FET having the structure shown in FIG. 1 will be described with reference to FIGS.

[Step 1]: SiO ₂ substrate or S
This is prepared a wafer to form a SiO ₂ layer and SiO ₂ layer 11 as a base layer i crystal substrate, the SiO ₂
Trench structures 17 to 19 for filling the source, drain, and gate are formed in the layer 11 by etching (FIG. 2A). Here, the depth and width of each trench are both about 1 μm, and the mutual distance is 0.5 μm.

[Step 2]: S formed in step 1
After depositing Si on the trench structure surface side of the iO ₂ layer 11, Si other than the trench structure portion is removed by etchback. Thereby, the trench structures 17-1
9 is filled with Si to form three Si regions 22 to 24 (FIG. 2B).

[Step 3]: Of the Si regions 22 to 24, only the central Si region 24 (FIG. 2B) to be the gate is masked on its surface with a photoresist having a window.
Boron is ion-implanted to form the p ⁺ type diffusion layer 14 as a gate (FIG. 2C).

[Step 4]: The surface of the Si regions 22 and 23 (FIG. 2C) to be the source and drain is masked with a photoresist having an open window, and phosphorus is ion-implanted to form the source and drain. N ⁺ type diffusion layers 12 and 1
3 is formed (FIG. 3A).

[Step 5]: p ⁺ type diffusion layers 14, n ⁺ type diffusion layers 12, 13 and S formed in steps 2 to 4
The n-type Si layer 15 is formed so as to cover the entire surface of the iO ₂ layer 11.
Are formed by deposition (FIG. 3B).

[Step 6]: n formed in Step 5
A part of the mold Si layer 15 that covers the source, the gate, and the drain is left, and the other unnecessary parts are removed by patterning by photoetching to form a channel part 16 (FIG. 3C). After that, the n ⁺ type diffusion layer 12,
Source contacts, gate contacts, and drain contacts are provided on the p-type diffusion layer 14 and the p ⁺ -type diffusion layer 14, respectively, and the wiring, the interlayer film, and
Processes such as passivation film formation are performed.

By the above steps, the J-FET having the structure shown in FIG. 1 is manufactured.

In this embodiment, the n-channel type is shown in which the gate is the p ⁺ type diffusion layer, the source and the drain are the n ⁺ type diffusion layers, and the channel layer 16 is the n type Si layer. As shown in FIG. 4, the gate is an n ⁺ type diffusion layer 14 ′, the source and the drain are p ⁺ type diffusion layers 12 ′,
13 'and the channel layer 16' is a p-type Si layer, it is possible to configure a p-channel junction field effect transistor.

[0026]

As described above, according to the present invention,
Since the gate layer, the source layer, and the drain layer are embedded in the insulating layer as the base layer, and the channel layer is formed on these, the insulating layer itself functions as a region separation layer that separates the gate, source, and drain. At the same time, it also functions as an element isolation layer that isolates it from other elements. Therefore, it is possible to perform the element isolation and the element internal area isolation without specially providing the element isolation area as in the conventional case, and it is possible to secure a sufficiently large breakdown voltage. Further, since no special element isolation region is required, there is an effect that the device size can be easily reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part showing a junction field effect transistor according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a method of manufacturing the junction field effect transistor of FIG.

FIG. 3 is an explanatory diagram following the process of FIG. 2 showing the method of manufacturing the junction field effect transistor of FIG. 1.

FIG. 4 is a sectional view of an essential part showing a junction field effect transistor according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view of essential parts showing a conventional junction field effect transistor.

[Explanation of symbols]

11 SiO ₂ layer (insulating layer) 12 n ⁺ type diffusion layer (source) 13 n ⁺ type diffusion layer (drain) 14 p ⁺ type diffusion layer (gate) 16 n type Si layer (channel layer) 12 ′ p ⁺ type diffusion Layer (source) 13 'p ⁺ type diffusion layer (drain) 14' n ⁺ type diffusion layer (gate) 16 'p type Si layer (channel layer)

Claims (2)

[Claims] 1. An insulating layer as a base layer, a first-conductivity-type diffusion layer having a high impurity concentration, which is embedded in the insulating layer and functions as a gate, and a predetermined distance from the first-conductivity-type diffusion layer. Two high-impurity-concentration second-conductivity-type diffusion layers embedded in the insulating layer with a first-type conductivity-diffusion layer sandwiched therebetween, each of which functions as a source or a drain; A second-conductivity-type diffusion layer that covers the second-conductivity-type diffusion layer and connects the first-conductivity-type diffusion layer and the second-conductivity-type diffusion layer to each other and functions as a channel layer. A junction-type field effect semiconductor device, comprising: 2. A step of forming three depressions on an insulating layer as a base layer, a step of filling the depressions with a semiconductor material, and a step of filling the semiconductor material filled in the central depression of the three depressions with impurities. Implanting to form a high-concentration first-conductivity-type diffusion layer that functions as a gate, and implanting impurities into the semiconductor material filled in two recesses on both sides of the three recesses to form a source or a drain, respectively. Forming a high-concentration second-conductivity-type diffusion layer that functions as a channel, and a low-impurity-concentration second layer that functions as a channel layer to cover the first-conductivity-type diffusion layer and the two second-conductivity-type diffusion layers. 2. A method of manufacturing a junction field effect semiconductor device, comprising the step of forming a two-conductivity-type diffusion layer.