JP2926723B2 - Complementary semiconductor device - Google Patents

Description

The present invention relates to a transistor structure of a complementary insulated gate field effect transistor integrated circuit (CMOS IC).

[Conventional technology]

CMOSIC is a P-channel MOS field-effect transistor (M
Since the OS field-effect transistor and the N-channel transistor are formed on the same substrate, a parasitic thyristor structure is formed inside. CMOSIC
In this case, a phenomenon (so-called latch-up) occurs in which the parasitic thyristor is triggered by external noise or the like and the power supply terminals are in a low impedance state. Various structures and manufacturing methods have been devised for improving the latch-up withstand capability. Among them, a method using an epitaxial substrate is the most common and has a great effect.

FIG. 5 is a cross-sectional view of a conventional CMOS IC using an N-type epitaxial substrate. An N ^- epitaxial layer 12 is formed on a high-concentration N ⁺ substrate 11, and a P-channel transistor is
An N-channel transistor is formed in the P well 2 formed in FIG. According to this structure, by using a high-concentration substrate, the parasitic resistance due to the substrate can be reduced to 1/100 or less of that without using an epitaxial substrate, so that latch-up does not occur.

[Problems to be solved by the invention]

As described above, it is possible to greatly improve the latch-up withstand capability by using an epitaxial substrate. However, at present, an epitaxial substrate is very expensive, which is two to three times as large as a normal substrate, and the pellet price is increased. Results. In addition, the epitaxial substrate has a defect that the yield of pellets is reduced due to the existence of surface defects associated with epitaxial growth called slip and mound.

[Means for solving the problem]

The complementary semiconductor device of the present invention is a semiconductor region of one conductivity type, an element isolation region provided to sandwich a part of the semiconductor region to separate a part of the semiconductor region from another region, A source of the second conductivity type formed in the partial region;
A drain diffusion layer; and a buried diffusion layer of one conductivity type provided below the source / drain diffusion layer. The buried diffusion layer is provided below a channel formation region determined by the source / drain diffusion layer. Except for that, it is formed to extend from under the source / drain diffusion layer to under the element isolation region.

According to the present invention, the latch-up withstand capability can be significantly improved at a low cost as a result of only changing a few steps to the conventional manufacturing method without using an epitaxial substrate.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of one embodiment of the present invention, wherein 1 is an N ⁻ substrate, 2 is a P well, 3 is an N ⁺ channel stopper, 4 is a P ⁺ channel stopper, 5 is a gate electrode, and 6 is P ⁺ A source / drain diffusion layer, 7 is an N ⁺ buried diffusion layer, 8 is an N ⁺ source / drain diffusion layer, 9 is a P ⁺ buried diffusion layer, and 10 is a metal wiring. N ^-
Formation of a P-well 2 in a substrate 1, channel stoppers 3, 4,
The formation of the gate electrode 5 and the formation of the source / drain diffusion layers 6 and 7 may be the same as the method according to the prior art.

The N ⁺ buried diffusion layer 7 in the P-channel transistor and the P ⁺ buried diffusion layer 9 in the N-channel transistor, which are the features of the present invention, can form the gate electrode 5 before the formation of the source / drain diffusion layers 6 and 8. Before or after. However, the buried diffusion layers 7, 9 need to be formed deeper than the source / drain diffusion layers 6, 8, and burying processing by a slight heat treatment is required.

It is desirable that the concentration of the buried layers 7 and 9 be as high as possible in order to increase the latch-up withstand capability. However, since the transistor breakdown voltage decreases, it is necessary to set the concentration in consideration of the operating voltage of the CMOS IC. In this embodiment, N _{− of} 1 × 10 ¹⁵ cm ⁻³ is used.
5 × 10 ¹³ for P well 2 with a substrate surface concentration of 8 × 10 ¹⁵ cm ^-3
The N-type diffusion layer 7 is implanted with 4 × 10 ¹³ by ion implantation of cm ⁻² phosphorus.
A P ⁺ diffusion layer 9 was formed by ion implantation of cm ⁻² boron. After the ion implantation for forming the buried diffusion layers 7 and 9,
Heat treatment at 100 ° C for 90 minutes. The transistor breakdown voltage is about 10 for both P-channel and N-channel transistors.
V is getting.

FIG. 3 shows the power supply voltage / current characteristics of the CMOS IC according to the embodiment having the structure shown in FIG. 2. As shown in FIG. 4, the latch-up was performed at 75 mA without the latch-up countermeasure. Confirmed that no up occurs.

FIG. 2 is a sectional view of another embodiment of the present invention. In FIG. 1, the channel stopper and the buried diffusion layer are formed separately, but the buried diffusion layers 7, 9 also serve as the channel stoppers 3, 4, so that the manufacturing process can be simplified. is there.

In the embodiment of the present invention, buried diffusion layers are formed in both the P-channel transistor and the N-channel transistor to prevent latch-up. However, in the case where only one of the buried diffusion layers can be inserted for manufacturing reasons or the like. However, it has been confirmed that the latch-up withstand capability is at least twice the latch-up starting current.

〔The invention's effect〕

As described above, in the present invention, by forming a buried diffusion layer of the opposite conductivity type to the source / drain diffusion layer in the source / drain diffusion layer region, the latch-up withstand capability can be greatly increased without using an expensive epitaxial substrate. Could be improved.

[Brief description of the drawings]

1 is a longitudinal sectional view of one embodiment of the present invention, FIG. 2 is a longitudinal sectional view of another embodiment according to the present invention, FIG. 5 is a longitudinal sectional view of the prior art, and FIG. FIG. 4 is a power supply voltage / current characteristic diagram in the embodiment without a countermeasure against latch-up. 1 ... N ^- substrate, 2 ... P well, 3 ... N ⁺ channel stopper, 4 ... P ⁺ channel stopper, 5 ... Gate electrode,
6,9 …… P ⁺ diffusion layer, 7,8 …… N ⁺ diffusion layer, 10 …… metal wiring,
11 …… N ⁺ substrate, 12 …… N ^- epitaxial layer.

Claims (1)

(57) [Claims] A semiconductor region of one conductivity type; an element isolation region provided to sandwich a part of the semiconductor region from another region so as to separate the semiconductor region from another region; A second conductivity type source / drain diffusion layer formed in the region,
And a buried diffusion layer of one conductivity type provided below the source / drain diffusion layer, wherein the buried diffusion layer is a source / drain diffusion layer excluding a lower part of a channel formation region determined by the source / drain diffusion layer. A complementary semiconductor device extending from under a drain diffusion layer to under an element isolation region.