JPH02111065A - Complementary semiconductor device - Google Patents

Abstract

PURPOSE:To improve latchup strength by forming an opposite-conductive type buried diffusion layer to a source.drain diffusion layer on a source.drain diffusion layer region. CONSTITUTION:An N<+> buried diffusion layer 7 in a P-channel transistor and a P<+> buried diffusion layer 9 in an N-channel transistor may be formed even before forming a gate electrode 5 provided that it is before forming the source.drain diffusion layers 6 and 8. However, the buried layers 7 and 9 are formed deeper than the source.drain diffusion layers 6 and 8 by heat treatment. Further, concentration of the buried layers 7 and 9 is desirably to be as high as possible, but on the other hand transistor pressure-tightness drops so that concentration is to be set up in consideration of operation voltage of a complementary insulated gate FET integrated circuit. Thereby, a latchup strength can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transistor structure of a complementary insulated gate field effect transistor integrated circuit (0MO3I C').

[Conventional technology]

Since the 0MO8IC has a P-channel MO8 field effect transistor (hereinafter referred to simply as a MO3 field-effect transistor) and an N-channel transistor formed on the same substrate, a parasitic thyristor structure is formed inside. In the 0MO8IC, this parasitic thyristor is triggered by external noise or the like, resulting in a phenomenon in which the impedance between the power supply terminals becomes low (so-called latch-up). Various structures and manufacturing methods have been devised to improve this latch-up resistance, but among these, the method using an epitaxial substrate is the most common and highly effective.

FIG. 5 is a cross-sectional structural diagram of a conventional 0MO8IC using an N-type epitaxial substrate.

An N- epitaxial layer 12 is formed on a heavily doped N+ substrate 11, a P-channel transistor is formed in the epitaxial layer 12, and an N-channel transistor is formed in a P-well 2 formed in the epitaxial layer 12. According to this structure, by using a highly doped substrate, the parasitic resistance due to the substrate can be reduced to 1/10 of that when no epitaxial substrate is used.
Latch-up does not occur because it can be set to 0 or less.

[Problem to be solved by the invention]

Although it is possible to significantly improve latch-up resistance by using an epitaxial substrate in this way,
Currently, epitaxial substrates are 2 to 3 times smaller than regular substrates.
It is extremely expensive, three times as expensive, resulting in an increase in the pellet price. In addition, since the epitaxial substrate has surface defects called slips and mounds that accompany epitaxial growth, there is also a drawback that the yield of pellets decreases.

[Means to solve the problem]

The latch-up resistant CMO8IC of the present invention is a P-channel FE
A diffusion layer of N-type for T and P-type for N-channel FET, that is, of the opposite conductivity type to the channel type, is formed in the region of the source/drain diffusion layer excluding the channel region, and the concentration of the diffusion layer is determined by the breakdown voltage of the transistor. is controlled to a maximum concentration that is higher than the operating power supply voltage.

The present invention does not use an epitaxial substrate, and by simply changing a few steps to the conventional manufacturing method, it is possible to significantly improve latch-up resistance at a low cost.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a cross-sectional view of one embodiment of the present invention, where 1 is an N- substrate, 2 is a P well, 3 is an N+ channel stopper, and 4 is a P well.
5 is a gate electrode, 6 is a P+ source/drain diffusion layer, 7 is an N+ buried diffusion layer, 8 is an N+ source/drain diffusion layer, 9 is a P+ buried diffusion layer, and 10 is a metal wiring. The formation of the P-well 2 on the N-substrate 1, the formation of the channel stopper 3.4, the gate electrode 5, and the formation of the source/drain diffusion layers 6 and 7 may be the same as the conventional method.

N in a P-channel transistor, which is a feature of the present invention
+P in buried diffusion layer 7 and N-channel transistor
+The buried diffusion layer 9 may be formed before or after the formation of the gate electrode 5 as long as it is before the formation of the source/drain diffusion layers 6 and 8. However, the buried diffusion layer 7゜9 is the source/drain diffusion layer 6, 8.
It is necessary to form it deeper, and a embedding process using some heat treatment is required.

Further, it is desirable that the concentration of the buried layers 7 and 9 be as high as possible in order to increase the latch-up resistance, but since this lowers the transistor breakdown voltage, it is necessary to set the concentration in consideration of the operating voltage of the CMOSIC.

In this example, the N-substrate surface concentration of I
On the other hand, an N-type diffusion layer 7 was formed by ion implantation of phosphorus at 5×I O of 15 cm −2 , and a P+ diffusion layer 9 was formed by ion implantation of poron at 4×10 13 cm −2 . Also, a buried diffusion layer? , 1100°C after ion implantation to form 9
The heat treatment was performed for 0 minutes, and the transistor breakdown voltage was approximately 10 V for both the P-channel transistor and the N-channel transistor.

Figure 3 shows the power supply voltage and current characteristics of the 0MO8IC of the example with the structure shown in Figure 2.As shown in Figure 4, it latched up at 75mA without latch-up measures, but it latched up to 300mA or more. It was confirmed that no uploads occurred.

FIG. 2 is a sectional view of another embodiment of the invention.

In FIG. 1, the channel stopper and the buried diffusion layer are formed separately, but the structure is such that the buried diffusion layers 7 and 9 also serve as the channel stoppers 3 and 4, which can simplify the manufacturing process. be.

In the embodiment of the present invention, a buried diffusion layer is formed in both the P-channel transistor and the N-channel transistor to prevent latch-up, but if a buried diffusion layer can only be inserted in one of them due to manufacturing reasons, etc. However, we have confirmed that the latch-up starting current is more than twice as strong.

[Effects of the Invention] As explained above, in the present invention, by forming a buried diffusion layer of a conductivity type opposite to that of the source/drain diffusion layer in the source/drain diffusion layer region, the invention can be realized without using an expensive epitaxial substrate. We were able to significantly improve latch-up resistance.

[Brief explanation of drawings]

FIG. 1 is a longitudinal sectional view of one embodiment of the present invention, FIG. 2 is a longitudinal sectional view of another embodiment of the invention, FIG. 5 is a longitudinal sectional view of the prior art, and FIG. 3 is a longitudinal sectional view of one embodiment of the present invention. FIG. 4 is a power supply voltage/current characteristic diagram in the embodiment without latch-up countermeasures. 1...N-substrate, 2...P well, 3
・・・・・・N+channel stopper, 4・・・・・・P
+ Channel stopper, 5... Gate electrode, 6,
9...P+diffusion layer, 7°8...N+diffusion layer, 10...metal wiring, 11...N
+substrate, 12...t...N-epitaxial layer. Agent: Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A P-channel MOSFET and an N-channel MOSFET formed independently in a semiconductor substrate of one conductivity type and a well of an opposite conductivity type.
A complementary field effect transistor having an OSFET, wherein at least one channel conductivity type of the transistor has a deep diffusion layer of opposite conductivity type to the source/drain diffusion layer under the source/drain diffusion layer.