JPS61268058A - Manufacture of complementary type mos integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the latch-up phenomenon of a complementary type MOS integrated circuit by implanting impurity ions to the inward section of a P-well from the direction along the direction of a crystal lattice of the P-well and forming a high concentration layer to a deep layer section. CONSTITUTION:A photo-resist 60 is applied onto a P-well 45, and impurity ions such as boron ions are implanted to an N-type substrate 41 to simultaneously shape a source region 62 and a drain region 63 in a P-MOS transistor Tr. The resist 60 is removed, a photo-resist 65 is applied onto a region 62, a gate electrode 57 and a region 63, and phosphorus is implanted to the P-well 45 to form a source region 66 and a drain region 67 in an N-MOSTr at the same time. Boron is implanted into the P-well 45 from the direction along the direction of a crystal lattice of the substrate 41 while penetrating the region 66 and the region 67, thus shaping high concentration layers 47 in predetermined thickness to inward sections. Accordingly, a latch-up can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a complementary MOS integrated circuit.

[Prior Art] Generally, a complementary MOS 4J product circuit (C-MOSIC) has a structure as shown in Fig. 5, in which a high voltage is applied between the drain D of an N-channel transistor and the source S of a P-channel transistor. When the voltage is applied, a path (indicated by the broken line in FIG. 5) consisting of the N-type drain region of the N-channel transistor, the P-well, the N-type substrate, and the P-type source region of the P-channel transistor is In order to prevent the phenomenon of conduction and large current flow, that is, rough rise, the amplification factor of the vertical NPN transistor of the N-channel MOS structure formed in the P-well of the N-type substrate is 1rt.
need to be lowered. For this reason, conventionally, there has been a method of forming a high impurity concentration layer inside the P-well when forming the P-well to form an impurity concentration distribution as shown in FIG. The method includes steps as shown in FIG. That is, the "enriched film (S+Oz)" formed on the N-type substrate of the silicon wafer is removed by a mask using photographic technology and chemical treatment, and the hole 3 for the P-well is opened (4-
1) Next, boron (Poron B ions) is implanted into the N-type substrate l through this hole 3.

At this time, a thin oxide film 4 is formed on the surface of the N-type substrate (4-2), and a P-well 5 is formed by heating the N-type substrate l to diffuse boron (poron) (4-2). 3) After removing the thin oxide film 4 in the hole 3, boron (poron) is injected into the deep part of the P-well 5 using a high-voltage, high-acceleration ion implanter to form a highly concentrated layer 7 (4). -4), P-well 5
A part of the oxide film (Sl 02 ) 2 in the area adjacent to the P-MO is removed by using a photo mask and chemical treatment.
68 for the S transistor is opened (4-5), and then the entire N-type substrate 1 is subjected to high-temperature heat treatment so that the N-type substrate 1 exposed in the hole 8 and the surface of the P-well 5 exposed in the hole 3 are heated. A gate oxide film 9.10 is formed (4-6). At this time, the heavily doped layer 7 injected into the deep part of the P-well 5 diffuses toward the surface, increasing the thickness of the heavily doped layer 7. Next, N type substrate 1
A uniform film of polycrystalline or amorphous silicon 12 is deposited on the entire surface (4-7), and a part of the polycrystalline or amorphous silicon 12 is removed using a mask using photo technology and chemical treatment to form an N-MOS transistor. Drill holes 13 and 14 for the source and drain, and holes 15 and 16 for the source and drain of the P-MOS transistor (4-8).
), and holes 13 and 15 for each source and drain, and hole 1
Gate electrodes 17 and 18 are formed between the gate electrodes 4 and 4 and 16, respectively. A photoresist 20 is applied on the P-well 5, and boron (Poron B) is applied to the N-type substrate l through the holes 15 and 16 for the source and drain of the P-MOS.
P-MOS) transistor source region 22,
Forming the drain region 23 at the same time (4-9), then
The photoresist 20 is removed, and the source region 22 of the P-MOS transistor, the gate electrode 18 . A photoresist 25 is applied on the drain region 23, and phosphorus (P- ions) is implanted into the P-well 5 through the holes 13 and 14 for the source and drain of the N-MOS transistor.
S) Simultaneously form the source region 26 and drain region 27 of the transistor (4-10), remove the photoresist 25, and further form a uniform film of polycrystalline or amorphous silicon 12 except above each gate electrode 17. Eliminate 4-
11) Next, an oxide film (S+ 02 ) is formed on the entire surface of the N-type substrate l.
28 (4-12), each source region 22.26
．． Oxide film (S+0z) 28 on drain region 23.27
were removed using a mask using photographic technology and chemical treatment, and holes 31, 32, 33, and 34 were opened for each electrode (4-13).
), aluminum 35 is deposited on the entire surface of this N-type substrate l, and aluminum is removed from areas other than each electrode. In this way, the complementary MOS integrated circuit manufactured by the conventional method is
The impurity concentration distribution on c-cliI has a cross section as shown in the figure.

The characteristics are as shown in FIG. This is an impurity concentration profile showing the phosphorus concentration of .

[Problems with the prior art] In such a conventional complementary MOS transistor, a high concentration layer is formed during the formation of the P-well, so that the high-concentration layer is injected into the P-well during the subsequent high-temperature heat treatment during the formation of the oxide film. The highly concentrated layer diffuses (7 receptors and porons in the highly concentrated layer diffuse toward the surface). Therefore, as the depth of the highly concentrated layer becomes shallower, the amplification degree HFE decreases, but the threshold hold VTH increases. In order to avoid such a phenomenon that causes
An expensive special ion implanter with an acceleration voltage of OOKev was required. Moreover, in this case, there was a problem that ion implantation defects occurred in the crystal lattice of the P-well due to high acceleration and high dose. [Objective of the Invention] This invention was made based on the above-mentioned circumstances. It is an object of the present invention to provide a method for manufacturing a semiconductor circuit that can form an impurity concentration distribution in a P-well through simple and ordinary steps to prevent latch-up phenomena in complementary MOS integrated circuits.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention utilizes the fact that the crystal states of the P-well and other parts are different after high-temperature treatment for forming a gate oxide film, etc. Then, using a normal ion implanter, boron (Poron B-) is injected deep into the P-well from the direction along the crystal lattice of the P-well to form a highly concentrated layer in the deep part. The main points are as follows.

[Example] The present invention will be explained below based on an embodiment shown in the drawings.

The oxide film (S102) 42 formed on the N-type substrate 41 of the silicon wafer is removed by a photo mask and chemical treatment, and a hole 43 for a P-well is opened (1-1).
), then boron (Poron B ions) is implanted into the N-type S plate 41 through this hole 43. At this time, a thin oxide film 44 is formed on the surface of the N-type substrate l (1-2),
This N-type substrate 41 is heated to diffuse boron (poron) to form a P-well 45 (1-3).The thin oxide film 44 and the P-well 45 are separated and the oxide film in the adjacent region is (S+ 02 ) 42 is removed by a mask using photographic technology and chemical treatment to form an N-MOS transistor and a P-M transistor.
Drill holes 43 and 48 for the OS transistors (1-
4) The entire N-type substrate 41 is subjected to high-temperature heat treatment to expose the N-type substrate l and the hole 43 of the P-well 45 in the hole 48.
Gate oxidation wJ4 is applied to the surface of P-'7zle 45 exposed to
9.5° (1-5). Next, a uniform film of polycrystalline or amorphous silicon 52 is deposited on the entire surface of the N-type substrate 41 (1-6). A portion of the polycrystalline or amorphous silicon 52 is removed by processing to form holes 55 and 56 for the source and drain of the P-MOS transistor, and an N-MOS transistor is formed on the P-well 45.
Drill holes 53 and 54 for the source and drain of the S transistor, respectively.

Gate electrodes 57.58 are formed between each source and drain hole 53.54 and hole 55.56 (1-7)
, a photoresist 60 is applied on the P-well 45, and boron (Poron B') is applied through the holes 55 and 56 for the source and drain of the P-MOS transistor. l!
Inject into the substrate 41 to form the source region 62 and drain region 63 of the P-MOS transistor at the same time (1-8)
, then the photoresist 60 is removed and this P-MOS
Transistor source region 62. A photoresist 65 is applied on the gate electrode 57 and the drain region 63, and N-M
OS) Holes 53 and 54 for transistor source and drain
Phosphorus (P. ions) is implanted into the P-well 45 through the process to simultaneously form the source region 66 and drain region 67 of the N-MOS transistor. In this case, the phosphorus ion implantation angle is approximately 7° with respect to the crystal lattice direction of the P-well.
The phosphorus ions are tilted to prevent the phosphorus ions from being implanted deeper into the P-well than necessary (1-9), and then the N-MO
Boron (Poron B°) is injected into the P-well 45 through the holes 53 and 54 for the source and drain of the S transistor and through the source region 66 and drain region 67 using an ion implanter with approximately 200-key. N inside! A high concentration layer 47 of a predetermined thickness is formed deep into the X1tW plate 41 by implanting it from a direction of ±10 or less with respect to the direction of the crystal lattice (1-10). At this time, poron ions accelerated to about 200 Kev are implanted. falls on the gate electrode 58, but the gate 1
[The electrode 58 is polycrystalline or amorphous, and therefore the crystal lattice is not aligned, so boron (Poron B4) is not implanted deep into the gate electrode 58.

The photoresist 65 is removed, and each gate electrode 57.
Remove the uniform film of the polycrystalline or amorphous silicon 52 except above 58 (1-11), and then form an oxide film (S+ 02 ) 68 on the entire surface of the N-type substrate 41 ('1-12).
), each source region 62, 66, drain region 63,87
The upper oxidized all (St02) 88 is removed using a photo mask and chemical treatment to form holes 71, 72 for each electrode,
73 and 74 are opened, aluminum 75 is deposited on the entire surface of this N-type substrate 41, and the aluminum except for each electrode is removed.

Complementary MOS integrated circuits manufactured by this method are
The N-MOS transistor has a cross section as shown in FIG. 2, and the impurity C chronotropy on the A-A line below the source region 66 and the B-B line below the gate electrode 58 is as shown in FIG. 3(a).
, (b), respectively. In FIG. 3, A is the P-well 45, the mouth is the high concentration injection layer 47, C is the source 66, 2 is the N substrate 41, and E is the gate electrode 5B.
The 0 dotted line, which is the impurity concentration profile, is phosphorus P.

The solid lines for ions indicate the concentration distribution of Poron B ions, respectively. As shown in Figure 3 (JL), the depth of the center of the high concentration layer becomes 0.8μ, and the amplification factor HF' decreases.Also, as shown in Figure 3 (b), the crystal lattice is aligned. Poron B° ions enter the gate electrode 58 at a depth less than half that of the N-type substrate 41 (single crystal) (the depth at the center of the concentration layer is 0.4 l), and a<N-type substrate. In this way, the poron ions are not implanted into the gate part of the transistor 41, and the amplification degree Hrt of the NPN transistor can be lowered without changing the threshhold Vrn. I can do it.

[Effects of the Invention] As explained above, the present invention performs ion implantation to form a high concentration layer in a process subsequent to the process of high-temperature heat treatment of the substrate, such as the process of forming a gate wiring film. In this case, the implantation angle is set to less than 1" with respect to the direction of the crystal lattice, and ions can be implanted deeply only into the P-well by utilizing the difference in the crystalline state between the gate and the substrate. Ion implanter (acceleration voltage 200Kev)
(below) can be used, and ion implantation does not cause defects in the crystal lattice due to high acceleration and high doses.Also, since the implantation process of the high concentration layer is performed with few subsequent heat treatment steps, the concentration due to diffusion The distribution is less spread,
It is possible to reduce the dose amount (shorten the implantation time), and because fewer ions enter the polycrystalline or amorphous gate electrode and insulating oxide film parts than single crystal, it is possible to reduce the amount of ions used in P-channel MOS parts, etc. Usual methods can be used to mask . Therefore, threshold VT)
This has the effect of lowering the amplification degree H and E of the NPN transistor without changing l and preventing rough rise.

[Brief explanation of drawings]

FIG. 1 is a process diagram of the method for manufacturing a complementary MOS integrated circuit according to the present invention, and FIG.
3 is a diagram showing its impurity concentration characteristics, FIG. 4 is a process diagram of a conventional complementary MOS integrated circuit manufacturing method, and FIG. 5 is a cross-sectional view of a transistor manufactured by the conventional manufacturing method. (N-MOS) transistor and P-MOS)
A cross-sectional view of the transistor, FIG. 6, is a diagram showing its impurity concentration characteristics. 41...N-type substrate, 45...P-well, 47...High concentration layer, 49.50...
・Gate oxide film, 62.66...source region,
63.67...Drain region, B-...
・Poron ion, Po... medium phosphorus ion. Patent applicant Casio Computer Co., Ltd. agent Patent attorney Machi 1) Quick-footed, ・”・1-t-
,' Coconut “g

Claims (1)

[Claims] A MOS transistor in which a region containing another impurity is formed in a substrate doped with impurities, and a source region, a drain region, and a high concentration layer of the other impurity are formed deeper than the source region and drain region in this region. In the method for manufacturing a complementary MOS integrated circuit, the high-concentration layer is subjected to high-temperature heat treatment for forming a gate oxide film, etc., and then the other impurity ions are removed from the direction along the crystal lattice direction of the substrate. 1. A method for manufacturing a complementary MOS integrated circuit, characterized in that it is formed by an implantation process.