JP2784111B2 - Method for manufacturing solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a two-dimensional solid-state image sensor used for a video camera, an electronic still camera, or the like, and a one-dimensional solid-state image sensor used for a facsimile, an electronic blackboard, or the like.

[0002]

2. Description of the Related Art For example, in a two-dimensional solid-state image pickup device, as shown in FIG. 4, a vertical CCD section 40 and a horizontal CCD section 41 are arranged, and an output gate 42 is provided at the last stage of the horizontal CCD section.
And a floating diffusion layer 44 interposed between the floating gate 44 and the reset gate 43. This floating diffusion layer is connected to the gate of the output transistor. Also, 45
Is a reset drain.

FIG. 3 is a cross-sectional view showing a manufacturing process of an AA 'portion in FIG.

(A) P formed on an N-type Si substrate 30
The surface of the well 31 is oxidized to form a SiO ₂ film 32,
Thereafter, a SiN film 33 is deposited, and after patterning, field ions are implanted.

(B) After locos oxidation, the field S
An iO ₂ film 34 is formed. Reference numeral 35 denotes a field ion-implanted P ⁺ layer (channel stop region). Then, Si
The N film 33 and the SiO ₂ film 32 are removed.

(C) A floating N ⁺ diffusion layer 36 is formed by N ⁺ ion implantation or the like.

(D) After oxidation and contact opening, a metal wiring 37 is formed.

[0008]

However, the solid-state imaging device manufactured by the above-mentioned conventional manufacturing method has the following problems.

(1) Field ion implanted P ⁺ layer 35 under field SiO ₂ film and floating N ⁺ diffusion layer 3
6 comes into contact with it, so that the junction capacitance increases.

(2) Since the area of the floating N ⁺ diffusion layer 36 cannot be reduced due to the necessity of securing a margin around the contact, the bottom capacitance of the N ⁺ diffusion layer 36 and the P well 31 increases.

(3) Field ion implanted P ⁺ layer 35
And the floating N ⁺ diffusion layer 36 are in contact with each other, so that the breakdown voltage is low. The withstand voltage of the output transistor and the like also decreases.

According to the present invention, without providing a special process,
An object of the present invention is to provide a method for reducing the detection capacitance and improving the withstand voltage.

[0013]

According to the present invention, there is provided a method of manufacturing a solid-state imaging device having a charge detecting portion including a floating diffusion layer formed of a second conductive type layer formed on a surface of a first conductive type region, comprising a field oxide film. Forming a floating diffusion layer by implanting impurity ions of the second conductivity type using a mask as a mask, wherein the step of forming the floating diffusion layer is performed after forming the field oxide film and before forming the floating diffusion layer. By performing the first conductivity type impurity ion implantation under the condition that the field ion implantation layer is formed under the field oxide film, the impurity is continuously formed over the deep portion below the field oxide film and below the floating diffusion layer formation region. Forming a field ion implanted layer .

[0014]

The P ⁺ / N ⁺ contact at the end of the field oxide film can be avoided.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on embodiments.

FIG. 1 is a sectional view of a manufacturing process corresponding to FIG.

(A) P formed on N-type Si substrate 10
The surface of the well 11 is oxidized to form a SiO ₂ film 12, and then a SiN film 13 is deposited and patterned.

(B) After locos oxidation, the field S
After the formation of the iO ₂ film 14, field ion implantation is performed through the SiO ₂ film from above the field SiO ₂ film and P ^{+ is} implanted under the SiO ₂ film to form a field ion implanted P ⁺ layer 15. I do. A deep P ⁺ layer is formed in a portion serving as a floating N ⁺ diffusion layer without a field SiO ₂ film.

(C) The floating N ⁺ diffusion layer 16 is formed by N ⁺ ion implantation or the like.

(D) After oxidation and contact opening, a metal wiring 17 is formed.

As apparent from the figure, the field SiO ₂
Since the P ⁺ layer under the film and the floating N ⁺ diffusion layer are not in contact with each other, the junction capacitance can be reduced. Also, the withstand voltage is increased.

FIG. 2 is a sectional view of a solid-state imaging device according to another embodiment of the present invention.

When the width of the floating N ⁺ diffusion layer 26 is reduced, there is no margin between the contact size and the N ⁺ diffusion layer size. In the conventional process, the metal wiring is formed at the end of the field SiO ₂ film by the P ⁺ layer or It is connected directly to the P-well and short-circuited. However, in the present invention,
Since there is no P ⁺ layer around the N ⁺ diffusion layer 26 to be contacted and there is a low-concentration P well, a short circuit can be prevented by additionally implanting a thin N ⁻ , so that the width of the N ⁺ diffusion layer is reduced. Can be smaller. Therefore, the junction capacitance can be reduced. Self contact is possible. Note that FIG.
, 20 is an N-type Si substrate, 21 is a P well, 24
Is a field SiO ₂ film, 25 is a field ion implanted P ⁺ layer, 27 is a metal wiring, and 28 is an N ⁻ layer.

[0024]

As described in detail above, according to the present invention, the detection capacitance of the floating diffusion layer can be reduced,
It is possible to improve detection sensitivity and reduce noise. Further, the withstand voltage can be increased, and the reliability can be improved and noise can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a solid-state imaging device according to another embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process in a conventional manufacturing method.

FIG. 4 is a configuration diagram of a solid-state imaging device.

[Explanation of symbols]

10, 20 N-type Si substrate 11, 21, P well 12 SiO ₂ film 13 SiN film 14, 24 field SiO ₂ film 15, 25 field ion implanted P ⁺ layer 16, 26 floating N ⁺ diffusion layer 17, 27 metal wiring 28 N ^- layer

Claims (1)

(57) [Claims] A first conductive type region formed on a surface of the first conductive type region;
A method for manufacturing a solid-state imaging device having a charge detection portion including a floating diffusion layer made of a conductive type layer, wherein the step of forming the floating diffusion layer by performing second conductive type impurity ion implantation using a field oxide film as a mask In the method for manufacturing a solid-state imaging device having the first conductivity type impurity ions formed under the condition that a field ion implantation layer is formed under the field oxide film after the formation of the field oxide film and before the formation of the floating diffusion layer, A step of forming a field ion-implanted layer continuously formed over the deep portion below the field oxide film and below the floating diffusion layer forming region by performing implantation. Production method.