JP3648518B2 - Solid-state imaging device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a solid-state imaging device for obtaining a highly sensitive signal output when the solid-state imaging device is miniaturized.
[0002]
[Prior art]
Conventionally, as a solid-state image sensor, an interline transfer type CCD solid-state image sensor shown in FIG. 5 has been widely used. In FIG. 5, 103 is a photodiode, 104 is a readout gate, 105 is a vertical charge transfer element, 102 is a horizontal charge transfer element, and 101 is an output circuit. After the signal charge photoelectrically converted by the photodiode 103 is accumulated for a predetermined period, the readout gate 104 is turned on and is read out to the vertical charge transfer element 105 at the same time for all pixels. Next, it is transferred through the vertical charge transfer element 105 and the horizontal charge transfer element 102, converted into a voltage by the output circuit 101, and read out.
[0003]
In general, the output circuit of such a CCD type solid-state imaging device has a wide range of so-called floating diffusion layer type output circuits in which a signal charge sent from a horizontal charge transfer element is inputted to the floating diffusion layer and its voltage change is detected. It is used. One conventional example of such a floating diffusion layer type output circuit is shown in FIGS. 6 is a plan view, and FIG. 7 is a sectional view taken along line CC ′ in FIG. In FIG. 7, 1 is a low-concentration n-type silicon substrate, 2 is a low-concentration p-type well, 3 is a p-type second well for reducing smear mixed in the vertical charge transfer element, and 4 is a buried channel of the charge transfer element. N-type layer, 5 is a high-concentration n-type floating diffusion layer, 6 is a channel stopper, 7 is an insulating film, 8 is a local oxide film, 9 is a field plate electrode, 10 is an output barrier electrode, 11 is a transfer electrode, 12 Is a polysilicon wiring also serving as the gate electrode of the output transistor, 13 is an Al wiring, 14 is a contact connecting the high-concentration n-type floating diffusion layer 5 and the Al wiring 13, and 15 is a contact connecting the polysilicon wiring 12 and the Al wiring 13. It is. In FIG. 6, 16 is a reset drain diffusion layer made of a high concentration n-type diffusion layer for discharging signal charges, and 17 is a reset electrode.
[0004]
This floating diffusion layer type output circuit detects signal charges by the following operation. First, a reset pulse is applied to the reset electrode 17 to set the voltage of the floating diffusion layer 5 equal to a predetermined DC voltage (reset voltage) applied to the reset drain diffusion layer 16. Subsequently, when a clock pulse is applied to the transfer electrode 11, the signal charge sequentially transferred in the horizontal charge transfer element 102 flows into the floating diffusion layer 5 over the output barrier electrode 10 to which a predetermined DC voltage is applied. As a result, the voltage of the floating diffusion layer 5 is lowered by ΔV from the previous reference voltage due to the inflow of signal charges. This voltage change due to the signal charge is detected as a voltage change in the polysilicon wiring 12 which also serves as the gate electrode of the output transistor connected via the Al wiring 13. In general, a reverse bias is applied to the n-type silicon substrate 1 with respect to the p-type well 2 in order to release excess charges generated in the photodiode to the substrate.
[0005]
The detection sensitivity η in such a floating diffusion layer type output circuit can be expressed by η = δV _S / δQ _S = 1 / C _D. Here, the amount of change .DELTA.V _S is the output voltage, .delta.Q _S change amount of the signal charge, C _D is the detection capacity. Therefore, in order to increase the detection sensitivity η it must reduce the detected capacitance C _D. Detected capacitance C _D of the floating diffusion layer-type output circuit shown in FIG. 6 and 7 when fractionated components, expressed by the equivalent circuit of FIG. 8, C _J is a junction capacitance between the floating diffusion layer 5 and the p-type second well 3, C _OG is a capacitance between the floating diffusion layer 5 and the output barrier electrode 10, and C _RS is a reset between the floating diffusion layer 5 and the output barrier electrode 10. the capacitance between the electrodes 17, C _L is the capacitance between the Al wiring 13 and the field plate electrode 9, or the capacitance between the p-type second well 3, and a polysilicon wiring 12 and the field plate electrode 9, C _DG is a capacitance between the polysilicon wiring 12 and the p-type second well 3 in the output circuit unit 101. The reduction method C _OG and C _RS of these components, a high concentration n-type floating diffusion layer 5 outputs the guard electrode 10, a method of spaced than the reset electrode 17 described in JP-B-61-25224 ing. On the other hand, as a method for reducing C _J , JP-A-59-65470 and JP-A-62-33463 describe a method of completely depleting the p-type well 2 immediately below the floating diffusion layer 5.
[0006]
[Problems to be solved by the invention]
However, reduction of the detected capacitance C _D of the conventional floating diffusion type output circuit by the following reasons are still insufficient.
[0007]
In accordance come technology, it has not been considered for the junction capacitance generated floating diffusion layer 5 around. That is, since the p-type second well 3 is widely provided so as to cover the n-type layer 4 around the floating diffusion layer 5 and the n-type layer 4 provided around the floating diffusion layer 5 as shown in FIG. the depletion layer that has become a growth difficult for the parasitic capacitance. What slave, purpose of the present invention is Ru near to reduce the junction capacitance of 5 near the floating diffusion layer.
[0008]
[Means for Solving the Problems]
To achieve purpose in the present invention, and the p-type second well 3 and the n-type layer 4 is formed by self-alignment.
[0010]
[Action]
It is possible to completely deplete the p-type second well 3 at the periphery of the n-type layer 4 by means for achieving the purpose can be to reduce the parasitic capacitance of the bonding peripheral portions.
[0012]
【Example】
<Example 1>
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a plan view of the periphery of a charge detection unit according to the first embodiment of the present invention, FIG. 2 is a sectional view taken along line AA 'in FIG. 1, and FIG. 3 is a sectional view taken along line BB' in FIG. is there. In FIG. 1, 23 is a p-type second well for reducing smear mixed in the vertical charge transfer element, 24 is an n-type layer serving as a buried channel of the charge transfer element provided in the p-type second well 23, Reference numeral 25 denotes a contact for connecting the polysilicon wiring 12 and the Al wiring 13. 3 in FIG. 3 is a channel stopper layer that is depleted during operation.
[0013]
This floating diffusion layer type output circuit detects signal charges by the same operation as in the conventional example.
[0014]
The structure of the present embodiment is created by the following manufacturing method. That is, the low concentration p-type well 2 is formed on the low concentration n-type silicon substrate 1 by ion implantation and thermal diffusion. Next, the region other than the local oxide film formation region is covered with the nitride film A, the channel stopper 26 is formed by implanting boron ions, and the local oxide film 8 is formed by surface oxidation. After removing the previous nitride film A, a new nitride film B is formed in a portion other than the region where the p-type second well 23 is formed, and the p-type second well 23 is formed by ion implantation. At this time, no ion implantation is performed in the region where the local oxide film 8 is present. Next, a region where the p-type second well 23 such as an output transistor is formed but the n-type layer 24 is not formed is covered with a new photoresist while leaving the previous nitride film B, and the n-type layer 24 is formed by ion implantation. To do. At this time, in the floating diffusion formation region, the p-type second well 23 and the n-type layer 24 are formed in a self-aligned manner using the nitride film B or the local oxide film as a mask.
[0015]
Next, the entire region is gate-oxidized to form the insulating film 7, and then the first layer of polysilicon is deposited and patterned to form the output barrier electrode 10 and the polysilicon wiring 12. Next, a transfer electrode 11 is formed by depositing and patterning a second layer of polysilicon. Thereafter, the outside of the region where the floating diffusion layer 5 is provided is covered with a photoresist, and the floating diffusion layer 5 is formed by ion implantation. Further, after depositing the phosphor glass film, the region outside the region where the contact 14 for connecting the floating diffusion layer 5 and the Al wiring 13 and the contact 25 for connecting the polysilicon wiring 12 and the Al wiring 13 are provided is covered with a photoresist and etched. . Next, Al is deposited to form an Al wiring 13.
[0016]
According to this embodiment, there are the following effects. First, as shown in FIG. 2, the p-type second well 23 and the n-type layer 24 are formed in a self-aligned manner. As a result, the p-type second well 23 is completely depleted around the diffusion layer 24 by the reset voltage applied to the n-type floating diffusion layer 5, and the parasitic capacitance in the peripheral portion of the junction can be eliminated.
[0017]
Second, a contact 25 for connecting the polysilicon wiring 12 and the Al wiring 13 was formed on the n-type layer 24 as shown in FIG. Reduced by this, between the field plate area of the polysilicon wiring 12 on the electrode 9 is reduced Al wiring 13 and the field plate electrode 9, or C _L it is possible to eliminate the capacitance between the p-type second well 23 it can. On the other hand, according to the structure of the present invention, the area of the n-type layer 24 having the same potential as that of the floating diffusion layer 5 is increased, but the p-type second well 23 and the p-type well 2 immediately below the n-type layer 24 are completely depleted. By doing so, the capacity can be increased slightly. Therefore, it is possible to reduce the detected capacitance C _D.
[0018]
The p-type second well 23 and the p-type well 2 immediately below the n-type layer 24 are formed to a depth of about 0.8 μm by the method described in JP-A-3-289173. If shallow, depletion can be easily performed by the voltage applied to the n-type substrate 1 and the reset voltage applied to the n-type floating diffusion layer 5.
[0019]
Third, the field plate electrode 9 having a conventional structure was removed, and the channel stopper 26 and the p-type well 2 immediately below the local oxide film 8 were depleted. This point will be described in more detail with reference to FIG. FIG. 4 is an example of a simulation result of the width dependence of the local oxide film 8 at the lowest potential inside the p-type well 2 immediately below the local oxide film 8 shown in FIG. As shown in the figure, for example, if the width of the local oxide film 8 is 1.8 μm or less, the reset voltage applied to the floating diffusion layer 5 and the polysilicon wiring 12 and the reverse bias voltage applied to the n-type substrate 1 are shown. Thus, it can be seen that the internal potential of the p-type well 2 immediately below the local oxide film 8 becomes larger than 0 V and is depleted. Accordingly, the capacitance between the polysilicon wiring 12 and the p-type well 2 can be eliminated. In order to prevent the breakdown voltage degradation between the channel of the transistor having the polysilicon wiring 12 as a gate and the diffusion layer 24, the minimum potential of the element isolation portion is set to be lower than the channel voltage of the transistor. That's fine.
[0020]
<Example 2>
A second embodiment of the present invention will be described with reference to FIGS. 9 is a plan view of the periphery of the charge detection portion of the second embodiment of the present invention, FIG. 10 is a cross-sectional view taken along line EE ′ in FIG. 9, and FIG. 11 is a cross-sectional view taken along line FF ′ in FIG. is there. 9 and 10, reference numeral 91 is a field plate electrode, and 92 is an n-type well that facilitates depletion of the p-type well 2 of the horizontal charge transfer element.
[0021]
In this embodiment, an n-type well 92 is provided in order to facilitate the depletion of the horizontal charge transfer element and increase the transfer efficiency in the first embodiment. However, as a result, there arises an adverse effect that the punch-through breakdown voltage between the n-type layer 24 and the n-type silicon substrate 1 deteriorates around the n-type layer. Therefore, the field plate electrode 91 is provided around the n-type layer 24 to improve the isolation performance. If the field plate electrode 91 is arranged at a predetermined distance from the n-type layer 24, the depletion layer extending from the n-type layer 24 can be sufficiently extended, so that no parasitic capacitance around the n-type layer 24 is generated. Therefore, the effect of reducing the detected capacitance C _D according to the present embodiment can nearly equalized in the first embodiment, it is compatible with the transfer efficiency of the horizontal charge transfer device.
[0022]
<Example 3>
A third embodiment of the present invention will be described with reference to FIG. This figure is a sectional view of a portion corresponding to BB 'in FIG. 1 of the first embodiment. Reference numeral 126 denotes a p-type diffusion layer for element isolation, and the other symbols are the same as those in the first embodiment. In this embodiment, the local oxide film 8 of the first embodiment is removed, and element isolation is performed only by the p-type diffusion layer 126 having a concentration higher than that of the p-type second well 23. Therefore, the operation of this embodiment is the same as that of the first embodiment. According to this embodiment, the step of forming the local oxide film can be eliminated.
[0023]
In the above embodiment, three methods for reducing the parasitic capacitance have been described in order to improve the detection sensitivity of the floating diffusion layer type output circuit of the CCD type image pickup device. On the other hand, parasitic capacitance is a cause of limiting the operation speed and detection sensitivity in all integrated circuits. Needless to say, the three methods described above have the effect of reducing the parasitic capacitance of all integrated circuits.
[0034]
【The invention's effect】
According to the present invention, the p-type second well 23 and the n-type layer 24 in the floating diffusion layer type output circuit are formed in a self-aligned manner so that the p-type second well 23 is completely depleted around the n-type layer 24. can be of, Ru can be eliminated parasitic capacitance of the bonding peripheral portions. Result of this, it is possible to improve the detection sensitivity greatly reduces the detected capacitance C _D.
[Brief description of the drawings]
FIG. 1 is a plan view of a periphery of a charge detection unit in a solid-state imaging device showing a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along the line AA ′ in FIG.
FIG. 3 is a cross-sectional view taken along line BB ′ in FIG.
FIG. 4 is an explanatory diagram showing an example of a potential analysis of a local oxide film width W dependency of a p-type well internal potential directly under the local oxide film.
FIG. 5 is a block diagram of an interline transfer type CCD solid-state imaging device.
FIG. 6 is a plan view of the periphery of a charge detection unit in a conventional solid-state imaging device.
7 is a cross-sectional view taken along the line CC ′ in FIG. 6;
FIG. 8 is an equivalent circuit diagram illustrating a ground capacitance of the charge detection unit.
FIG. 9 is a plan view of the periphery of a charge detection unit in a solid-state imaging device showing a second embodiment of the present invention.
10 is a cross-sectional view taken along the line EE ′ of FIG. 9;
11 is a sectional view taken along line FF ′ of FIG.
FIG. 12 is a cross-sectional view around a charge detection unit in a solid-state imaging device showing a third embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 5 ... High concentration n-type floating diffusion layer, 8 ... Local oxide film, 10 ... Output barrier electrode, 12 ... Polysilicon wiring, 13 ... Al wiring, 14 ... Contact, 16 ... High concentration n-type reset drain diffusion layer, 17 ... Reset electrode, 23 ... p-type second well, 24 ... n-type layer, 25 ... contact.

Claims (1)

A charge transfer unit for transferring a signal charge in a semiconductor region of a second conductivity type provided on a semiconductor substrate of the first conductivity type, and a first for holding a signal charge from the charge transfer unit for a certain period Higher concentration than the conductive type floating diffusion layer, the first conductive type diffusion layer wider than the first conductive type floating diffusion layer and the second conductive type semiconductor region surrounding the first conductive type diffusion layer A solid-state imaging device including a detection circuit for detecting and amplifying a potential change of the first conductive type floating diffusion layer due to a signal charge, wherein the second conductive type diffusion layer is higher than the second conductive type semiconductor region. The second conductivity type diffusion layer having a concentration is formed by self-alignment by ion implantation using the same mask as the first conductivity type diffusion layer, and the second conductivity type having a higher concentration than the semiconductor region of the second conductivity type. diffusion of the diffusion layer of the first conductivity type A solid-state imaging apparatus characterized by completely depleted in the periphery.

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