JPH02288266A - Solid state image sensor - Google Patents

Abstract

PURPOSE:To obtain a solid stage image sensor in which a dark current does not flow to a photodiode part by forming a recess formed on a semiconductor substrate with a first region of an excessive charge scavenging channel region, and providing a second region on the surface of the substrate or in a shallower dent than the recess. CONSTITUTION:In a solid state image sensor, an excessive charge scavenging channel region is divided into a first region 36a near an N<+> type layer 4 as a drain and a second region 36b near an N-type layer 3 for forming a photodiode, the first region is formed in a groove, the second region is formed in a dent, and the second region may be formed on a flat surface of a substrate. The second region is desirably formed in length of 1/2 or less of the length of the channel region. As a result, half or more of dark currents generated in the regions 36a, 36b operating as the channel region can be removed to the layer 4 for excessive charge scavenging drain, and a solid stage image sensor in which most of a dark current generated in the region 36a does not flow to the photodiode can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state image sensor, and particularly to a solid-state image sensor suitable for increasing sensitivity.

[Conventional technology]

Conventional charge-coupled device with overflow gate (hereinafter referred to as C
FIG. 5 shows an example of the configuration of a CD-type solid-state imaging device. The flow of signals from a photodiode 41, such as a PN junction diode, to the vertical CCD 43 is controlled by a selection gate 42, which is connected to a gate line 51. The horizontal CCD 44 transfers the signal from the vertical CCD 43 to the output amplifier 45. Normally, the vertical CCD 43 is driven quickly by a four-phase clock. In the figure, 46.47.48.4
9 is a clock wiring for the vertical CCD 43. Signal charges excessively accumulated in the photodiode 41 are swept out from the gate electrode 50 via the drain line 53.
2.

FIG. 3 shows a cross-sectional view of the pixel portion of such a conventional CCD type solid-state image sensor. This element is described in Japanese Patent Laid-Open No. 172764/1983. As shown in the figure, the pixel section of the conventional CCD type image sensor includes a light receiving section 10 and a light shielding section 3 horizontally adjacent to the light receiving section 10.
It consists of 5. A groove is formed in a portion of the surface of the P-type substrate 1 that corresponds to the light shielding portion 35 . An N-type layer 3 constituting a photodiode is formed on the substrate surface of the light-receiving region 10,
On the substrate surface of the light-shielding region 35, an N-type layer 5 as a transfer channel of the vertical CCD section and an N+ layer 4 as a drain for sweeping out excess charge are formed, and a p-type layer 4 as a channel stopper is formed.
It is separated from adjacent elements by the f layer 2. The sloped portion of the side surface of the groove sandwiched between the N-type layer 3 constituting this photodiode and the N+ layer 4 serving as a drain for sweeping out excess charges served as a channel region 36 for flushing out excess charges. Also P
A read/transfer gate electrode 7 made of, for example, polycrystalline Si is formed on the mold substrate 1 with a gate oxide film 37 interposed therebetween.
A vertical CCD transfer gate electrode 8 consisting of
Further, a light shielding film 9 made of AQ, for example, was formed with the insulating film 6 interposed therebetween. This light shielding film 9 also functions as a gate electrode.

In this way, the excess charge sweep-out channel region 36, which is sandwiched between the N-type layer 3 of the photodiode and the N+ layer 4 as a drain for sweeping out excess charge, and controls the sweep-out of excess charge from the photodiode portion to the drain for flushing out excess charge, is formed on the P-type substrate. Since it is formed on the side surface of the groove formed on one surface,
The channel length for sweeping out excess charge was effectively increased.

[Problem to be solved by the invention]

In the above conventional technology, since the groove in which the excess charge sweeping channel region is formed is formed by dry etching, sufficient consideration is not given to the fact that damage from dry etching remains on the groove surface and this damage increases dark current. First, there is a problem in that approximately half of the dark current generated in the excess charge sweeping channel region flows into the photodiode section, increasing the dark current of the photodiode.

SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device having a structure that prevents dark current generated in an excess charge sweeping channel region from flowing into a photodiode portion.

[Means to solve the problem]

The above object is to (1) provide a semiconductor substrate with an array of photoelectric conversion elements, a signal readout element for reading out signals from the photoelectric conversion elements, a charge transfer element for transferring charges from the signal readout elements, and the photoelectric conversion element; It has an excess charge sweeping element for sweeping out the excess charge accumulated in the conversion element,
The excess charge sweeping element is a solid-state imaging device comprising a gate electrode, a diffusion layer serving as a drain, and an excess charge sweeping channel region formed through an oxide film on the gate electrode, wherein the excess charge sweeping channel region is , consisting of a first region near the diffusion layer and a second region near the light weight conversion element, the first region being provided in a recess formed in the semiconductor substrate, and the second region being provided in a recess formed in the semiconductor substrate. is a solid-state imaging device, characterized in that it is provided on the surface of the semiconductor substrate or in a recess shallower than the recess; (2) the impurity concentration in the first region is lower than the impurity concentration in the second region; The solid-state imaging device according to 1 above.

(3) The solid-state imaging device according to item 1, wherein the gate electrode of the excess charge sweeping element is electrically connected to the diffusion layer serving as the drain.

(4) The semiconductor substrate includes a well layer of a second conductivity type formed on the surface of the semiconductor substrate of the first conductivity type, and
(5) The charge transfer device has a gate electrode of 2 JPJ, and (5) the charge transfer device has a gate electrode of 2 JPJ. 1 above, wherein one of the gate electrodes also serves as a gate electrode of the excess charge sweeping element.
This is achieved by the solid-state imaging device described above.

[For production]

By forming a groove in only a part of the excess charge sweep-out channel region near the excess charge sweep-out drain, a large amount of dark current generated in this part can be constantly discarded to the excess charge sweep-out train. Dark current does not flow into the photodiode section.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a sectional view of a pixel portion of a solid-state image sensor according to an embodiment of the present invention. This embodiment is different from the conventional example shown in FIG. 3 in that the excess charge sweeping channel region is formed by a first region 36a close to N''fVJ4 as a drain for excess charge sweeping, and an N-type layer 3 constituting a photodiode. The first region 36b is formed in a groove, and the second region 36b is formed in a depression.The second region 36b is formed in the plane of the substrate surface. It is preferable that the second region has a length of 1/2 or less of the length of the entire excess charge sweeping channel region. Reference numeral 11 designates an excess charge sweeping gate electrode. More than half of the dark current generated in the first and second regions 36a and 36b, which act as channel regions, is discarded into the drain N7 layer 4 for sweeping out excess charges, so most of the dark current generated in the first region 36a is was able to prevent it from flowing into the photodiode.

Although it is difficult to form deep grooves without damage, the depth of the recess in the second region 36b can be adjusted to the depth of the recess in the first region 36a.
LOGO3 (Local Oxy-dati
By using the oxidation method (on pf Si), the channel length can be extended by sweeping out excess charge with almost no damage.

Furthermore, by forming the P-type layer 16 so as to cover the Nt layer 4 deeper than the N+ layer 4 serving as a drain for sweeping out excess charge, the extension of the depletion layer of the Nf layer can be suppressed. Signal charges that would otherwise have been discarded can be used effectively.

Furthermore, by using the excess charge sweeping gate electrode 11 as the wiring for the excess charge sweeping drain N7 layer 4, it is possible to reduce the area occupied by the excess charge sweeping section.

FIG. 6 is a process diagram showing a method for manufacturing the pixel portion of the solid-state image sensing device shown in FIG. 4. A nitride film 55 is formed on the surface of a P-type substrate 1 made of P-type silicon, and after a desired pattern is formed by an etching process using a mask, a LOGO8 oxide film 56 with a thickness of about 0.4 μm is formed by thermal oxidation. (Figure 6(a)).

After removing the nitride film 55 and the LOGO8 oxide film 56, the N-type layer 3 is formed by ion implantation using a mask and a diffusion process. The depth of the depression formed by removing this LOGO8 oxide film 56 is about 0.2 μm (FIG. 6(b)).
, then an etching process using a mask to a thickness of 1 μm.
After forming an oxide film 57 with a thickness of about m in a desired pattern, a groove 76 with a depth of 3 μm is formed by dry etching using this as a mask.

After forming a thin oxide film 58 in the groove 76 by thermal oxidation, the P-type layer 16 is formed by ion implantation using a mask and a diffusion process.
and N layer 4 are sequentially formed (FIG. 6(c)). Oxide film 5
After removing 7.58 and forming a thin oxide film 12 on the entire surface by thermal oxidation, 91 is removed by ion implantation using a mask.
Form layer 2. Further, an excess charge discharging gate electrode 11 made of polycrystalline silicon is selectively formed by an etching process using a mask (FIG. 6(d)).

FIG. 1 shows a pixel section of a solid-state image sensor according to another embodiment of the present invention. In this embodiment, a P-type well layer/[21 is provided on the surface of the N-type substrate 22, and the depth of the groove is set to be greater than or equal to the depth of the P-type well layer 21.
tWI4 was electrically connected to the N-type substrate 22, eliminating the need for wiring to the drain.

This allows the excess charge sweeping section to be miniaturized and sensitivity to be improved. In addition, a second region 36 in which no depression is formed
A P-type layer 29 was formed during the process. As a result, the P-type layer 2
By creating a potential barrier at the portion 9, it is possible to prevent a large amount of dark current generated in the first region 36a from flowing into the photodiode N-type layer 3. Furthermore, a P-type layer 24 having a concentration higher than that of the P-type layer 29 was formed in the first region 36a. As a result, the extension of the depletion layer in the first region 36a can be suppressed, so that the signal charge that was wasted in the NtM4 for draining excess charge through the first region 36a can be effectively used. Note that 25 is a P-type layer for isolation. This allows for more reliable isolation.

FIG. 2 shows a pixel section of a solid-state image sensor according to still another embodiment of the present invention. One difference between this embodiment and the embodiment shown in FIG. 1 is that the photodiode has a PtNP structure. This has the effect of increasing the capacity of the photodiode and suppressing dark current. Two parts are divided into a first part 11a in which an excess charge sweeping gate electrode is formed in the groove and a second part 11b in the other part, and the first part 11a in the groove is electrically connected to the N-type substrate 22. Connected but second part 1
1b means not electrically connected. In this case as well, wiring for the N+ layer 4 is not required.

FIG. 7 is a process diagram showing the manufacturing method of the embodiment shown in FIG. Using a mask, ion implantation and thermal diffusion are performed on the surface of the N-type substrate 22 made of N-type silicon to a depth of approximately 6.
A P-type well layer 21 with a thickness of .mu.m is formed (FIG. 7(a)).

Next, an oxide film 57 with a thickness of about 1 μm is formed and a desired pattern is formed by an etching process using a mask.
Using this as a mask, the well layer 2 is etched by dry etching.
A groove 76 having a depth of about 7 μm, which is deeper than 1, is formed. After forming a thin oxide film 58 in the groove 76 by thermal oxidation, the Nt layer 4 is formed by ion implantation using a mask and a diffusion process.

The two isolation layers 2 are formed by diagonal implantation technique (FIG. 7(b)). Next, after removing the oxide films 57 and 58 and forming a thin oxide film 12 on the entire surface by thermal oxidation, polycrystalline silicon is deposited on the entire surface and etching is performed using the oxide film 12 as a stopper to sweep out excess charge and form a gate electrode. Then, the first portion 11a is selectively formed (FIG. 7(C)). Furthermore, after forming a thin oxide film 12 on the entire surface by thermal oxidation, a second portion 11b of the gate electrode for discharging excess charge made of polycrystalline silicon is selectively formed by an etching process using a mask (FIG. 7 (cl)). .

Note that the N-type layer 34 and the P-type layer 33, which will become a photodiode, are sequentially formed in a self-aligned manner with respect to the second portion 11b of the gate electrode by ion implantation using a mask and a diffusion process.

FIG. 8 shows a plan view of a pixel section of a solid-state image sensor according to still another embodiment of the present invention. The area surrounded by the broken line 61a is the active region 61, which includes a photodiode section 62, a read channel section 80, and a vertical CCD section 64. A portion outside the broken line 61a indicated by diagonal lines sloping upward to the right is an isolation region 68, in which 21 layers are formed. 66 and 67 are transfer gate electrodes of the vertical CCD, and 67 also serves as a read gate electrode.

Note that 76 is a groove portion, and the photodiode portion 62 is an N-type layer formed in a diagonally shaded area downward to the right and a vertical C
It consists of a P'' layer formed over the entire surface of the photodiode section using the transfer gate electrodes 66 and 67 of the CD as a mask.

Next, FIG. 9 shows a sectional view taken along line AA' in FIG. This figure differs from the embodiment shown in FIG. 1 in that the gate electrode for sweeping out excess charge also serves as the transfer electrode 67 of the vertical COD. This simplifies the element configuration. Note 6
6 is a transfer gate electrode of the other vertical CCD, and 70 is an insulating film between the eyebrows. Furthermore, by using the region between A and A' in FIG. 8, that is, the wiring region of the vertical CCD transfer electrode, as the second region 36b of the excess charge sweeping channel region,
It is possible to prevent the area of the light receiving section from decreasing due to the provision of the excess charge sweeping section.

Another example in which the structure of this embodiment is partially modified will be shown. 1st
FIG. 0 is a sectional view thereof, and is a view of a portion corresponding to FIG. 9. This figure differs from the embodiment shown in FIG. 9 in that both wiring regions of the vertical CCD transfer electrodes 66 and 67 are used as the second region 36b of the excess charge sweeping channel region. During the horizontal scanning period, by making the potential of the vertical CCD transfer electrode 67 higher than the potential of the vertical CCD transfer electrode 66, most of the dark current generated in the second region 36b of the excess charge sweeping channel region is swept away. It can be swept out to the Nt layer 4 for train.

In the embodiments of the present invention, we have talked about grooves, but of course holes can also be used. Furthermore, the effect remains the same even if the conductivity types are completely reversed. Furthermore, in the above embodiments, the light-receiving section uses a junction diode, but the present invention can also be applied when another photoelectric conversion element such as a MOS diode or a photoconductive film is used instead of the junction diode. It is clear that the effects of the present invention can be achieved even if the above is implemented.

〔Effect of the invention〕

According to the present invention, a large amount of dark current generated in the excess charge sweeping channel can be discarded to the excess charge sweeping drain, and can be prevented from flowing into the photodiode section. Therefore, the excess charge sweeping channel can be lengthened without increasing dark current, and the excess charge sweeping section can be made smaller.

[Brief explanation of the drawing]

Figures 1, 2, 4, 9, and 1θ. FIG. 3 is a cross-sectional view of a pixel portion of a solid-state image sensor according to an embodiment of the present invention, FIG. 5 is a configuration diagram of a conventional CCD solid-state image sensor, Figure 6 shows
FIG. 4 is a process diagram showing a method for manufacturing a pixel portion of a solid-state image sensor according to an embodiment of the present invention shown in FIG. FIG. 8 is a plan view of a pixel portion of a solid-state image sensor according to an embodiment of the present invention. 1...P-type substrate 2...PT layer 3.34.
...(For photodiode) N-type layer 4...(For excess charge sweeping drain) N''R5...(For vertical CCD channel) N-type layer 6・Insulating film 7.8...
Transfer gate electrode 9...light shielding film 10...
Light receiving part 11.50...Excess charge sweeping gate electrode 1
1a...(Excess charge sweeping gate electrode) First portion 11b...(Excess charge sweeping electrode to gate 1) Second portion 12.57.58...Oxide film 16.24.25.
29...P type layer 21...P type well layer 22...
・N-type substrate 33... (for photodiode) P-type layer 35
... Light shielding part 36 ... Excess charge sweeping channel region 36a ...
-First area 36b...Second area 37...
Gate oxide film 38... Interlayer oxide film 41... Photodiode 42... Selection gate 43... Vertical CCD 44... Horizontal CCD 45... Output amplifier 46, 47, 48.49... Clock wiring 51.52
...Gate line 55...Nitride film 56...LO
GO5 oxide film 61...active region 61a...
Broken line 62...Photodiode section 64...
・Vertical CCD section 66.67... Transfer gate electrode 68... Isolation region 70... Interlayer insulating film 76... Groove 80... Read channel section

Claims (1)

[Claims] 1. An array of photoelectric conversion elements, a signal readout element for reading out signals from the photoelectric conversion elements, a charge transfer element for transferring charges from the signal readout elements, and an array of photoelectric conversion elements on a semiconductor substrate. The photoelectric conversion element has an excess charge sweep-out element for discharging excess charges accumulated in the photoelectric conversion element, and the excess charge sweep-out element includes a gate electrode, a diffusion layer serving as a drain,
In a solid-state imaging device comprising the gate electrode and an excess charge sweeping channel region formed through an oxide film,
The excess charge sweeping channel region includes a first region near the diffusion layer and a second region near the photoelectric conversion element, and the first region is provided in a recess formed in the semiconductor substrate. , wherein the second region is provided in a recess shallower than the surface of the semiconductor substrate or the recess. 2. The solid-state imaging device according to claim 1, wherein the impurity concentration in the first region is lower than the impurity concentration in the second region. 3. The solid-state imaging device according to claim 1, wherein the gate electrode of the excess charge sweeping element is electrically connected to the diffusion layer serving as the drain. 4. The semiconductor substrate is composed of a well layer of a second conductivity type formed on the surface of the semiconductor substrate of the first conductivity type, and the bottom of the recess in which the first region is provided is formed by the semiconductor substrate of the first conductivity type. 2. The solid-state image sensor according to claim 1, wherein the solid-state image sensor reaches the substrate. 5. The solid-state imaging device according to claim 1, wherein the charge transfer device has two layers of gate electrodes, and one of the gate electrodes also serves as a gate electrode of the excess charge sweeping device.