JP2885296B2 - Charge transfer element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device,
In particular, the present invention relates to a charge transfer element using a junction field-effect transistor as a charge detection means.

[0002]

2. Description of the Related Art A charge transfer device using a junction field effect transistor as a charge detection device is disclosed in a technical report of the Institute of Television Engineers of Japan [ITEJ Technical Report Vol. 14
No. 16, pp. 19-24, IPU90-11, C
E'90-11 (Feb. 1990)]. FIG. 3A is a plan view of this type of conventional charge transfer device, and FIGS. 3B and 3C respectively show the B-
It is sectional drawing of the B line and CC line.

In FIG. 1, reference numeral 1 denotes an n-type silicon substrate;
Denotes a p-type well, 3 denotes an n-type charge transfer region provided in the p-type well, and 4 and 5 denote a charge transfer electrode and an output gate formed on the charge transfer region via a gate insulating film 6, respectively. , 7 is a junction gate region formed integrally with the charge transfer region for receiving signal charges transferred in the region, and 8 is formed substantially at the center of the junction gate region 7 so as to penetrate through the region. A p-type source region 9 is a junction gate region 7
P-type drain region formed on both sides of, 10 n ⁺ -type reset drain voltage V ₁ of the constant potential is applied,
11 is a reset gate for discharging signal charges accumulated in the junction gate region 7 to the reset drain 10;
Reference numeral 12 denotes ap ⁺ -type channel stopper provided in the surface region of the p-type well 2 so as to surround the active region, 13 denotes a thick oxide film, and 14 denotes a load transistor.

In the above charge transfer device, the junction gate type field effect transistor for charge detection has a junction gate region 7, a source region 8, and a drain region 9, and the p-type well 2 below the junction gate region 7 is used as a channel. It is configured as an area.

Next, the operation of the conventional example will be described. The signal charges transferred in the charge transfer region 3 are transferred to the junction gate region 7 and accumulated therein. The hole current flowing through the p-type well 2 immediately below the gate region due to the potential change of the gate region 7 caused by this [in FIG.
[Indicated by an arrow] is modulated. This change in current is converted into a voltage signal via the load transistor 14 and detected from the output terminal Out. Next, the charge is discharged to the reset drain 10 by the voltage control of the reset gate 11, the voltage of the junction gate region 7 is reset to the reset voltage V _1. By repeating the above operation, the transferred charges can be sequentially converted into voltages and detected.

[0006]

In the above-described conventional charge transfer device, the capacitance of the junction gate region is used as a method of converting charges into a voltage. Therefore, in order to obtain a high-sensitivity output signal, it is necessary to reduce the total capacitance of the junction gate region. In order to reduce the capacitance, generally, the area of the gate region should be as small as possible. It is necessary to make it small. However, in the charge detector of this type, the junction gate region constitutes the gate of the junction type FET, and reducing this size decreases the gain of the source follower, which is not necessarily an advantageous measure. Further, the distance between the source region in the junction gate region and the drain region arranged around the junction gate region greatly affects the characteristics of the source follower. Therefore,
Reduction of the junction gate region increases variation in device characteristics. Accordingly, it is an object of the present invention to provide a charge transfer device having good sensitivity and stable characteristics by reducing the capacitance without reducing the area of the junction gate region.

[0007]

According to the present invention, there is provided a charge transfer element of a second conductivity type provided in a semiconductor region of a first conductivity type and partitioned into an element isolation region of a first conductivity type. A charge transfer element main body having a charge transfer electrode formed on a charge transfer region via a gate insulating film, and provided in the first conductivity type semiconductor region adjacent to an output end of the charge transfer element main body; A second conductivity type annular gate region receiving the transfer of the signal charge from the charge transfer element body, a first conductivity type source region provided in the annular gate region through the region, and a periphery of the annular gate region A junction field effect transistor having a first conductivity type drain region connected to the element isolation region, and a part of the first conductivity type semiconductor region as a channel region;
A charge discharging mechanism for extracting signal charges accumulated in the annular gate region, wherein the annular gate region is formed thinner than the charge transfer region .

[0008]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a plan view of one embodiment of the present invention, and FIGS. 1B and 1C show the BB line and C line, respectively.
It is sectional drawing of the -C line. As shown in the figure, the charge transfer element main body includes a charge transfer region 3 formed in a p-type well 2 surrounded by a channel stopper 12 and a charge formed thereon via a gate insulating film 6. It is constituted by the transfer electrode 4.

A junction gate type field effect transistor for detecting a signal charge transferred by a charge transfer element body includes an n-conductivity type junction gate region 7 disposed at a subsequent stage of the charge transfer element body via an output gate 5. P-type source region 8 provided in junction gate region 7 through the region
And a p-type drain region 9 provided on both sides of the junction gate region 7 so as to be in contact with the channel stopper, and a portion of the p-type well 2 below the junction gate region 7 serving as a channel region.

[0010] The reset transistor for resetting the junction gate region 7, a junction gate region 7 serving as a source region, a reset drain 10 voltage V ₁ of the constant voltage is applied, the reset pulse phi _R is applied A reset gate 11.

The present embodiment is different from the conventional example shown in FIG. 3 in that a thick oxide film 13 is formed on the junction gate region 7. With this configuration, the distance between the junction gate region 7 and the output gate 5 and the reset gate 11 is increased, and the thickness of the junction gate region is reduced, so that the total capacitance is reduced. Therefore, according to the present embodiment, the sensitivity can be improved without reducing the area of the junction gate region. For example, the impurity concentration of the p-type well 2 as 1 × 10 ¹⁵ cm ^-3, by the 3000Å thickness of the oxide film on the junction gate region from 1000 Å, the total volume of this region from 0.03 pF 0 It was able to reduce about 15% to 0.025 pF.

Next, the manufacturing method of this embodiment will be described with reference to FIG. First, a p-type well 2 is formed on an n-type silicon substrate 1, and an n-type impurity is selectively introduced into a surface region of the p-well to form a charge transfer region (3) and a junction gate region 7. Next, a silicon nitride film 15 is grown on the entire surface of the substrate by the CVD method, and the nitride film is formed except on the charge transfer region (3), the source region (8), the drain region (9) and the reset drain (10). Is removed. Next, a photoresist mask 16 is formed so as to cover the active region.
Is formed, and boron (B) is ion-implanted to form the channel stopper 12 (FIG. 2A).

Next, after removing the photoresist mask 16 and performing thermal oxidation to form a thick insulating film 13, the silicon nitride film 15 is removed [FIG. 2 (b)]. Next, the source region 8 and the drain region 9 are formed by ion implantation of boron (FIG. 2C). Subsequently, a reset drain (10) is formed by ion implantation of phosphorus (P) and a gate insulating film (6) is formed by a conventional method, and then a charge transfer electrode (4), an output gate (5), and a reset gate are formed. (11)
To form

The embodiments of the present invention have been described above.
The present invention is not limited to this embodiment, and various modifications can be made. For example, the drain region of a junction field effect transistor is not formed as a special region,
A portion of the channel stopper can be used instead. Also, the conductivity types can be all reversed from those of the embodiment.

[0015]

As described above, according to the present invention, the thickness of the insulating film on the junction gate region is made larger than that of the gate insulating film immediately below the charge transfer electrode. Can be reduced to reduce the capacitance of the junction gate region that converts the voltage into a voltage, and the signal detection sensitivity can be improved. Further, according to the present invention, it is not necessary to shorten the distance between the source and the drain of the junction field effect transistor, so that it is possible to suppress the manufacturing variation of the charge detection unit, and to improve the yield and the characteristics. Stabilization can be achieved.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view illustrating one embodiment of the present invention.

FIG. 2 is a process cross-sectional view for explaining a manufacturing method according to one embodiment of the present invention.

FIG. 3 is a plan view and a cross-sectional view of a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 n-type silicon substrate 2 p-type well 3 charge transfer region 4 charge transfer electrode 5 output gate 6 gate insulating film 7 junction gate region 8 source region 9 drain region 10 reset drain 11 reset gate 12 channel stopper 13 thick insulating film 14 load transistor 15 Silicon nitride film 16 Photoresist mask

Claims (1)

(57) [Claims] A second conductive type charge transfer region provided in the first conductive type semiconductor region and partitioned into a first conductive type element isolation region; and a gate insulating film formed on the charge transfer region. A charge transfer element main body having a charge transfer electrode formed therein, and receiving a signal charge from the charge transfer element main body provided in the first conductivity type semiconductor region adjacent to an output end of the charge transfer element main body. A second conductivity type annular gate region, a first conductivity type source region provided in the annular gate region through the region, and an element isolation region provided around the annular gate region; First
A junction field effect transistor having a conductivity type drain region and using a part of the first conductivity type semiconductor region as a channel region; and a charge discharging mechanism for extracting signal charges stored in the annular gate region Wherein the annular gate region is formed thinner than the charge transfer region, and an insulating film thicker than the gate insulating film is formed on the annular gate region. Charge transfer device.