JPH04369230A - Charge coupled device - Google Patents

Abstract

PURPOSE:To eliminate a sensitivity changeover switch by a method wherein an output circuit is provided with the holding region of a signal charge and the potential of the holding region of the signal charge is distributed in a step shape. CONSTITUTION:An N-type layer 120 which is depleted by a voltage which is lower than a reset drain voltage VRD is formed. Then, when a signal charge amount is made small and a sensitivity is made high, a signal charge Q is accumulated in a floating diffusion layer 11 whose capacity is small. Then, when the signal charge amount is made large and a dynamic range is required, a signal charge Q' is accumulated in the floating diffusion layers 11 and 120, and the capacity of the floating diffusion layers can be increased. Consequently, the substantial capacity of the floating diffusion layers executing a charge-to- voltage conversion operation can be increased without installing a sensitivity changeover gate electrode as the signal charge amount is increased. As a result, when the signal charge amount is small, a sensitivity can be increased; when the signal charge amount is large, the dynamic range can be increased.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a charge-coupled device.
In particular, the present invention relates to a charge coupled device that can reduce random noise in an output circuit, increase the amount of saturated charge, and is suitable for miniaturization.

0002

[Prior Art] FIGS. 2(a) and 2(b) are plan views of conventional output circuits, and FIGS. 2(c) and 2(d) are height views of the output circuits shown in FIGS. 2(a) and 2(b). This is a potential diagram of charges accumulated in the floating diffusion layer during high sensitivity and low sensitivity. This is disclosed in Japanese Unexamined Patent Publication No. 1-166561.

In FIG. 2, 7 is a P-type semiconductor substrate; 13 is a P-type semiconductor substrate;
5 is an insulating film, 1 is a transfer channel, 2 to 5 are transfer electrodes made of polycrystalline silicon, etc., 6 is an output gate electrode, 1
0, 11, and 13 are N-type regions, 14 is a reset gate electrode, and 15 and 16 are sensitivity switching gate electrodes. Note that SEL1 and SEL2 are switching control signals that are applied to the sensitivity switching gate electrodes at appropriate times. Further, the output is subjected to charge-voltage conversion and impedance conversion by the floating diffusion layer 11, the charge detection transistor T1, and the resistor R, and is taken out from the terminal VOUT. In addition, φ1, φ2, V
OG is a clock pulse for changing the potential of the transfer channel 1 and transferring signal charges to the floating diffusion layer 11, and φR is a clock pulse for discharging the signal charges.

Next, operations at high sensitivity and low sensitivity will be explained using FIGS. 2(b) to 2(d). First, when trying to obtain high sensitivity, the switching signal SEL1 for sensitivity switching is set to low level as shown in FIG. 2(c), and the signal is transferred to the floating diffusion layer 11 via the transfer electrode and the output electrode. Accumulates the signal charge. At this time, the potential change ΔVSIH due to the signal charge Q of the floating diffusion layer 11 is:

00
05]

[Equation 1] ΔVSIH=Q/C11

...(1). Here, C11 is the sum of the capacitance of the floating diffusion layer 11 with respect to the substrate and the capacitance of the wiring connected to the floating diffusion layer 11.

Next, in the case of low sensitivity, as shown in FIG. 1(d), the switching signal SEL1 for switching the sensitivity is set to a high level to open the second MOS transistor and make the floating diffusion layers 11 and 12 conductive. At this time, the switching signal SEL2 for sensitivity switching is set to low level. Potential change ΔVS of floating diffusion layers 11 and 12 due to signal charge amount Q
IL is

[0007]

[Equation 2] ΔVSIL=Q/(C11+C12)

...(2). Here, C11 is the same as above,
C12 is the sum of the capacitance of the floating diffusion layer 12 to the substrate and the capacitance to the adjacent gate.

In this way, in the conventional example, by changing the substantial capacitance of the floating diffusion layer that performs charge-voltage conversion using the sensitivity switching signals SEL1 and SEL2, the sensitivity is high when the amount of signal charge is small, and the sensitivity is high when the amount of signal charge is small. When the amount of charge is large, the sensitivity is lowered to increase the dynamic range.

[0009]

[Problem to be solved by the invention] However, the problem that the circuit becomes complicated because it is necessary to switch the sensitivity when the amount of signal charge is small and when the amount of signal charge is large was not considered. .

An object of the present invention is to solve this problem and eliminate the need for a sensitivity changeover switch.

[0011]

[Means for Solving the Problems] The above object is achieved by making the potential distribution of the floating diffusion layer step-like.

0012

[Operation] This is achieved by making the potential distribution of the floating diffusion layer step-like. As a result, the substantial capacitance of the floating diffusion layer can be automatically increased as the amount of signal charge increases, making it possible to eliminate the need for a sensitivity changeover switch.

[0013]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of an output circuit to which the present invention is applied, A-A
' This shows a cross-sectional view and potential distribution. This embodiment differs from the conventional example shown in FIG. 2 in that the gate electrode for sensitivity switching is eliminated, and an N-type layer 120 that is depleted at a voltage lower than the reset drain voltage: VRD is newly provided. As a result, when high sensitivity is to be obtained with a small amount of signal charge, the signal charge Q is accumulated in the floating diffusion layer 11 having a small capacitance, as shown in FIG. 1(c). Next, when the amount of signal charge is large and a dynamic range is required, the signal charge Q' is accumulated in the floating diffusion layers 11 and 120 as shown in FIG. 1(d), making it possible to increase the capacitance of the floating diffusion layer. can. In this way, in this embodiment, the effective capacity of the floating diffusion layer that performs charge-voltage conversion can be increased as the amount of signal charge increases without providing a sensitivity switching gate electrode, so when the amount of signal charge is small, It has high sensitivity and can provide a large dynamic range when the amount of signal charge is large.

FIG. 3 shows a plan view and an A-A' cross-sectional view of the output circuit of the second embodiment of the present invention, and a diagram showing the potential distribution of the A-A' cross-section in FIG. Shown in Figure 4. One difference between this embodiment and the embodiment shown in FIG. 1 is that electrodes 30, 31, and 32 fixed at constant potentials are newly provided on floating diffusion layers 123, 26, and 27. This allows the insulating film 3 to be removed without changing the structure on the substrate side.
By changing the thickness of 3, 34, and 35, the floating diffusion layer 123
, 26, and 27 can be freely set. Another reason is that a plurality of N-type layers 26 and 27 are provided, which are depleted at a voltage lower than the reset drain voltage: VRD. Here, it is assumed that the N-type layer 27 is depleted at a lower voltage than the N-type layer 26. As a result, when trying to obtain high sensitivity with a small amount of signal charge, the signal charge QA1 is transferred to the floating diffusion layer 12 with a small capacitance, as shown in FIG. 4(a).
It is accumulated in 3. When the amount of signal charges increases and a dynamic range becomes necessary, the signal charges QA2 are accumulated in the floating diffusion layers 123 and 26, as shown in FIG. 4(b), and the capacitance of the floating diffusion layers can be increased. If the amount of signal charge increases further and a dynamic range is required, use the method shown in Figure 4 (
As shown in c), the signal charge QA3 is transferred to the floating diffusion layer 123,
26 and 27, and the capacitance of the floating diffusion layer can be further increased. Thereby, the capacitance of the floating diffusion layer can be set more precisely according to the amount of signal charge. It should be noted that the well structures 21 and 22 are provided to improve the characteristics of the image sensor, and the details thereof will be omitted.

FIG. 9 shows a plan view and an A-A' cross-sectional view of the output circuit of the fifth embodiment of the present invention, and a diagram showing the potential distribution of the A-A' cross-section in FIG. It is shown in FIG. This embodiment differs from the embodiments shown in FIGS. 3 and 4 in that the width of the N-type layer 26 is changed so that it is depleted at a voltage lower than the reset drain voltage: VRD. Due to the influence of lateral diffusion, the N-type region 26-1 is larger than the N-type region 26-1.
6-2 has a lower impurity concentration, so the N-type region 26
-1, the N-type region 26-2 is depleted at a lower voltage. As a result, even if one type of N-type layer 26 is used, a potential distribution similar to that shown in FIG. 4 can be realized as shown in FIG. 10. Note that the same effect can be obtained even if the width of the N-type layer is smoothly changed.

FIG. 5 shows a sectional view of an output circuit according to a third embodiment of the present invention. The difference between this embodiment and the embodiment shown in FIG. 3 is that an electrically floating electrode 8 made of, for example, polycrystalline Si is provided on the floating diffusion layers 123, 26, 27 via an insulating film 42 of about 100 nm.
1, 82, and 83 have been installed. This allows the potential distribution within the substrate to be defined more firmly and prevents potential pockets from occurring.

FIG. 6 shows a sectional view of an output circuit according to a fourth embodiment of the present invention. This embodiment differs from the embodiment shown in FIG. 3 in that dense P-type diffusion layers 113, 114, and 115 are used to create a stepped potential distribution. This prevents depletion of the Si--SiO2 interface and suppresses 1/f noise generated by interface traps. Note that 117 is an N-type layer provided to ensure smooth transfer of signal charges, 112 is an insulating film, 116 is an electrode fixed at a constant potential, 113, 1
14 and 115 are electrically floating.

The present invention can of course also be applied to floating well type charge detectors. FIG. 7 shows a cross-sectional view of a conventional floating well type charge detector. This element is described in Osawa et al., TV Society National Conference 2-12 (1988), "High Sensitive Charge Detector for CCD." A conventional floating well type charge detector, as shown in this figure, has N
A P-type well layer 41 is formed on the type substrate 20, and an N-type CCD channel layer 103 is formed within the P-type well layer 41. The gate electrode 105 of the charge detection transistor of the output circuit has a size of 5 μm×5 μm, an oxide film 106 of 1 μm thickness, and an FPP (Flat Potential Pl).
The thickness of the oxide film 42 under the oxide film 104 is 93 nm. Note that the FPP 104 is an electrically floating polycrystalline Si gate. Further, boron ions are implanted to form a P channel 43 under the charge transfer channel 103. In the conventional example, signal charge detection is performed using the gate electrode 10 of the charge detection transistor of the output circuit.
This is done by modulating the hole current 101 flowing from the source 100 to the drain 44 by the signal charge 102 transferred below the source 100.

As described above, according to the conventional example, the hole current 101
does not flow through the Si-SiO2 interface 45, and therefore does not include 1/f noise generated by interface traps. Furthermore, by increasing the thickness of the gate oxide film 106 to 1 μm, the detection capacitance is reduced and high sensitivity is achieved. However, no consideration was given to the fact that the saturated charge amount is as small as 2000 electrons, and therefore the dynamic range is small.

FIG. 8 shows a cross-sectional view of a conventional floating well type charge detector in the charge transfer direction. The signal charge 102 is connected to the final gate electrode 47 of the CCD.
The hole current 101 is transferred to the gate electrode 105 of the charge detection transistor of the output circuit, and modulates the hole current 101 flowing from the source 100 to the drain 44 . Then, it passes under the reset gate 48 and is discharged to the reset drain 108.

The embodiments of the present invention shown in FIGS. 5 and 6 can be applied to the conventional floating well type charge detector shown in FIG. 8 in exactly the same manner.

[0022]

Effects of the Invention According to the present invention, by making the potential distribution of the floating diffusion layer step-like, the effective capacitance of the floating diffusion layer can be increased as the amount of signal charge increases. Switches can be made unnecessary.

[Brief explanation of drawings]

FIG. 1 is a plan view of an output circuit according to a first embodiment of the present invention, A
-A' cross-sectional view and potential distribution diagram.

FIG. 2 is a plan view, an A-A' sectional view, and a potential distribution diagram of a conventional output circuit.

FIG. 3 is a plan view and a sectional view taken along line AA' of an output circuit according to a second embodiment of the present invention.

FIG. 4 is a potential distribution diagram of an output circuit according to a second embodiment of the present invention.

FIG. 5 is a sectional view of an output circuit according to a third embodiment of the present invention.

FIG. 6 is a sectional view of an output circuit according to a fourth embodiment of the present invention.

FIG. 7 is a cross-sectional view of a conventional output circuit.

FIG. 8 is a cross-sectional view of a conventional output circuit.

FIG. 9 is a plan view and a sectional view taken along line A-A' of an output circuit according to a fifth embodiment of the present invention.

FIG. 10 is a potential distribution diagram of an output circuit according to a fifth embodiment of the present invention.

[Explanation of symbols]

11, 12, 123... floating diffusion layer, 26, 27, 120
...N-type layer depleted at a voltage lower than the reset drain voltage, 30-32, 105, 116... Electrode fixed at a constant potential, 33-35, 106, 112... Interlayer insulating film.

Claims (4)

[Claims] 1. A charge coupling device comprising a transfer element formed on a semiconductor substrate that transfers signal charges and an output circuit that converts the signal charges into voltage and takes out the signal charges, wherein the output circuit is located in the signal charge holding area. A charge-coupled device characterized in that the potential distribution of the signal charge holding region is step-like. 2. A charge coupling device comprising a transfer element formed on a semiconductor substrate that transfers signal charges and an output circuit that converts the signal charges into voltage and takes out the signal charges, wherein the output circuit includes a storage area for the signal charges. and a reset transistor for discarding the signal charge, and the width of the signal charge holding region becomes narrower as the distance from the reset transistor increases. 3. In claim 1, the signal charge holding region has an impurity region of the same conductivity type as the signal charge that holds the signal charge, and the impurity region is composed of a plurality of regions having different impurity concentrations. Charge coupled device. 4. The charge-coupled device according to claim 3, wherein electrodes fixed to a constant potential are provided on the plurality of regions having different impurity concentrations via insulating films having different thicknesses.