JP2003347537A - Solid-state image pickup element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve knee characteristics in a vertical overflow drain system CCD solid-state image pickup element. <P>SOLUTION: In the vertical overflow drain system solid-state image pickup element where a first-conductivity-type overflow barrier region is provided, and a plurality of light receiving sensor sections 22 are aligned in a matrix, a first-conductivity-type impurity introduction region 41 is formed between adjacent light receiving sensor sections 22 in a vertical direction. In the first- conductivity-type impurity introduction region 41, ground potential for forming capacity to the ground at a portion to the overflow barrier region is applied. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a vertical overflow drain type solid-state imaging device used for a digital still camera, a camera-integrated VTR, and the like.

[0002]

2. Description of the Related Art In recent years, with the development of digital technology, digital still cameras have become widespread and have been widely accepted due to their convenience. In addition, this digital camera is being replaced by a silver halide camera (a so-called film camera) because development is not required and data can be exchanged very easily, and the pursuit of higher definition is desired. . Current,
Digital still cameras for consumer use range from 2 million to 300
Although a solid-state image pickup device having a class of 10,000 pixels is mainly used, it is said that a larger number of pixels are required to realize image quality equivalent to that of a silver halide camera. At present, along with the demand for increasing the number of pixels, there is a strong demand for maintaining the characteristics and further improving the characteristics. Similarly, the number of pixels in a solid-state imaging device for a camera-integrated VTR has been increasing in recent years, and a demand for higher definition has been increasing.

FIG. 5 shows an example of a conventional vertical overflow drain type CCD solid-state imaging device. FIG. 3 is a cross-sectional structure showing a main part of the imaging region. The CCD solid-state imaging device 1 includes a plurality of light receiving sensor units 2 each composed of, for example, a photodiode, which constitute pixels, and is arranged in a matrix. The imaging device has an imaging area in which the section 3 is formed, and a horizontal transfer is performed at a vertical end of the imaging area via a storage area (not shown) having a plurality of vertical transfer register sections, or not. A register section is provided, and an output section is connected to the horizontal transfer register section via charge-voltage conversion means.

In the imaging region, an overflow barrier region 6 made of a second conductivity type, for example, a p-type semiconductor region is formed in a silicon semiconductor substrate 5 of a first conductivity type, for example, an n-type. A photodiode comprising an n-type semiconductor region (so-called charge storage region) 7 constituting the sensor section 2 and a surface p-type semiconductor region 8 thereon is formed. On one side of the light receiving sensor section row, an n constituting a vertical transfer register section 3 is provided via a p-type read gate section 9.
A buried region 10 is formed.
A type semiconductor well region 11 is formed. On the other side of the light receiving sensor unit row, a pixel separation region for separating pixels adjacent in the horizontal direction, that is, a p-type channel stop region 1
2 are formed. This p-type channel stop region 12
Is electrically connected to the surface p-type semiconductor region 8 of the light receiving sensor unit 2 and a ground potential is applied. The surface p-type semiconductor region 8 becomes a so-called hole accumulation region, and is formed at an interface between the n-type charge accumulation region 7 and an insulating film 13 described later in order to reduce dark current.

An insulating film 13 is formed on the surface of the semiconductor substrate 5, and a transfer electrode made of, for example, a two-layer film of polycrystalline silicon is formed on the n-type buried region 10 and the read gate portion 9 via a gate insulating film 13G. 14 are formed. The vertical transfer resist portion 3 is constituted by the n-type buried region 10 and the transfer electrode 14. Further, the transfer electrode 14 is
And an opening 17 in a part corresponding to the light receiving sensor unit 2.
Light-shielding film 16 made of, for example, an Al film
Is formed.

In this CCD solid-state imaging device 1, as shown in FIG. 6, during normal imaging operation, the p-type channel stop region 12 and the surface p-type semiconductor region 8 are set to the ground potential,
A predetermined substrate bias voltage V _sub is applied to the mold semiconductor substrate 5. The signal charge (electrons in this example) e photoelectrically converted by the light receiving sensor unit 2 is stored in the n-type charge storage region 7. Excess charge is discharged to the substrate 5 side beyond the overflow barrier phi _A. At the time of the electronic shutter operation, a considerable ΔV _sub is applied in addition to the substrate bias voltage v _sub, and all the charges accumulated in the n-type charge accumulation region 7 are swept away to the substrate 5 side.

That is, the electric potential of the overflow barrier region 6 can be controlled by the substrate bias voltage, and the amount of signal charges that can be stored in the n-type charge storage region 7 can be changed with a certain degree of freedom. I have.

[0008]

In the case of a CCD solid-state imaging device used in a digital still camera, it is important to sufficiently accumulate the signal charges for the dynamic range and the S / N ratio. It is needless to say that storing a large signal (signal charge) in the light receiving sensor unit 2 is beneficial. However, when a large amount of light is incident, that is, when there is a signal charge that overflows from the n-type charge storage region 7 in the light-receiving sensor unit 2, the charge flows out from the n-type charge storage region 7 toward the substrate 5, and it is as if. The state is such that a negative bias is applied to the overflow barrier region 6, and the substrate bias value required during the normal imaging operation is reduced. That is, as shown by the broken line 19 in FIG. 6, the potential level of the overflow barrier gradually becomes shallow, and as a result, more charges are accumulated, so-called knee characteristics appear. Ideally, the signal charge that is photoelectrically converted with respect to the light amount should change linearly.However, since the charge overflows toward the substrate, the linearity collapses, and the linearity of the sensitivity is maintained for the CCD solid-state imaging device. It becomes a state that does not drip. This is because the controllability of the overflow barrier due to the substrate bias is weak. In order to suppress the knee characteristics, it is desired that the electric potential of the overflow barrier region 6 does not fluctuate even when the signal charges flow out of the overflow barrier toward the substrate.

The present invention has been made in view of the above circumstances, and provides a solid-state imaging device capable of suppressing knee characteristics.

[0010]

A solid-state image pickup device according to the present invention is a solid-state image pickup device of a vertical overflow drain type, wherein a first light-receiving sensor section is provided between vertically adjacent light-receiving sensors.
A structure in which a first conductivity type impurity introduction region to which a ground potential for forming a capacitance to ground is applied between the first conductivity type impurity barrier region and the conductivity type overflow barrier region is formed.

In the solid-state imaging device according to the present invention, since the first conductivity type impurity introduction region of the ground potential is formed between the light receiving sensor portions adjacent in the vertical direction, a pair of the first conductivity type overflow barrier region is formed. Even if the ground capacitance becomes large and the excess charge exceeds the overflow barrier when a large amount of light enters, the fluctuation of the electric potential in the overflow barrier region is suppressed.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the solid-state imaging device according to the present invention will be described below with reference to the drawings.

FIGS. 1 to 4 show an embodiment of a solid-state imaging device according to the present invention, that is, a CCD solid-state imaging device of a vertical overflow drain type. FIG. 3 shows a main part of the imaging area. In the CCD solid-state imaging device 21 according to the present embodiment, a plurality of light receiving sensor units 22 each including a photodiode, for example, constituting a pixel are arranged in a matrix, and one side of each light receiving sensor unit row extending in the vertical direction is provided with a CCD.
It has an imaging area 24 in which a vertical transfer register section 23 having a CD structure is formed. At an end in the vertical direction of the imaging area 24, a storage area having a plurality of vertical transfer register sections (not shown) is provided. Alternatively, the horizontal transfer register section is arranged without any intervention, and an output section is connected to the horizontal transfer register section via a charge-voltage converter.

In the imaging region 24, an overflow barrier region 26 made of a first conductivity type, for example, a p-type semiconductor region is formed in a second conductivity type, for example, an n-type silicon semiconductor substrate 25. Light receiving sensor section 22
Semiconductor region (so-called charge storage region) 2 constituting
7 and a photodiode comprising the surface p-type semiconductor region 28 thereon. On one side of each light receiving sensor section row, an n-type buried region 30 forming the vertical transfer register section 23 is formed via a p-type read gate section 29, and n
A p-type semiconductor well region 31 is formed below the mold buried layer 30. On the other side of each light receiving sensor unit row, an element isolation region for separating pixels adjacent in the horizontal direction, that is, a p-type channel stop region 32 is formed. The p-type channel stop region 32 is electrically connected to the surface p-type semiconductor region 28 of the light receiving sensor unit 22, and a ground potential is applied. The surface p-type semiconductor region 28 is a so-called hole accumulation region, and is used to reduce the dark current.
7 and an insulating film 33 described later, and is formed in a stripe shape in the vertical direction so as to be common to the respective light receiving sensor units 2 in the vertical direction. p-type channel stop region 32
Are also formed in a stripe shape in the vertical direction along the vertical transfer resist portion 23.

An insulating film 33 is formed on the surface of the semiconductor substrate 25.
Is formed, and n-type buried region 30 and read gate unit 2 are formed.
A transfer electrode 34 [34A, 34B] made of, for example, a two-layer film of polycrystalline silicon is formed on the gate electrode 9 via a gate insulating film 33G. The n-type buried region 30 and the transfer electrode 34 constitute a vertical transfer resist portion 23. Further, the transfer electrode 34 is covered with an interlayer insulating film 35 to partially cover the light receiving sensor unit 2.
A light-shielding film in which an opening 37 is formed in a portion corresponding to 2, in this example, an Al light-shielding film 36 is formed.

[0016] In this embodiment, in particular, between adjacent pixels in the vertical direction, i.e. between the light receiving sensor section 22, a ground potential to form a ground capacitance C _A between the overflow barrier region 26 is applied A first conductivity type impurity introduction region, that is, a p-type impurity introduction region 41 formed by, for example, ion implantation is formed. The p-type impurity introduction region 41 can be formed by ion-implanting a p-type impurity with a required implantation energy, for example, several hundred keV or less. In this example, the p-type impurity introduction region 41 is required to be connected to the surface p-type semiconductor region 28 immediately below the surface p-type semiconductor region 28 extending between the light receiving sensor units 22 adjacent in the vertical direction. Formed over a depth of

The p-type impurity introduction region 41 must be at the same electric potential as the p-type channel stop region 32 and the surface p-type semiconductor region 28, that is, at the ground potential. Therefore, for example, when formed by ion implantation, two-stage ion implantation is performed with different implantation energies, and the p-type impurity introduction region 41 of a required depth is brought into contact with the lower surface of the surface p-type semiconductor region 28. Form. The impurity concentration of the p-type impurity-introduced region 41 is such that a required capacitance with respect to the ground, that is, a parasitic capacitance that suppresses a change in the barrier potential of the overflow barrier region 26 is formed between the p-type impurity introduction region 41 and the overflow barrier region 26. It is sufficient if the concentration is sufficient. The concentration of the p-type impurity introduction region 41 is, for example, 1.0
It can be about × 10 ¹⁶ cm ^{−3 to} 3.0 × 10 ¹⁹ cm ⁻³ . The concentration of the p-type channel stop region 32 and the surface p-type semiconductor region 28 is, for example, about 1.0 × 10 ¹⁹ cm ⁻³ .

On the other hand, the charges photoelectrically converted by the light receiving sensor section 22 are read out to the vertical transfer resist section 23 through the readout gate section 29. The change in the electric potential of the read gate unit 29 leads to a read failure. In the manufacturing process of the CCD solid-state imaging device, since there is a process to which heat is applied, impurities in the p-type impurity introduction region 41 diffuse to the read gate portion 29 side by heat treatment, and the electric potential of the read gate portion 29 fluctuates. Must be avoided.

Therefore, the p-type impurity introduction region 41 is formed in a pattern shape which does not affect the electric potential of the read gate portion 29. p-type impurity introduction region 41
For example, as shown in FIG. 1, it can be formed in a cross pattern so as to cover the width of the opening 37 of the light shielding film 36. Further, in a photolithography step of transferring a pattern, a completed shape largely depends on a pattern mask. Therefore, in the p-type impurity introduction region 41, emphasis is placed on left-right symmetry, and
It is preferable to make the pattern shape symmetrical to the left and right. As described above, the p-type impurity introduction region 41 is formed so as to prevent the electric potential of the read gate portion 29 from fluctuating due to the diffusion of the impurity due to heat. Must be similarly avoided, and the electrical potential of the light receiving sensor section 22 must be formed so as not to cause a variation. In this example, the cross pattern is used to minimize the influence on the electric potential of the light receiving sensor unit 22 and to make the same potential as the p-type channel stop region 32 and the surface p-type semiconductor region 28. Shape p
The mold impurity introduction region 41 is partially (eg, 1/1 of the horizontal opening width) of the light receiving sensor portion 22 corresponding to the edge of the opening 37.
(Approximately 3 ranges). In order to make contact between the p-type impurity introduction region 41 and the p-type channel stop region 32 and the surface p-type semiconductor region 28,
The type impurity introduction region 41 may be formed so as to enter the opening 37.

The pattern shape of the p-type impurity-doped region 41 is not limited to the cross pattern shape, but may be any shape that does not affect the electric potential of the readout gate unit 29 and the electric potential of the light-receiving sensor unit 22, that is, If the pattern shape is such that it does not approach the read gate unit 29 and the number of parts that contact the light receiving sensor unit is reduced,
Can be adopted.

In the CCD solid-state image pickup device 21 of the vertical overflow drain type according to the present embodiment, the signal charges photoelectrically converted by the light receiving sensor unit 22 and accumulated in the n-type charge accumulation region 27 are read out as usual. The signal is read out to the vertical transfer resisting section 23 through the gate section 29, transferred to the vertical transfer resisting section 23, transferred to the horizontal transfer register section, output from the horizontal transfer register section via the charge-voltage converter, and output from the output section. You. As described with reference to FIG. 6, the p-type channel stop region 32 and the surface p-type semiconductor region 28 are set to the ground potential during the normal imaging operation, and the predetermined substrate bias voltage V is applied to the n-type semiconductor substrate 25.
_{When sub} is applied, the signal charge e is stored in the n-type charge storage region 27. Excess charge is discharged to the substrate 25 side over the overflow barrier phi _A, at the time of the electronic shutter operation, all in addition to the substrate bias voltage v _sub applying a substantial [Delta] V _sub, accumulated in the n-type charge accumulation region 27 The electric charge e is swept away to the substrate 25 side.

According to the above-described CCD solid-state image pickup device 21 according to the present embodiment, the p-type semiconductor region 28 which is connected to the grounded surface p-type semiconductor region 28 and extends below the light-receiving sensor portion 22 adjacent to each other in the vertical direction. since -type impurity doped region 41, the capacitance to ground associated with the overflow barrier region 26 (so-called parasitic capacitance) C _a is larger than conventional, overflow substrate bias barrier region 26
To improve the controllability of the electric potential. In other words, even when the excess charge exceeds the overflow barrier at the time of the large amount of light incident, the fluctuation of the electric potential in the overflow barrier region can be suppressed, and so-called knee characteristics can be suppressed.

In the case of the conventional solid-state imaging device 1 shown in FIG. 5, the capacitance to ground associated with the overflow barrier region 6 is a parasitic capacitance between the overflow barrier region 6 and the p-type channel stop region 12. However, the p-type channel stop region 12 is
Since there is a distance of about 2 μm, the parasitic capacitance value associated with the overflow barrier region is not large enough. The capacity C is generally C = ε _O / S / d [where ε _O
Is the dielectric constant, S is the electrode area, and d is the distance between the electrodes. The above-mentioned capacitance to ground in the present embodiment is compared with the above-mentioned capacitance to ground in the conventional example at the same pixel size. In the present embodiment, the area of the p region facing the overflow barrier region is the total area of the p-type channel stop region 32 and the p-type impurity-doped region 41 and is larger than that of the conventional p-type channel stop region 12 alone. . In addition, the distance between the overflow barrier region and the p region opposed thereto is larger than the distance d ₁ (see FIG. 5) between the conventional p-type channel stop region 12 and the overflow barrier region 6 in the present embodiment. In this case, the distance d ₂ between the p-type impurity introduction region 41 and the overflow barrier region 26 is shorter. Therefore, in the present embodiment, the parasitic capacitance associated with the overflow barrier region becomes sufficiently large as compared with the conventional example, and the electric potential fluctuation of the overflow barrier region 26 can be suppressed. In the configuration shown in FIG. 5, the surface p-type semiconductor region 13
When the present embodiment is compared with a comparative example in which is also extended between the light receiving sensor units 2 that are vertically adjacent to each other, the grounding capacitance of the overflow barrier region is greater in the present embodiment. growing. That is, although the area constituting the capacitor is the same, the distance between the overflow barrier region and the p-type region is shorter in the present embodiment by the presence of the p-type impurity-doped region 41. With respect to the ground.

Since the p-type impurity-doped region 41 is formed with a required depth between the light-receiving sensors 22 adjacent in the vertical direction, it is possible to prevent signal charges of upper and lower pixels adjacent in the vertical direction from being mixed. Pixel color mixing can be prevented. That is, in recent years, the demand for increasing the number of pixels has increased, and as the unit pixels have become finer, it has become difficult to maintain various characteristics. Therefore, in order to accumulate the same amount of charge as that of a relatively large unit pixel in the light receiving sensor unit, there may be a case where the electric potential of the light receiving sensor unit is deepened. In such a case, it is necessary to prevent the signal charges of the upper and lower pixels adjacent to each other in the vertical direction from being mixed at a deep position from the semiconductor surface. In the present embodiment, since the p-type impurity-doped region 41 is formed to a required depth within a range that does not reach the overflow barrier region 26, color mixing of pixels can be avoided.

When the p-type impurity introduction region 41 is formed in a pattern shape that does not affect the electric potential of the read gate portion 29, for example, a cross pattern shape, the influence on the read gate portion 29 is suppressed to a small value, and the read gate It is possible to suppress almost no change in the electric potential of the portion 29, and to improve the reading of the signal charges into the vertical transfer resist portion 23. Further, by making the p-type impurity introduction region 41 a cross-shaped pattern and reducing the contact portion with the light receiving sensor unit 22, the influence on the electric potential of the light receiving sensor unit can be minimized. By forming the p-type impurity-introduced region 41 so as to partially overlap the light-receiving sensor section 22, misalignment due to patterning peculiar to photolithography when the p-type impurity-introduced region 41 is formed is reduced. , A minute white spot defect can be suppressed.

In the CCD solid-state imaging device 21, the signal charges are electrons. The generated holes are discharged through the surface p-type semiconductor region 28 and the p-type channel stop region 32 at the ground potential because only the electrons of the photoelectrically converted hole electron pair are used as signal charges. In the present embodiment, since the p-type impurity introduction region 41 can be formed to a deep region between pixels, various defects such as minute white spot defects due to holes can be prevented.

The present invention can be applied to an IT (interline transfer) type and FIT (frame interline transfer) type CCD solid-state imaging device.

[0028]

According to the solid-state imaging device of the present invention, the first ground potential is applied between the light-receiving sensors adjacent to each other in the vertical direction to form a grounding capacitance with the overflow barrier region. By forming the conductive type impurity introduction region, the capacitance to ground accompanying the overflow barrier region is increased, and the electric potential variation of the overflow barrier region when a large amount of light is incident can be suppressed. Therefore, knee characteristics can be suppressed. That is, the knee characteristics are improved. A light-receiving sensor unit having a charge accumulation region of a second conductivity type and a surface first conductivity type region thereon;
When the surface first conductivity type region is connected to the pixel isolation region and the first conductivity type impurity introduction region is formed immediately below the front surface first conductivity type region extending between the vertically adjacent light-receiving sensors. A ground potential is applied to the first conductivity type impurity introduction region through the pixel isolation region and the surface first conductivity type region, and a ground capacitance is formed between the first conductivity type impurity introduction region and the overflow barrier region. Therefore, knee characteristics can be suppressed.

Since the first conductivity type impurity introduction region is formed with a required depth, it is possible to prevent the signal charges of the upper and lower pixels adjacent in the vertical direction from being mixed.

When the first conductivity type impurity-introduced region has a pattern shape which does not change the electric potential of the readout gate portion, signal charges from the light receiving sensor portion can be satisfactorily read out to the vertical transfer resist portion.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a main part showing an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is an enlarged sectional view taken on line AA of FIG. 1;

FIG. 3 is an enlarged sectional view taken on line BB of FIG. 1;

FIG. 4 is an enlarged sectional view taken on line CC of FIG. 1;

FIG. 5 is a sectional view of a main part showing an example of a conventional solid-state imaging device.

FIG. 6 is a diagram illustrating the operation of a vertical overflow drain type solid-state imaging device.

[Explanation of symbols]

21: CCD solid-state imaging device, 22: light receiving sensor unit, 23: vertical transfer resist unit, 24: second conductivity type semiconductor substrate, 26: first conductivity type overflow barrier region, 26 ... Second conductivity type charge storage region, 28
... Surface first conductivity type region, 29... Readout gate portion, 30... Second conductivity type buried region, 31.
Conductive type semiconductor well region, 32... First conductive type channel stop region, 33... Insulating film, 33G... Gate insulating film, 34... Transfer electrode, 35. ..Light shielding film, 37 ... opening

Claims (3)

[Claims] 1. A vertical overflow drain type solid-state imaging device having a first conductivity type overflow barrier region and a plurality of light receiving sensor units arranged in a matrix, wherein the light receiving sensors are vertically adjacent to each other. A solid-state imaging device, wherein a first conductivity type impurity-introduced region to which a ground potential for forming a capacitance with respect to ground is formed between the portion and the overflow barrier region is formed. 2. The light-receiving sensor section has a charge accumulation region of a second conductivity type and a surface first conductivity type region thereon, and has a first conductivity type connected to the surface first conductivity type region. A pixel isolation region is formed, and the first conductivity type impurity-introduced region is formed immediately below the surface first conductivity type region extending between the light receiving sensor units adjacent in the vertical direction. Item 2. The solid-state imaging device according to Item 1. 3. The solid according to claim 1, wherein said first conductivity type impurity-introduced region has a pattern shape which does not change the electric potential of a read gate connected to a vertical transfer register. Imaging device.