JP6727897B2 - Solid-state imaging device, method of manufacturing solid-state imaging device, and imaging system - Google Patents

Description

The present invention relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an imaging system.

A solid-state imaging device such as a CMOS image sensor or a CCD image sensor is provided with a light blocking member that prevents light from entering a portion other than a photoelectric conversion unit that performs photoelectric conversion. For example, a CMOS image sensor having a global electronic shutter (batch simultaneous exposure for all pixels) function has a charge holding unit that holds the charges transferred from the photoelectric conversion unit. When light enters the charge holding portion and photoelectric conversion occurs, the photoelectrically converted charges become noise, which may deteriorate image quality. Therefore, the charge holding portion is covered with a light shielding member to prevent light from entering. Further, in the CCD image sensor as well as in the CMOS image sensor, when light enters the reading section, it causes noise, so the reading section is covered with a light shielding member.

In a solid-state imaging device having a light blocking member, since an optically transparent interlayer insulating film exists between the substrate and the light blocking member, the light blocking performance can be improved by preventing light entering through the interlayer insulating film. Has been planned. In Patent Document 1, the insulating film provided under the light shielding member is etched to reduce the thickness of the insulating film. By thinning the insulating film under the light shielding member to reduce the distance between the photoelectric conversion unit and the lower surface of the light shielding member, leakage of light to the charge holding unit is suppressed and the light shielding performance is improved.

JP 2012-248681 A

When the gap between the gate electrodes has a certain size, when the insulating film is formed on the adjacent gate electrodes and the light-shielding film is formed, there is a portion where the insulating film is sufficiently flat between the gate electrodes. Therefore, even if the light-shielding film is etched, residues are unlikely to occur. On the other hand, due to the miniaturization of the semiconductor process, the distance between the gate electrodes becomes narrow. When a light-shielding film serving as a light-shielding member is formed on this narrow space and the light-shielding film is etched, residues of the light-shielding film may exist inside the narrow space. Such residues can cause leaks. In Patent Document 1, an insulating film is formed below the light-shielding film to fill the recesses between the gate electrodes and between the wirings, thereby alleviating the step. This can reduce the generation of etching residues on the light-shielding film. However, in Patent Document 1, although it is possible to fill a recess that is narrower than a certain interval, it is not possible to completely fill a recess that is larger than the interval and a narrow gap remains, and a light shielding member remains in this gap. was there. Even if the insulating film to be embedded is thickened, a gap is generated depending on the distance between the recesses, and it is not possible to completely prevent the generation of residues.

Further, if the flatness of the surface of the insulating film is impaired due to the step of the gate electrode, the flatness of the light shielding member and the structure formed thereon may be similarly deteriorated, and the yield may be reduced. An object of the present invention is to provide a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an imaging system that can improve the yield while maintaining the light-shielding performance of the light-shielding member.

A method for manufacturing a solid-state imaging device according to an embodiment of the present invention includes a first transistor, a first region, a second region, a third region, and a fourth region on a substrate having a first region, a second region, a third region, and a fourth region . a gate electrode adjacent to said first gate electrode and a second gate electrode of the second transistor, the first gate electrode is positioned on the first region, said second gate a step of the electrode is positioned on the second region, the gap between the first gate electrode and the second gate electrode can be on the top of the fourth region, said fourth Forming an insulator film covering the first region and the first gate electrode and the second gate electrode, and shading covering the third region and the fourth region on the insulator film. a step of forming a film made of sexual material, of the light-shielding made of a material film which is located above the void across the insulator film, located on at least the fourth region Forming a light-shielding member on the third region from a film made of the light-shielding material by etching a part of the material; the light- shielding member, the first gate electrode, and the second gate electrode Forming an insulating film covering the insulating film, and forming a contact plug penetrating the insulating film to connect to either the first transistor or the second transistor,
On the insulating film, have a, and forming a wiring connected to the contact plug, in the step of forming a film made of the light shielding material, and the insulator film and the fourth region There is a void between them.

Manufacturing method of another embodiment solid-state imaging device according to the embodiment of the present invention, the etching time of the ratio of the insulator layer to the etch time of the light-shielding made of a material film a, the light-shielding of the light shielding member When the etching selection ratio between the film made of a material and the insulating film is b, the film thickness of the insulating film is t, and the film thickness of the light shielding member is d ₁ , the insulating film is a×b×d It is formed so as to satisfy ₁ ≦t .

A solid-state imaging device according to another embodiment of the present invention is located on the substrate having the first region, the second region, the third region, and the fourth region, and is located on the first region. A second gate electrode of a second transistor located above the first gate electrode of the first transistor and the second region and adjacent to the first gate electrode, and the third gate electrode of the second transistor. A region, the fourth region, an insulating film that covers the first gate electrode and the second gate electrode, and the insulating film is disposed between the insulating film and the substrate, and the third region and the fourth region. An insulator film covering the first gate electrode and the second gate electrode, and a light blocking member provided between the insulating film and the third region,
A wiring provided on the insulating film, wherein a portion of the insulating film covering the third region is located between the light shielding member and the third region , located in the gap of said gate electrode a second gate electrode over the fourth region, there is a void between said fourth region and said fourth region covering part of said insulator layer To do.

According to the present invention, the yield can be improved while maintaining the light shielding performance of the solid-state imaging device.

3 is a block diagram of the solid-state imaging device according to the first embodiment of the present invention. FIG. FIG. 3 is a schematic cross-sectional view showing the structure of the solid-state imaging device according to the first embodiment of the present invention. FIG. 6 is a process sectional view illustrating the method of manufacturing the solid-state imaging device according to the first embodiment of the present invention. FIG. 9 is a schematic cross-sectional view showing the structure of the solid-state imaging device according to the second embodiment of the present invention. FIG. 6A is a process sectional view illustrating the method of manufacturing the solid-state imaging device according to the second embodiment of the present invention. FIG. 11 is a block diagram of a solid-state image pickup device according to a third embodiment of the present invention. It is a top view which shows the structure of the solid-state imaging device by 3rd Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the solid-state imaging device by 3rd Embodiment of this invention. FIG. 13A is a process sectional view illustrating the method of manufacturing the solid-state imaging device according to the third embodiment of the present invention. FIG. 13A is a process sectional view illustrating the method of manufacturing the solid-state imaging device according to the third embodiment of the present invention. FIG. 13A is a process sectional view illustrating the method of manufacturing the solid-state imaging device according to the third embodiment of the present invention. It is a block diagram of an imaging system by a 4th embodiment of the present invention.

(First embodiment)
The solid-state imaging device and the method for manufacturing the same according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a solid-state imaging device according to this embodiment. The solid-state imaging device includes a pixel region 10 having a plurality of pixel circuits 1 arranged in a matrix, and a peripheral region 20 located around the pixel region and having peripheral circuits arranged therein. The pixel circuit 1 includes a photoelectric conversion unit that performs photoelectric conversion and a reading unit that reads out electric charges. The reading unit includes a transfer transistor that transfers charges, a transistor that resets the charge-voltage conversion unit, an amplification transistor that outputs a signal according to the potential of the charge-voltage conversion unit, and a transistor that selects the amplification transistor. In addition, the reading unit may include a charge holding unit that holds a charge from the photoelectric conversion unit. Incident light is blocked by a light blocking member in a circuit portion other than the photoelectric conversion portion, for example, a charge holding portion. Further, in the pixel region 10, a color filter for controlling the spectral sensitivity characteristic and a microlens for condensing light are provided on the photoelectric conversion units, and light is blocked between the photoelectric conversion units to prevent color mixing. A member can be formed. Further, the pixel region 10 may include pixels that do not output an image, such as an optical black pixel in which the photoelectric conversion unit is shielded from light, a dummy pixel having no photoelectric conversion unit, in addition to the effective pixel.

The peripheral region 20 includes a vertical scanning circuit 21, a column amplification circuit 22, a horizontal scanning circuit 23, and an output section 24. The vertical scanning circuit 21 supplies a control signal for controlling the transistor of the pixel circuit 1 to be on (conductive state) or off (non-conductive state). The vertical signal line 11 is provided in each column of the pixel circuit 1 and reads out a signal from the pixel circuit 1 for each column. The column amplifier circuit 22 includes a differential amplifier circuit and a sample hold circuit, and amplifies the pixel signal output to the vertical signal line 11. The horizontal scanning circuit 23 supplies a switch connected to the amplifier of each column and a control signal for controlling the switch to be turned on or off. The output unit 24 includes a buffer amplifier and a differential amplifier, and outputs the pixel signal from the column amplification circuit 22 to a signal processing unit outside the solid-state imaging device. The output pixel signal is subjected to processing such as analog/digital conversion and correction of input data by the signal processing unit. The solid-state imaging device may be a so-called digital sensor having an analog/digital conversion function.

FIG. 2 is a schematic cross-sectional view of the solid-state imaging device according to the present embodiment. Here, two arbitrary first transistors 206 and second transistors 207 that are adjacent to each other in plan view are shown. The transistors 206 and 207 are, for example, transistors included in the pixel circuit 1. Two adjacent transistors 206 and 207 have a pair of gate electrodes 201 and 202 adjacent to each other, and a void 302 exists between these gate electrodes 201 and 202. The transistor having the pair of gate electrodes having the void 302 between them may be either the pixel circuit 1 or the peripheral circuit.

The semiconductor substrate 100 has a surface parallel to the XY plane including the X-axis direction and the Y-axis direction, and the semiconductor substrate 100 has the first conductivity type having a predetermined thickness in the Z-axis direction (first direction). A well 101 (for example, P type) is provided. An element isolation region 102 that defines an active region is provided on the surface of the semiconductor substrate 100 where the well 101 is formed. In the active region defined by the element isolation region 102, impurity regions 203, 204, 205 having a conductivity type opposite to that of the well 101 (for example, N type) are provided separately from each other.

A gate electrode 201 is provided over the semiconductor region (channel region) between the impurity regions 203 and 204 with a gate insulating film 103 interposed therebetween. As a result, a transistor 206 having the impurity regions 203 and 204 forming the source/drain regions and the gate electrode 201 is formed. Here, the source/drain region means a semiconductor region which can function as at least one of a source and a drain of a transistor. Depending on the driving method of the transistor, the same semiconductor region may function as a source or a drain, and the same semiconductor region functions as a source of a transistor and a drain of another transistor. There is also. Similarly, the gate electrode 202 is provided over the semiconductor region (channel region) between the impurity regions 204 and 205 with the gate insulating film 103 interposed therebetween. As a result, a transistor 207 having the impurity regions 204 and 205 forming the source/drain regions and the gate electrode 202 is formed. These two transistors 206 and 207 share one source/drain region (impurity region 204). The distance between the gate electrodes 201 and 202 of the two transistors 206 and 207 is narrow, for example, about 1.0 μm or less. Typically, the distance between the gate electrode 201 and the gate electrode 202 is smaller than the sum of the thicknesses of the gate electrode 201 and the gate electrode 202 and is 0.5 μm or less. The distance between the gate electrode 201 and the gate electrode 202 may be 0.1 μm or more.

In addition, the thickness and the film thickness of the member here refer to the length in the Z-axis direction (first direction) perpendicular to the plan view of the semiconductor substrate 100. The direction in which layers such as a gate electrode, an insulating film, and a light shielding member described later are stacked on the semiconductor substrate 100 can be defined as the Z-axis direction. In the following description, the thickness and the film thickness of a member refer to the length in the Z-axis direction unless otherwise specified.

An insulator film 301 is provided over the semiconductor substrate 100 provided with the transistors 206 and 207. The insulator film 301 is not completely embedded in the gap between the gate electrode 201 and the gate electrode 202, and at least a part of the region between the gate electrode 201 and the gate electrode 202 has a void (hole) 302. Has been formed. By forming the void 302 in at least a part of the region between the gate electrode 201 and the gate electrode 202, the flatness of the surface of the insulator film 301 on this region can be improved. That is, the influence of the step difference of the base formed by the gate electrode 201 and the gate electrode 202 is mitigated on the surface portion of the insulator film 301 on the region between the gate electrode 201 and the gate electrode 202. A light-shielding member 308 made of a light-shielding material such as tungsten or tungsten silicide is provided in a part of the insulating film 301. By forming the void 302, the surface of the insulating film 301 can be planarized, and a residue can be prevented from being generated when the light-blocking film is etched over the insulating film 301 to form the light-blocking member 308. it can.

An interlayer insulating film 310 is provided on the insulating film 301. A contact hole penetrating the interlayer insulating film 310 and the insulator film 301 is formed, and contact plugs 311a to 311c are provided in the contact hole. The contact plug 311a is connected to the gate electrode 201, and the contact plug 311b is connected to the gate electrode 202. The contact plug 311c is connected to the source/drain region (impurity region 205). The contact plugs 311a-c are connected to the wirings 312a-c.

3A to 3D are process cross-sectional views showing the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. As shown in FIG. 3A, an element isolation region 102 that defines an active region is formed on the surface portion of the semiconductor substrate 100 by using, for example, an STI (Shallow Trench Isolation) method or a LOCOS (LOCal Oxidation of Silicon) method. Form. Then, the well 101 is formed in a predetermined region of the semiconductor substrate 100 by an ion implantation method.

After forming the well 101, a gate insulating film 103 made of, for example, a silicon oxide film is formed on the surface of the active region of the semiconductor substrate 100 by using a thermal oxidation method, a CVD method, or the like. A polysilicon film, for example, is deposited on the entire surface of the semiconductor substrate 100 on which the gate insulating film 103 is formed by, for example, the CVD method. This polysilicon film is patterned by using photolithography and dry etching to form gate electrodes 201 and 202 made of the polysilicon film. Next, ion implantation is performed using the gate electrodes 201 and 202 as masks to form impurity regions 203, 204 and 205 in the semiconductor substrate 100 in a self-aligned manner with respect to the gate electrodes 201 and 202 as source/drain regions. To do.

Thus, the transistor 206 having the impurity regions 203 and 204 and the gate electrode 201 and the transistor 207 having the impurity regions 204 and 205 and the gate electrode 202 are formed in the active region of the semiconductor substrate 100.

Next, as shown in FIG. 3B, an insulator film 301 such as a silicon oxide film is deposited on the semiconductor substrate 100 on which the transistors 206 and 207 are formed. At this time, the insulator film 301 is formed so that the insulator film 301 is not completely embedded in the gap between the gate electrode 201 and the gate electrode 202. Thereby, the void 302 is formed in at least a part of the region between the gate electrode 201 and the gate electrode 202. Typically, in the insulating film forming conditions, the more isotropic components and the faster the film forming rate, the more likely voids will remain in the narrow gap. In consideration of such a point, the insulating film 301 is formed while leaving the void 302 by appropriately setting the film forming conditions of the insulating film 301 according to the distance between the gate electrodes 201 and 202 and the film thickness. can do.

As a concrete film forming condition, a film is formed by using a CVD method having small anisotropy or fluidity such as a parallel plate plasma CVD method using a TEOS-O ₂ system or SiH ₄ -O ₂ system gas species. It is preferable. This is because as the film formation speed increases, voids 302 that are voids are easily formed between the gate electrode 201, the gate electrode 202, and the insulator film 301, while a gap sufficiently narrower than the void 302 is blocked. This is because the depression of the film on the void can be reduced.

In this example, the gas flow rate was TEOS: 265 sccm, O ₂ : 2.5 sccm, and the pressure was 360 Pa. Further, a plasma CVD oxide film equivalent to 500 Å was formed by setting RF output to the upper electrode 720W and the lower electrode 320W and forming the film for 4 seconds.

When the insulator film 301 is formed so as to fill the gap on the pattern arranged at a narrow interval such as the gate electrodes 201 and 202, the surface portion of the insulator film 301 between the gate electrode 201 and the gate electrode 202 is formed. A fine recess is formed on (a surface opposite to the surface in contact with the gate electrodes 201 and 202). When a film is deposited in this fine recess in a later step, it may not be completely removed when the film is subsequently etched, and may remain as a residue. In particular, when this film is a conductive film, this residue causes a short circuit between wirings, which causes a defect. By forming the insulator film 301 so as to leave the void 302 between the gate electrodes 201 and 202, as compared with the case where the insulator film 301 is formed so as to fill the gap between the gate electrodes 201 and 202, The depression on the area between 202 can be reduced.

Next, as shown in FIG. 3C, a light-shielding film 309 made of, for example, tungsten, tungsten silicide, or the like is formed on the insulator film 301 by using a sputtering method, a CVD method, or the like. Further, after forming the light shielding film 309, the light shielding film 309 is patterned into a predetermined shape by using photolithography and dry etching. Thereby, as shown in FIG. 3D, the light blocking member 308 is formed from the light blocking film 309. In this patterning, the portion of the light shielding film 309 located above the photoelectric conversion portion can be removed. Further, in the light-shielding film 309, the portion located above the contact portion to be formed later can also be removed. In this example, of the light-shielding film 309, the portion located above the impurity region 204 between the gate electrodes 201 and 202, that is, the portion located above the void 302 is removed. At this time, no depression is formed on the surface of the insulator film 301 so that the residue of the light shielding film 309 remains. That is, the flatness of the surface of the insulator film 301 on the region between the gate electrodes 201 and 202 can be improved, and the etching residue of the light shielding film 309 can be avoided. Further, even when it is not necessary to remove the light blocking film 309 on the impurity region 204 between the gate electrodes 201 and 202, the flatness of the surface of the insulator film 301 is improved, and thus the flatness of the light blocking member 308 is improved. The effect that can be obtained is obtained.

Further, according to this embodiment, the effect that the film thickness of the insulator film 301 can be reduced can be obtained. As another means for reducing the step difference on the surface of the insulator film 301, increasing the thickness of the insulator film 301 can be considered. However, when the thickness of the insulator film 301 is increased, the distance between the light blocking member 308 and the semiconductor substrate 100 is increased, and the light blocking performance is deteriorated. On the other hand, according to the present embodiment, the film thickness of the insulating film can be reduced without causing a step on the surface of the insulating film 301. For example, the thickness of the insulator film 301 can be made smaller than the thickness of the gate electrodes 201 and 202. Therefore, the distance between the light blocking member 308 and the semiconductor substrate 100 can be shortened, and the light blocking performance can be improved.

From the viewpoint of light shielding properties, the height of the lower surface of the light shielding member 308 not formed on the gate electrode 201 is preferably lower than the height of the upper surfaces of the gate electrodes 201 and 202. That is, the film thickness of the insulator film 301 is preferably thinner than the film thickness of the gate insulating film 103 and the film thickness of the gate electrodes 201 and 202 added together. Since the thickness of the gate insulating film 103 is typically smaller than that of the gate electrodes 201 and 202, if the thickness of the insulator film 301 is smaller than that of the gate electrodes 201 and 202. It is enough.

After that, as shown in FIG. 2, an interlayer insulating film 310 that covers the light blocking member 308 and the gate electrodes 201 and 202 of the plurality of transistors is formed. The interlayer insulating film 310 is flattened by an etch back method, a CMP method, a reflow method, or the like. Then, a contact hole penetrating the interlayer insulating film 310 and the insulator film 301 to reach the semiconductor substrate 100, the gate electrodes 201 and 202, or the light shielding member 308 is formed. The contact plugs 311a to 311c are formed by embedding a conductive material such as tungsten in the contact holes. The contact plugs 311a to 311c penetrate the interlayer insulating film 310 and the insulating film 301 and are connected to one of the plurality of transistors 206 and 207. On the other hand, no contact plug is formed on the impurity region 204, that is, on the void 302. If a contact hole is provided so as to penetrate the void 302, a conductive material may enter the void 302 when forming a contact plug, but such a situation can be avoided if the contact hole is not provided on the void 302. When it is necessary to connect the contact plug to the impurity region 204, it is preferable to form the contact plug at a position away from the void 302. Since the light shielding film 309 is removed from the portions where the contact plugs 311a to 311c pass, the contact plugs 311a to 311c are formed apart from the light shielding member 308. A contact plug (not shown) connected to the light blocking member 308 can be further formed. Further, wirings 312a to 312c connected to the contact plugs 311a to 311c are formed on the interlayer insulating film 310.

The insulator film 301 also functions as an etch stopper film when the light shielding member 308 is etched. If the thickness of the insulator film 301 is smaller than the thickness of the insulator film 301 that is etched by over-etching when etching the light shielding member, the surface of the semiconductor substrate 100 is exposed when the light shielding member 308 is etched and the semiconductor substrate 100 is etched. Damage is added. This etching damage causes dark current and the like.

Here, in the Z-axis direction (first direction) in which the gate electrode 201 of the first transistor 206, the insulating film 301, and the light blocking member 308 are stacked, the film thickness of the insulating film 301 is t, and the film of the light blocking member 308 is t. Let the thickness be d ₁ . Further, the ratio of the over-etching time to the main etching time at the time of etching the light shielding member is a, and the selection ratio of the insulator film 301 to the light shielding member 308 at the time of etching the light shielding member is b. At this time, the thickness of the insulator film 301 etched at the time of etching the light shielding member is a×b×d ₁ . Therefore, it is preferable that the film thickness t of the insulator film 301 is a×b×d ₁ or more.

Further, if the light shielding member 308 and the wirings 312a to 312c come into contact with each other, it may cause a leak or the like. In the Z-axis direction, the film thickness of the gate electrodes 201 and 202 is d ₂ , the smallest distance among the distances from the wirings 312 a to 312 c to the semiconductor substrate 100 is d ₃ , and the thickness of the gate insulating film 103 is d ₄ . At this time, the film thickness t of the insulator film 301 is preferably thinner than d ₃ −(d ₁ +d ₂ +d ₄ ).

From the viewpoint of light shielding properties, the thicker the insulating film 301, the wider the distance between the light shielding member 308 and the semiconductor substrate 100 and the lower the light shielding performance. Shows good shading performance.

A specific example will be described below. When tungsten is used for the light blocking member 308, the film thickness d ₁ is preferably 0.1 μm or more in order to obtain sufficient light blocking ability. The transmittance of tungsten is 0.2% or less at a thickness of 0.1 μm or more, and a sufficient light-shielding ability can be achieved.

When the ratio a of the over-etching time to the main etching time at the time of etching the light blocking member is 0.1 and the selection ratio b of the insulating film 301 to the light blocking member 308 is 0.1, the film thickness t of the insulating film 301 It must be at least 1.0 nm or more. In practice, it is necessary to consider manufacturing variations and the like, so that the insulator film thickness is preferably 5.0 nm or more.

Further, the film thickness d ₁ of the light shielding member 308 is 0.1 μm, the film thickness d _{2 of the} gate electrode is 0.2 μm, the distance d ₃ between the wirings 312a to 312c and the semiconductor substrate 100 is 0.6 μm, and the film of the gate insulating film is formed. When the thickness d ₄ is 8.0 nm, it is preferable that the thickness t of the insulator film 301 is at least smaller than 0.3 μm in order to prevent contact with the wiring. Actually, the manufacturing process variation of the interlayer insulating film and the light shielding member occurs, and the light shielding performance decreases as the film thickness t of the insulating film 301 increases. Therefore, the film thickness t of the insulating film 301 should be 0.1 μm or less. Is preferred.
Therefore, the thickness of the insulator film 301 is preferably 1 nm or more and less than 0.3 μm, more preferably 5 nm or more and 0.1 μm or less.

As described above, according to this embodiment, it is possible to reduce the depressions on the surface of the insulator film formed between the gate electrodes, and improve the flatness of the base of the structure formed on this region. be able to. In particular, when the conductive film formed on the region between the gate electrodes is removed by etching, it is possible to prevent the conductive film residue from remaining in the recess of the insulating film, which improves the manufacturing yield. Can be planned.

(Second embodiment)
The solid-state imaging device and the manufacturing method according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a schematic cross-sectional view showing the structure of the solid-state imaging device according to the present embodiment, and FIG. 5 is a process cross-sectional view showing the method for manufacturing the solid-state imaging device according to the present embodiment. The same components as those of the solid-state imaging device according to the first embodiment shown in FIGS. 1 to 3 are designated by the same reference numerals, and the description thereof will be omitted or simplified.

As shown in FIG. 4, the solid-state imaging device according to the present embodiment is shown in FIG. 2 except that sidewall spacers 304, 305, 306, and 307 are formed on the side surfaces of the gate electrodes 201 and 202. It is substantially the same as the solid-state imaging device according to the first embodiment. Since the sidewall spacers 305 and 306 are formed on the opposite side surfaces of the gate electrodes 201 and 202, the void 302 is formed between the sidewall spacers 305 and 306. Also in this embodiment, the void 302 is formed without being filled with the insulator film 301 in the gap between the gate electrodes 201 and 202, so that the flatness of the surface of the insulator film 301 on the void 302 is improved. You can

Next, the method for manufacturing the solid-state imaging device according to the present embodiment will be explained with reference to FIGS. In FIG. 5A, the well 101, the element isolation region 102, the first transistor 206, and the second transistor 207 are formed in the semiconductor substrate 100 in the same manner as in the method of manufacturing the solid-state imaging device according to the first embodiment. .. A dielectric film 303 made of, for example, a silicon oxide film is formed on the entire surface by a CVD method or the like. Subsequently, as shown in FIG. 5B, the dielectric film 303 is etched back to form sidewall spacers 304, 305, 306, 307 on the side surfaces of the gate electrodes 201, 202. It should be noted that the dielectric film and the insulating film are merely different in name for convenience, and the material forming the dielectric film and the material forming the insulating film may be the same.

Next, as shown in FIG. 5C, an insulator film such as a silicon oxide film is formed on the semiconductor substrate 100 on which the sidewall spacers 304, 305, 306, and 307 are formed by using the plasma CVD method or the like. 301 is deposited. At this time, the insulator film 301 is formed so that the insulator film 301 is not embedded in the gap between the sidewall spacers 305 and 306 between the gate electrodes 201 and 202. As a result, the void 302 remains in at least a part of the region between the gate electrode 201 and the gate electrode 202. By forming the insulator film 301 so as to form the void 302 between the gate electrodes 201 and 202, the depression formed in the region between the gate electrodes 201 and 202 can be reduced.

Next, a light-shielding film made of tungsten, tungsten silicide, or the like is formed on the insulator film 301 by a sputtering method, a CVD method, or the like. Further, the light shielding member 308 is formed by patterning the light shielding film into a predetermined shape using photolithography and dry etching. Here, a portion of the light shielding film located above the impurity region 204 between the gate electrodes 201 and 202 is removed. At this time, since no depression is formed on the surface of the insulator film 301 on the region between the gate electrodes 201 and 202, the etching residue of the light shielding film can be suppressed.

Further, by forming the sidewall spacers 304, 305, 306, 307 on the side surfaces of the gate electrodes 201, 202, the steps of the gate electrodes 201, 202 are provided with a gradual slope. As a result, the coverage of the light blocking member 308 on the step portion, especially on the sidewall spacer 304, is improved, and the light blocking performance can be improved. Further, as in the first embodiment, the film thickness of the insulator film 301 is made thinner than the film thickness of the gate electrodes 201 and 202 and the film thickness of the gate insulating film 103, and the light shielding member 308 is formed. The distance between the semiconductor substrate 100 and the semiconductor substrate 100 can be shortened. This makes it possible to obtain good light shielding performance.

As in the first embodiment, the insulator film 301 is also an etch stopper film during etching of the light shielding member, so the thickness of the insulator film 301 should be thicker than the thickness of the insulator film etched during etching of the light shielding member. Is preferred. Note that in the Z-axis direction (first direction) in which the gate electrode 201 of the first transistor 206, the insulating film 301, and the light shielding member 308 are stacked, the thickness of the insulating film 301 is t, and the thickness of the light shielding member 308 is t. Be d ₁ . Further, the ratio of the over-etching time to the main etching time at the time of etching the light shielding member is a, and the etching selection ratio of the insulating film 301 to the light shielding member at the time of etching the light shielding member is b. In that case, since the thickness of the insulator film 301 that is etched during the etching of the light shielding member is a×b×d ₁ , t is preferably a thickness of a×b×d ₁ or more.

Further, when the light blocking member 308 and the wiring come into contact with each other, it causes a leak or the like. In the Z-axis direction, when the film thickness of the gate electrodes 201 and 202 is d ₂ , the smallest distance from the wirings 312 a to 312 c to the semiconductor substrate 100 is d ₃ , and the thickness of the gate insulating film 103 is d _4. The film thickness t of the insulator film 301 is preferably thinner than d ₃ −(d ₁ +d ₂ +d ₄ ).
As the method of forming the insulator film 301, the same method as in the first embodiment can be used.

As described above, according to this embodiment, it is possible to reduce the depressions on the surface of the insulator film formed between the gate electrodes, and improve the flatness of the base of the structure formed on this region. be able to. In particular, when the conductive film formed on the region between the gate electrodes is removed by etching, it is possible to prevent the conductive film residue from remaining in the recess of the insulating film, which improves the manufacturing yield. Can be planned. Further, by forming the sidewall spacer on the side surface of the gate electrode, the light shielding performance can be improved.

(Third Embodiment)
The solid-state imaging device and the method for manufacturing the same according to the third embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a block diagram of the solid-state imaging device of this embodiment. The solid-state imaging device includes a pixel region 501 including a plurality of pixel circuits 401, and a peripheral region 502 including peripheral circuits such as a vertical scanning circuit 530, a column amplification circuit 531 and a horizontal scanning circuit 532. Although the pixel circuit 501 of 2 rows and 2 columns is shown in the pixel region 501 of FIG. 6, the number of pixels is not limited. The pixel circuit 401 includes a photoelectric conversion unit 402, a charge holding unit 403, a charge-voltage conversion unit 404, a power supply unit 405, a pixel output unit 407, first and second transfer transistors M1 and M2, a reset transistor M3, an amplification transistor M4, A selection transistor M5 and an overflow drain (hereinafter referred to as OFD) transistor M6 are provided. The photoelectric conversion unit 402 includes a microlens, a photodiode, and the like, and accumulates charges according to incident light. The photoelectric conversion unit 402 is electrically connected to the transistor M6 for OFD and the first transfer transistor M1. The transistor M6 discharges the electric charge of the photoelectric conversion unit 402 to the power supply unit 405 according to the control signal OFD(n) supplied to the gate electrode.

The first transfer transistor M1 transfers the charge from the photoelectric conversion unit 402 to the charge holding unit 403 according to the control signal TX1(n) supplied to the gate electrode. The charge holding unit 403 holds the charges transferred via the transfer transistor M1. The second transfer transistor M2 transfers the charge held in the charge holding unit 403 to the charge-voltage conversion unit 404 according to the control signal TX2(n). The reset transistor M3 resets the voltage of the charge-voltage converter 404 to the voltage of the power supply unit 405 according to the control signal RES(n). The amplification transistor M4 outputs a signal corresponding to the potential of the gate electrode to the signal line OUT(m). The selection transistor M5 is electrically connected between the power supply unit 405 and the amplification transistor M4, and supplies a current to the amplification transistor M4 according to the signal SEL(n).

The power supply unit 405 has the same node as the drain of the reset transistor M3, the drain of the selection transistor M5, and the drain of the OFD. The vertical scanning circuit 530 supplies the control signals RES(n), TX1(n), TX2(n), SEL(n), and OFD(n) to the unit pixel circuit. The signal output from the signal line OUT is held in the column amplification circuit 531 and processed such as amplification and addition. The horizontal scanning circuit 532 sequentially outputs the signals held in the column amplifier circuit 531 to the output terminal OUT.

The operation of the global shutter in the solid-state imaging device according to the present embodiment will be described. After a certain storage period has elapsed, the charges generated in the photoelectric conversion unit 402 are transferred to the charge holding unit 403 via the transfer transistor M1. While the charge holding unit 403 holds the signal charges, the photoelectric conversion unit 402 starts to accumulate charges again. The charges in the charge holding unit 403 are transferred to the charge-voltage conversion unit 404 via the second transfer transistor M2 and output as a signal from the pixel output unit 407 which is one terminal of the amplification transistor M4. Further, the transistor M6 of the OFD discharges the charge of the photoelectric conversion unit 402 so that the charge generated in the photoelectric conversion unit 402 does not enter the charge holding unit 403 while the signal charge is held in the charge holding unit 403. Can be done. The reset transistor M3 sets the charge-voltage conversion unit 404 to a predetermined potential before the signal charge is transferred from the charge holding unit 403 (reset operation). The potential of the charge-voltage converter 404 at this time is output from the pixel output unit 407 to the column amplifier circuit 531 as a noise signal. Then, the reset transistor M3 is turned off, and a signal based on photoelectric conversion is output to the column amplification circuit 531. The column amplification circuit 531 outputs a signal of a difference between the noise signal and a signal based on photoelectric conversion, thereby generating a signal from which the noise signal is removed.

FIG. 7 is a plan view of the pixel region 501 of the solid-state imaging device according to the present embodiment as seen from the Z-axis direction. Although FIG. 7 shows the pixel circuits 401 of 3 rows×3 columns which form the pixel region 501, the number of pixels is not limited as described above. In each pixel circuit 401, the element isolation region 102 defines a substantially inverted S-shaped active region 102a. Gate electrodes 601 to 606 of the transistors M1 to M6 forming the pixel circuit are arranged on the active region 102a. That is, a plurality of gate electrodes 601, 602, 603, 604, 605 are arranged in this order from the lower side of the active region 102a in FIG. 7 so as to cross the active region 102a. Here, the gate electrode 601 is the gate electrode of the first transfer transistor M1, and the gate electrode 602 is the gate electrode of the second transfer transistor M2. The gate electrode 603 is the gate electrode of the reset transistor M3, and the gate electrode 604 is the gate electrode of the amplification transistor M4. The gate electrode 605 is the gate electrode of the selection transistor M5. The gate electrodes 604 and 605 are adjacent to each other in a plan view.

The active region 102a below the gate electrode 601 is the photoelectric conversion unit 402 formed of a photodiode. The active region 102a between the gate electrode 601 and the gate electrode 602 is a charge holding portion 403 that temporarily holds the charge transferred from the photoelectric conversion portion 402. A first transfer transistor M1 arranged between the photoelectric conversion unit 402 and the charge holding unit 403 is formed. The active region 102a between the gate electrode 602 and the gate electrode 603 is the charge-voltage converter 404.

The active region 102a is connected between the photoelectric conversion unit 402 and a connection portion (active region 102a between the gate electrodes 603 and 604) to the power supply voltage line, and the gate electrode of the transistor M6 of the OFD is provided on this connection portion. 606 is arranged. A light shielding member 308 is provided on the charge holding portion 403 and the gate electrodes 601 and 602. In FIG. 7, black circles schematically represent the contact portions for connecting to the wiring in the upper layer.

FIG. 8 is a schematic cross-sectional view of the pixel region and the peripheral region of the solid-state imaging device according to the present embodiment. That is, the pixel region 501 on the left side of FIG. 8 shows a cross section from the charge holding portion 403 of the line AA′ in FIG. 7 to the selection transistor M5, and the peripheral region 502 on the right side of the dotted line is the column amplification circuit path. Etc. show cross sections of any two transistors provided adjacent to each other in FIG. FIG. 8 also shows a sectional view parallel to the XY plane and a sectional view parallel to the YZ plane.

In the semiconductor substrate 100, a well 101 composed of a P-type semiconductor region and an element isolation region 102 are provided. In the pixel region 501, the element isolation region 102 defines a substantially inverted S-shaped active region 102a as shown in FIG. In the peripheral region 502, the element isolation region 102 defines an active region 102b.

The N-type semiconductor region 421 and the P-type semiconductor region 431, the N-type semiconductor region 422, the N-type semiconductor region 423, the N-type semiconductor region 424, and the N-type semiconductor region 425 are formed on the surface of the active region 102a of the pixel region 501. They are provided apart from each other. The N-type semiconductor region 421 is an impurity region forming the charge holding unit 403. The P-type semiconductor region 431 is a surface protection layer of the N-type semiconductor region 421. The N-type semiconductor region 422 is an impurity region (floating diffusion region) forming the charge-voltage converter 404. The N-type semiconductor region 423 is an impurity region forming the drains of the reset transistor M3 and the amplification transistor M4. The N-type semiconductor region 424 is an impurity region forming the source of the amplification transistor M4 and the drain of the selection transistor M5. The N-type semiconductor region 425 is an impurity region that constitutes the source of the selection transistor M5 and functions as the pixel output unit 407.

A gate electrode 602 is provided on the semiconductor substrate 100 between the N-type semiconductor region 421 and the N-type semiconductor region 422 with the gate insulating film 103 interposed therebetween. As a result, the second transfer transistor M2 having the source/drain regions formed by the N-type semiconductor regions 421 and 422 and the gate electrode 602 is formed. A gate electrode 603 is provided on the semiconductor substrate 100 between the N-type semiconductor region 422 and the N-type semiconductor region 423 with the gate insulating film 103 interposed therebetween. As a result, the reset transistor M3 having the source/drain regions formed by the N-type semiconductor regions 422 and 423 and the gate electrode 603 is formed. A gate electrode 604 is provided on the semiconductor substrate 100 between the N-type semiconductor region 423 and the N-type semiconductor region 424 with the gate insulating film 103 interposed therebetween. As a result, the amplification transistor M4 having the source/drain regions formed by the N-type semiconductor regions 423 and 424 and the gate electrode 604 is formed. A gate electrode 605 is provided on the semiconductor substrate 100 between the N-type semiconductor region 424 and the N-type semiconductor region 425 with the gate insulating film 103 interposed therebetween. As a result, the select transistor M5 having the source/drain regions formed by the N-type semiconductor regions 424 and 425 and the gate electrode 605 is formed.

N-type semiconductor regions 426, 427, and 428 are provided on the surface of the active region 102b of the peripheral region 502 so as to be separated from each other. A gate electrode 607 is provided on the semiconductor substrate 100 between the N-type semiconductor region 426 and the N-type semiconductor region 427 with the gate insulating film 103 interposed therebetween. As a result, the peripheral transistor 617 including the source/drain regions formed by the N-type semiconductor regions 426 and 427 and the gate electrode 607 is formed. A gate electrode 608 is provided on the semiconductor substrate 100 between the N-type semiconductor region 427 and the N-type semiconductor region 428 with the gate insulating film 103 interposed therebetween. Therefore, the peripheral transistor 618 having the source/drain regions formed by the N-type semiconductor regions 427 and 428 and the gate electrode 608 is formed. A metal silicide film 432 for reducing wiring resistance, diffusion layer resistance, contact resistance and the like is provided on the surface portions of the N-type semiconductor regions 426, 427 and 428 of the peripheral transistors 617 and 618 and the gate electrodes 607 and 608. There is. As the metal silicide film 432, cobalt silicide, titanium silicide, or the like can be applied.

Dielectric films 701 and 702 are provided on the semiconductor substrate 100 in the pixel region 501 so as to cover upper surfaces and side surfaces of the gate electrodes 602, 603, 604, and 605. Sidewall spacers 703a and 704 are provided on the side surfaces of the gate electrodes 602, 603, 604, and 605 covered with the dielectric films 701 and 702, respectively.

Sidewall spacers 701a are provided on the side surfaces of the pair of gate electrodes 607 and 608 of the peripheral transistors 617 and 618 arranged in the peripheral region 502. Further, on the semiconductor substrate 100 in the peripheral region 502, a dielectric film 703 is provided so that the side surface covers the upper surface and the side surface of the gate electrodes 607 and 608 covered with the sidewall spacer 701a. Sidewall spacers 704 are provided on the side surfaces of the gate electrodes 607 and 608 covered with the sidewall spacers 701a and the dielectric film 703.

An insulating film 301 is provided on the entire surface of the semiconductor substrate 100. The gap between the pair of gate electrodes 604 and 605 is not filled with the insulator film 301, and a void 801 is formed. That is, the void 801 exists in the region surrounded by the first and second gate electrodes 604 and 605 and the insulator film 301. The light blocking member 308 is not formed at a position facing the void 801 with the insulator film 301 interposed therebetween in the Z axis direction perpendicular to the plan view. Further, the gap between the pair of gate electrodes 607 and 608 is not filled with the insulator film 301, and a void 802 is formed. A light blocking member 308 is provided on the insulator film 301 in the pixel region 501 so as to cover the charge holding portion 403 and the gate electrode 602 of the second transfer transistor M2. Although not shown in FIG. 8, an interlayer insulating film, a contact hole penetrating the interlayer insulating film and the insulating film 301, and a contact hole connected to the contact hole are formed on the insulating film 301 as in FIG. Wiring is provided.

9 to 11 are process cross-sectional views showing the method of manufacturing the solid-state imaging device according to the present embodiment. In FIG. 9A, the element isolation region 102 that defines the active regions 102a and 102b is formed on the surface of the semiconductor substrate 100 by, for example, the STI method or the LOCOS method. Next, the well 101 formed of a P-type semiconductor region is formed in a predetermined region of the pixel region 501 and the peripheral region 502 by an ion implantation method. By the ion implantation method, the N-type semiconductor region 421 and the P-type semiconductor region 431 are formed in the formation region of the charge holding portion 403 of the pixel region 501.

A gate insulating film 103 made of a silicon oxide film or the like is formed on the surface portions of the active regions 102a and 102b of the semiconductor substrate 100 by using, for example, a thermal oxidation method or a CVD method. A polysilicon film, for example, is deposited on the entire surface of the semiconductor substrate 100 on which the gate insulating film 103 is formed by the CVD method. Next, the polysilicon film is patterned by using photolithography and dry etching to form gate electrodes 602, 603, 604, 605, 607 and 608 made of the polysilicon film. N-type semiconductor regions 422, 423, 424, 425 are formed in the semiconductor substrate 100 in the pixel region 501 by ion implantation in a self-aligned manner with the gate electrodes 602, 603, 604, 605.

Although an example in which the N-type semiconductor region 421 and the P-type semiconductor region 431 are formed before the gate electrodes 602 to 608 are formed is shown here, the N-type semiconductor region 421 and the P-type semiconductor region 421 are formed after the gate electrodes 602 to 608 are formed. The P-type semiconductor region 431 may be formed. In this case, the N-type semiconductor region 421 and the P-type semiconductor region 431 can also be formed in self-alignment with the gate electrode 602, like the N-type semiconductor regions 422, 423, 424, and 425.

Next, a dielectric film 701 such as a silicon oxide film is formed by a CVD method or the like on the entire surface of the semiconductor substrate 100 on which the gate electrodes 602 to 608 are formed. The dielectric film 701 may be used as an antireflection film by forming a laminated structure of a silicon oxide layer and a silicon nitride layer. After forming a photoresist film (not shown) that covers the pixel region 501 and exposes the peripheral region 502 by photolithography, the dielectric film 701 in the peripheral region 502 is etched back using this photoresist film as a mask. As a result, the dielectric film 701 is left in the pixel region 501, and side wall spacers (first dielectric film) made of the dielectric film 701 (first dielectric film) are formed on the side surfaces of the gate electrodes 607 and 608 in the peripheral region 502. A sidewall spacer) 701a is formed. Next, the photoresist film (not shown) used for the mask is removed by, for example, ashing.

Next, in FIG. 9B, ion implantation is performed on the peripheral region 502 using the gate electrodes 607 and 608 and the sidewall spacers 701a as masks. As a result, the N-type semiconductor regions 426, 427, and 428 to be the source/drain regions are formed in self-alignment with the gate electrodes 607 and 608 and the sidewall spacers 701a. Then, a dielectric film 702 is formed on the entire surface by, eg, CVD. This dielectric film 702 is used as a protective film for the pixel region 501 when forming the metal silicide film 432 in the peripheral region 502. After forming the dielectric film 702, a photoresist film (not shown) that covers the pixel region 501 and exposes the peripheral region 502 is formed by photolithography, and then the dielectric film of the peripheral region 502 is formed using this photoresist film as a mask. The film 702 is etched. As a result, the dielectric film 702 is selectively left in the pixel region 501. Next, the photoresist film (not shown) used for the mask is removed by, for example, ashing.

A metal silicide film 432 is selectively formed on the surface portions of the gate electrodes 607 and 608 and the N-type semiconductor region 426 of the peripheral region 502 where silicon is exposed by a salicide (Self-ALIgned siliCIDE) process. Specifically, for example, a metal film of cobalt or the like is deposited and heat-treated to silicify silicon in a portion in contact with the metal film, and then the unreacted metal film is removed. As a result, the metal silicide film 432 is locally formed.

Next, as shown in FIG. 10A, a dielectric film (first dielectric film) 703 is formed on the entire surface by, eg, sputtering or CVD. After forming a photoresist film (not shown) that covers the peripheral region 502 and exposes the pixel region 501 by photolithography, the dielectric film 703 in the pixel region 501 is etched back using this photoresist film as a mask. As a result, the dielectric film 703 is left in the peripheral region 502, and side wall spacers (first dielectric film 703) are formed on the side surfaces of the gate electrodes 602 to 605 in the pixel region 501 covered with the dielectric films 701 and 702. 1 side wall spacer) 703a is formed. Next, the photoresist film (not shown) used for the mask is removed by, for example, ashing.

Next, as shown in FIG. 10B, a second dielectric film such as a silicon oxide film is formed on the entire surface by, eg, CVD method, and then the dielectric film is etched back. .. Thus, sidewall spacers (second sidewall spacers) 704 are formed on the side surfaces of the gate electrodes 602 to 605 covered with the dielectric films 701 and 702 and the sidewall spacers 703a. Further, sidewall spacers 704 are formed on the side surfaces of the gate electrodes 607 and 608 covered with the sidewall spacers 701a and the dielectric film 703. At this time, the dielectric films 701 and 703 may be silicon nitride films to use the dielectric films 701 and 703 as etching stopper films.

At this time, depending on the thickness of the film covering the side surfaces of the gate electrodes 602 to 608 and the distance between the gate electrodes 602 to 608, a narrow gap is generated or not generated between the sidewall spacers 704. For example, when the thickness of the film covering the side surfaces of the gate electrodes 602 to 608 is 0.2 μm, when the distance between the gate electrodes 602 to 608 is smaller than 0.3 μm, a narrow gap is formed between the sidewall spacers 704. appear. Such a narrow gap may occur, for example, between a pair of adjacent gate electrodes and in a place where it is not necessary to provide a contact portion in the impurity region between these gate electrodes. For example, in FIG. 10B, a narrow gap is generated between the first gate electrode 604 and the second gate electrode 605 and between the first gate electrode 607 and the second gate electrode 608. There is. Here, if the light shielding member 308 is directly formed in the narrow gap and is to be removed by etching, the residue of the light shielding member 308 may be generated as described above. As will be described later, according to the present embodiment, by forming voids in the narrow gap, it is possible to prevent the generation of etching residues. Note that no contact portion is provided in the impurity region between the first gate electrode 604 and the second gate electrode 605, as shown in FIG. On the other hand, such a narrow gap does not occur in a portion where the gap between the gate electrodes 602 to 608 is larger than 0.4 μm.

Next, as shown in FIG. 11, an insulator film 301 such as a silicon oxide film is formed by using, for example, a plasma CVD method or the like. At this time, the insulator film 301 is embedded in the gap between the first gate electrode 604 and the second gate electrode 605 and the gap between the first gate electrode 607 and the second gate electrode 608. The voids 801 and 802 are formed so as not to exist. By forming the insulator film 301 so that the voids 801 and 802 are left, depressions in regions between the gate electrodes 604 and 605 and between the gate electrodes 607 and 608 are reduced.

Specific film forming conditions, be formed by a TEOS-O2 system and _SiH 4 -O parallel plate plasma CVD method small CVD method anisotropy and fluidity like using ₂ based gas species Is preferred. This is because as the film formation speed increases, voids 801 that are voids are easily formed between the gate electrode 604, the gate electrode 605, and the insulator film 301, while a gap that is sufficiently narrower than the void 801 is closed. This is because the depression of the film on the void can be reduced.

In this example, the gas flow rate was TEOS: 265 sccm, O ₂ : 2.5 sccm, and the pressure was 360 Pa. Further, a plasma CVD oxide film equivalent to 500 Å was formed by setting RF output to the upper electrode 720W and the lower electrode 320W and forming the film for 4 seconds.

Next, a light shielding member 308 made of tungsten, tungsten silicide, or the like is formed on the insulator film 301 by using a sputtering method, a CVD method, or the like. Further, the light blocking member 308 is patterned into a predetermined shape by using photolithography and dry etching.

By patterning, the light-shielding member 308 on the charge holding portion 403, the gate electrode 601 of the transfer transistor, and the gate electrode 602 of the second transfer transistor 612 remains, and the other portions are removed by etching. At this time, the flatness of the surface of the insulator film 301 on the region between the gate electrodes 604 and 605 and the region between the gate electrodes 607 and 608 is improved as in the first and second embodiments, and this portion has a light blocking member. It is possible to prevent the etching residue of 308 from being generated.

Further, by stacking the sidewall spacers 703a and 704 on the side surface of the gate electrode 602, the step difference of the gate electrode 602 can be reduced. This improves the coverage of the light blocking member 308 and improves the light blocking performance. Further, a void 801 is formed between the first gate electrode 604 of the amplification transistor M4 and the second gate electrode 605 of the selection transistor M5. The void 801 which is a void has a lower dielectric constant than the dielectric films 703 and 704 made of silicon oxide, silicon nitride, or the like. Therefore, the parasitic capacitance between the gate electrodes 604 and 605 can be reduced as compared with the case where the dielectric films 703 and 704 are embedded between the gate electrodes 604 and 605. By reducing the parasitic capacitance of the gate electrode 604 of the amplification transistor M4, it is possible to suppress a decrease in amplification efficiency of the amplification circuit.

Similar to the first and second embodiments, the insulator film 301 also functions as an etch stopper film when etching the light shielding member. In the Z-axis direction (first direction), the thickness of the insulator film 301 is t, the thickness of the light shielding member 308 is d _1, and the ratio of the overetch time to the main etching time during etching of the light shielding member is a. Let b be the etching selection ratio of the insulator film 301 with respect to the light-shielding member when the member is etched. At this time, the thickness of the insulator film etched at the time of etching the light shielding member is a×b×d ₁ .

When the film thickness t of the insulator film 301 is smaller than a×b×d ₁ , the surface of the dielectric film 703 is exposed at the time of etching the light blocking member in the pixel region. When the dielectric film 703 is used as an antireflection film for a photodiode, the optical characteristics of the photodiode may change if the dielectric film 703 is etched and its thickness changes. Therefore, it is preferable that the thickness t of the insulator film 301 is a×b×d ₁ or more.

When the dielectric film 703 is not used as the antireflection film of the photodiode, if the sum of the film thickness t of the insulator film 301 and the film thickness t′ of the dielectric film 703 is smaller than a×b×d _1. Good.

Since contact between the light shielding member 308 and the wiring may cause leakage or the like, the film thickness t of the insulator film 301 is preferably such that the light shielding member does not contact the wiring. When the gate electrodes 607 to 608 in the pixel region have different film thicknesses, the sum of the film thickness of the larger gate electrode and the film thickness of the dielectric film 703 is d ₂ , which is the distance between the semiconductor substrate 100 and the wiring. When the minimum distance (film thickness of the interlayer insulating film) is d ₃ and the thickness of the gate insulating film 103 is d ₄ , the film thickness t of the insulator film 301 is calculated from d ₃ −(d ₁ +d ₂ +d ₄ ). It is preferably thin.

From the viewpoint of light shielding property, the thicker the insulating film 301 is, the wider the distance between the light shielding member 308 and the semiconductor substrate 100 is, and the light shielding performance is deteriorated. Is preferred.

A specific example will be described below. When tungsten is used for the light blocking member 308, the film thickness d ₁ is preferably 0.1 μm or more in order to obtain sufficient light blocking ability. The transmittance of tungsten is 0.2% or less at a thickness of 0.1 μm or more, and a sufficient light-shielding ability can be achieved.

When the ratio a of the over-etching time to the main etching time at the time of etching the light blocking member is 0.1 and the etching selection ratio b of the insulating film 301 to the light blocking member 308 is 0.1, the film thickness t of the insulating film 301. Needs to be at least 1 nm or more. In reality, it is necessary to consider manufacturing variations and the like, so that the thickness of the insulator film 301 is preferably 5 nm or more.

Further, the thickness d _{2 of the} gate electrode is 0.2 μm, the smallest distance (thickness of the interlayer insulating film) d ₃ of the distance between the substrate and the wiring is 0.6 μm, and the thickness of the gate insulating film 103 is 8. When the thickness is 0 nm, it is preferable that the thickness t of the insulator film 301 is at least smaller than 0.3 μm so as not to contact the wiring. Actually, it is necessary to consider the manufacturing variation in the interlayer insulating film thickness, the film thickness of the light shielding member 308, and the deterioration of the light shielding performance due to the increase of the film thickness t of the insulator film 301. Therefore, the actual film thickness of the insulator film 301. It is preferable that t is smaller than 0.1 μm.
Therefore, the thickness of the insulator film 301 is preferably 1 nm or more and less than 0.3 μm, more preferably 5 nm or more and less than 0.1 μm.

As described above, according to this embodiment, it is possible to reduce the depressions on the surface of the insulator film formed between the gate electrodes, and improve the flatness of the base of the structure formed on this region. be able to. In particular, when the conductive film formed on the region between the gate electrodes is removed by etching, it is possible to suppress the residue of the conductive film in the recess of the insulating film and improve the manufacturing yield. Further, by forming the sidewall spacer on the side surface of the gate electrode, the light shielding performance can be improved.

In this embodiment, as an example of the condition that a narrow gap is generated between the sidewall spacers, the case where the gap between the gate electrodes is narrower than 0.3 μm is illustrated, but the gap between the gate electrodes where the narrow gap is generated is not always 0. It is not limited to the case of narrower than 0.3 μm. If the thickness of the insulator film deposited on the side surface of the gate electrode or the width of the sidewall spacers changes, the width of the gap between the sidewall spacers changes accordingly. Therefore, while considering the size of the depression formed on the insulator film, the portion where the insulator film is formed so that the voids remain remains in consideration of the design rules and process conditions required for each solid-state imaging device. It is preferable to set it appropriately.

In this embodiment, the gate electrodes 601 to 605 in the pixel region 501 are covered with the dielectric films 701 and 702, the sidewall spacers 703a and 704, and the insulating film 301. However, the structure of the insulating film/dielectric film covering the gate electrodes 601 to 605 is not limited to this. For example, the number of sidewall spacers to be stacked may be appropriately increased or decreased depending on the degree of relaxation of the step difference by the sidewall spacers 703a and 704. Alternatively, either of the dielectric films 701 and 702 may not be formed. The same applies to the peripheral region 502.

Furthermore, in the present embodiment, an example is shown in which voids are formed between the gate electrodes of the amplification transistor M4 and the selection transistor M5 in the pixel region 501, but voids are also formed between the gate electrodes of the other transistors M1 to M4 and M6. May be formed.

(Fourth Embodiment)
An imaging system according to the fourth embodiment of the present invention will be described. Imaging systems include digital still cameras, digital camcorders, copiers, facsimiles, mobile phones, in-vehicle cameras, observation satellites, and the like. FIG. 12 shows a block diagram of a digital still camera as an example of the imaging system according to the fourth embodiment.

In FIG. 12, the imaging system includes a barrier 1001 for protecting the lens, a lens 1002 for forming an optical image of a subject on the solid-state imaging device 1004, a diaphragm 1003 for changing the amount of light passing through the lens 1002, and a mechanical shutter 1005. Equipped with. The imaging system further includes the solid-state imaging device 1004 described in the first to third embodiments, and the solid-state imaging device 1004 converts the optical image formed by the lens 1002 as image data. Here, it is assumed that an AD conversion unit is formed on the semiconductor substrate of the solid-state imaging device 1004. The imaging system further includes a signal processing unit 1007, a timing generation unit 1008, an overall control/arithmetic unit 1009, a memory unit 1010, a recording medium control I/F unit 1011, a recording medium 1012, and an external I/F unit 1013. The signal processing unit 1007 performs various corrections and compresses the imaged data output from the solid-state imaging device 1004. The timing generator 1008 outputs various timing signals to the solid-state imaging device 1004 and the signal processor 1007. The overall control/arithmetic unit 1009 controls the entire digital still camera, and the memory unit 1010 functions as a frame memory for temporarily storing image data. The recording medium control I/F unit 1011 performs recording or reading on a recording medium. The recording medium 1012 is composed of a detachable semiconductor memory or the like, and records or reads imaging data. The external I/F unit 1013 is an interface for communicating with an external computer or the like. Here, the timing signal and the like may be input from the outside of the imaging system, and if the imaging system has at least the solid-state imaging device 1004 and the signal processing unit 1007 that processes the imaging signal output from the solid-state imaging device 1004. Good.

(Other embodiments)
The above-described embodiment merely shows specific examples for carrying out the present invention, and the technical scope of the present invention is not limitedly interpreted by these. That is, the present invention can be implemented in various forms without departing from the technical idea thereof. For example, the present invention can be widely applied not only to the space between the gate electrodes of the transistors but also to a circuit configuration in which an etching residue of the light shielding member may occur, such as a fine space between wiring patterns. Further, in the above-described embodiment, the solid-state imaging device having signal charges as electrons has been described as an example, but the present invention can be similarly applied to a solid-state imaging device having signal charges as holes. In this case, the conductivity type of the semiconductor region described above is opposite between the P type and the N type. The planar layout of the pixel circuit of the solid-state imaging device shown in FIG. 6 is an example, and the planar layout of the pixel circuit of the solid-state imaging device to which the present invention is applicable is not limited to this. Absent. Furthermore, the configuration of the readout unit of the pixel circuit is not limited to the example shown in FIG.

In addition, in the third embodiment, the present invention has been described by taking the CMOS image sensor having the global electronic shutter function as an example, but the solid-state imaging device to which the present invention can be applied is not limited to the CMOS image sensor. For example, the present invention can be applied to a CCD image sensor. In the CCD image sensor, a light shielding member is arranged on the reading unit for reading and transferring charges generated by photoelectric conversion in the photoelectric conversion unit. The same structure and manufacturing method as those of the above-described embodiments can be applied to the underlying structure and manufacturing method on which the light shielding member is deposited. In the present specification, the “charge holding unit” also means the above-mentioned reading unit when the solid-state imaging device is a CCD image sensor.

100 semiconductor substrate 101 well 102 element isolation region 103 gate insulating films 201, 202, 601 to 608 gate electrodes 203, 204, 205 impurity regions 301 insulator films 303, 701 to 703 dielectric films 302, 801, 802 voids 304 to 307 , 701a, 703a, 704 Side wall spacer 308 Light blocking members 421 to 425 N type impurity region 432 P type impurity region

Claims (26)

A method for manufacturing a solid-state imaging device, comprising:
A first gate electrode of a first transistor and a second gate electrode adjacent to the first gate electrode on a substrate having a first region, a second region, a third region and a fourth region. A second gate electrode of said transistor, said first gate electrode being located above said first region, said second gate electrode being located above said second region, said first gate electrode being located above said first region. Forming a gap between the gate electrode and the second gate electrode above the fourth region,
Forming an insulator film covering the fourth region, the first gate electrode and the second gate electrode;
Forming a film of a light-shielding material on the insulator film, the film covering the third region and the fourth region;
Of the film made of the light-shielding material located above the void with the insulator film interposed therebetween, at least a part of the film located above the fourth region is removed by etching, and the light-shielding material is formed. Forming a light blocking member on the third region from a film made of
Forming an insulating film covering the light shielding member, the first gate electrode and the second gate electrode;
Forming a contact plug penetrating the insulating film to connect to either the first transistor or the second transistor;
A step of forming a wiring connected to the contact plug on the insulating film,
Have
A method of manufacturing a solid-state imaging device, wherein a void exists between the insulator film and the fourth region in the step of forming a film made of the light-shielding material. The ratio of the etching time of the insulating film to the etching time of the film of the light-shielding material is a, the etching selection ratio of the film of the light-shielding material to be the light-shielding member and the insulating film is b, When the thickness of the insulator film is t and the thickness of the light shielding member is d ₁ ,
The method for manufacturing a solid-state imaging device according to claim 1, wherein the insulating film is formed so as to satisfy a×b×d ₁ ≦t. The fourth region includes an impurity region shared by the first transistor and the second transistor, and in the step of forming the contact plug, the contact plug is not formed on the impurity region. Alternatively, the method for manufacturing the solid-state imaging device according to the item 2. The solid-state imaging device includes a peripheral circuit,
The method for manufacturing a solid-state imaging device according to claim 1, wherein the first transistor and the second transistor form the peripheral circuit. The solid-state imaging device includes a pixel region having a plurality of pixel circuits,
The pixel circuit is
A first transfer transistor for transferring charges from the photoelectric conversion unit to the charge holding unit;
A second transfer transistor that transfers the charge from the charge holding unit to the charge-voltage conversion unit;
An amplification transistor that outputs a signal according to the potential of the charge-voltage converter,
Have
The method of manufacturing a solid-state imaging device according to claim 1, further comprising the charge holding portion, wherein the charge holding portion is covered with the light shielding member. The method for manufacturing a solid-state imaging device according to claim 5, wherein the light blocking member covers the gate electrode of the first transfer transistor and the gate electrode of the second transfer transistor. Between the step of forming the first gate electrode and the second gate electrode and the step of forming the insulator film,
Forming a dielectric film covering the first gate electrode and the second gate electrode;
Forming sidewall spacers on side surfaces of the first gate electrode and the second gate electrode by etching back the dielectric film;
The method for manufacturing a solid-state imaging device according to claim 1, further comprising: Between the step of forming the first gate electrode and the second gate electrode and the step of forming the insulator film,
Forming a first dielectric film covering the first gate electrode and the second gate electrode;
Forming a first sidewall spacer on a side surface of the first gate electrode and the second gate electrode by etching the first dielectric film;
Forming a second dielectric film covering the first sidewall spacers;
Forming a second sidewall spacer on the first sidewall spacer by etching the second dielectric film;
The method for manufacturing a solid-state imaging device according to claim 1, further comprising: Between the step of forming the first sidewall spacer and the step of forming the second dielectric film, the first sidewall spacer, the first gate electrode, and the second gate electrode are covered. 3 further has a step of forming a dielectric film,
In the step of forming the insulator film, between the first sidewall spacer and the second sidewall spacer, between the insulator film and an upper surface of the first gate electrode, and the insulator. The method for manufacturing a solid-state imaging device according to claim 8, wherein the third dielectric film is located between a film and an upper surface of the second gate electrode. A substrate having a first region, a second region, a third region and a fourth region,
A first gate electrode of a first transistor overlying the first region;
A second gate electrode of a second transistor located on the second region and adjacent to the first gate electrode;
An insulating film covering the third region, the fourth region, the first gate electrode and the second gate electrode,
An insulator film which is disposed between the insulating film and the substrate and covers the third region, the fourth region, the first gate electrode and the second gate electrode;
A light blocking member provided between the insulating film and the third region;
A wiring provided on the insulating film,
A portion of the insulating film covering the third region is located between the light blocking member and the third region,
Between the gap of the first gate electrode and the second gate electrode is located on the fourth region, said fourth region covering part and the fourth region of said insulator layer A solid-state imaging device in which a void exists. A part of the insulator disposed between the insulating film and the substrate is located in the gap between the first gate electrode and the second gate electrode, and the void is the one of the insulator. The solid-state imaging device according to claim 10, wherein the solid-state imaging device is located between the portion and the insulating film. The solid-state imaging device according to claim 11, wherein the insulator includes a sidewall spacer provided between the first gate electrode and the second gate electrode. The solid-state imaging device according to claim 12, wherein the insulator further includes a portion located between the sidewall spacer and the void. The solid-state imaging device according to claim 12, wherein the sidewall spacer is made of silicon nitride, and a silicon nitride film is located between the third region and the light shielding member. The insulator includes a first portion located on an upper surface of the first gate electrode and a second portion located on an upper surface of the second gate electrode, wherein the void is 15. The solid-state imaging device according to claim 11, wherein the solid-state imaging device is located between the first portion and the second portion. 16. The silicon nitride film is provided between the third region and the light shielding member, and the silicon oxide film is provided between the silicon nitride film and the light shielding member. 2. The solid-state imaging device according to item 1. The solid-state imaging device according to claim 10, wherein the insulator film is in contact with the void . 18. The solid-state imaging device according to claim 10, wherein a member made of the same material as the light shielding member does not exist between the void and the insulating film. The solid-state imaging device according to any one of claims 10 to 18, wherein a material of the light shielding member is tungsten or tungsten silicide. A pixel region having a plurality of pixel circuits; and a peripheral region located around the pixel region and provided with peripheral circuits, wherein the third region is located in the pixel region and the fourth region The solid-state imaging device according to claim 10, wherein is located in the peripheral region. The first transistor and the second transistor share an impurity region,
20. The solid-state imaging device according to claim 10, wherein the void exists on the impurity region. The pixel circuit is
A first transfer transistor for transferring charges of the photoelectric conversion unit to the charge holding unit;
A second transfer transistor for transferring the charge of the charge holding unit to the charge-voltage conversion unit;
A third transistor having a gate electrode connected to the charge-voltage converter,
Including
21. The solid-state imaging device according to claim 20, wherein the gate electrode of the first transfer transistor, the light shielding member covers the charge holding unit and the gate electrode of the second transfer transistor. 23. The solid-state imaging device according to claim 10, wherein a distance between the first gate electrode and the second gate electrode is larger than 0.1 μm and smaller than 0.3 μm. A solid-state imaging device according to any one of claims 10 to 23,
A signal processing unit that processes a signal output by the solid-state imaging device;
Imaging system having. A CMOS image sensor having a global electronic shutter function,
A signal processing unit for processing a signal output from the CMOS image sensor;
An imaging system having:
The CMOS image sensor is
A substrate having a first region, a second region, a third region and a fourth region,
A first gate electrode of a first transistor overlying the first region;
A second gate electrode of a second transistor located on the second region and adjacent to the first gate electrode;
An insulating film covering the third region, the fourth region, the first gate electrode and the second gate electrode,
An insulator film covering the third region, the fourth region, the first gate electrode and the second gate electrode;
A light blocking member provided between the insulating film and the third region,
A portion of the insulator film, which is disposed between the insulating film and the substrate and covers the third region, is located between the light shielding member and the third region,
Said first gap between the gate electrode and the second gate electrode is located on the fourth region, said fourth region and said fourth region covering part of said insulator layer An imaging system in which there are voids between. The imaging system according to claim 25, wherein the CMOS image sensor includes a pixel circuit and a peripheral circuit, and the first transistor and the second transistor are included in the peripheral circuit.

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