JP2016219792A - Solid-state imaging apparatus, method for manufacturing solid-state imaging apparatus, and imaging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of improving a yield, while maintaining light-shielding performance by a light-shielding member, a method for manufacturing the solid-state imaging apparatus, and an imaging system.SOLUTION: The method for manufacturing the solid-state imaging apparatus according to one embodiment includes the steps of: forming a gate electrode of a first transistor and a gate electrode of a second transistor adjacent to the first transistor on a substrate; forming an insulator film covering the gate electrode of the first transistor and the gate electrode of the second transistor, so as to form a void between the gate electrode of the first transistor and the gate electrode of the second transistor; forming a film on the insulator film; and forming a light-shielding member by removing a part of the film by etching.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an imaging system.

  In a solid-state imaging device such as a CMOS image sensor or a CCD image sensor, a light shielding member is provided to prevent light from entering a portion other than a photoelectric conversion unit that performs photoelectric conversion. For example, a CMOS image sensor having a global electronic shutter (all pixel simultaneous exposure) function has a charge holding unit that holds charges transferred from a photoelectric conversion unit. When light enters the charge holding portion and photoelectric conversion occurs, the photoelectrically converted charge becomes noise, which may deteriorate image quality. For this reason, the charge holding portion is covered with a light shielding member to prevent light from entering. Also in the CCD image sensor, as in the case of the CMOS image sensor, when light enters the readout section, it causes noise, so the readout section is covered with a light shielding member.

  In a solid-state imaging device having a light shielding member, since an optically transparent interlayer insulating film exists between the substrate and the light shielding member, the light shielding performance is improved by preventing light entering through this interlayer insulating film. It is illustrated. In Patent Document 1, the thickness of the insulating film is reduced by etching the insulating film disposed under the light shielding member. By thinning the insulating film under the light shielding member and reducing the distance between the photoelectric conversion portion and the lower surface of the light shielding member, leakage of light to the charge holding portion is suppressed and the light shielding performance is improved.

JP 2012-248861 A

  When the gap between the gate electrodes has a certain size, when an insulating film is formed on adjacent gate electrodes and a light shielding film is formed, there is a portion where the insulating film is sufficiently flat between the gate electrodes. Therefore, even if the light shielding film is etched, a residue is hardly generated. On the other hand, the gap between the gate electrodes becomes narrow due to miniaturization of the semiconductor process. When a light-shielding film serving as a light-shielding member is formed on the narrow interval and the light-shielding film is etched, a light-shielding film residue may exist inside the narrow interval. Such residues can cause leaks. In Patent Document 1, an insulating film is formed under a light-shielding film so as to bury recesses between gate electrodes and between wirings to reduce the level difference. Thereby, generation | occurrence | production of the etching residue of a light shielding film can be reduced. However, in Patent Document 1, although it is possible to bury recesses that are narrower than a certain interval, it is not possible to embed recesses that are equal to or greater than the interval evenly, and a narrow gap remains, and a light shielding member remains in this gap. was there. Even if the insulating film to be embedded is made thick, a gap is generated depending on the interval between the recesses, and the generation of the residue cannot be completely prevented.

  Further, when the flatness of the surface of the insulating film is impaired due to the level difference of the gate electrode, the flatness of the light shielding member and the structure formed thereon is also deteriorated, and the yield may be lowered. An object of the present invention is to provide a solid-state imaging device, a manufacturing method of the solid-state imaging device, and an imaging system that can improve the yield while maintaining the light shielding performance by the light shielding member.

  A method of manufacturing a solid-state imaging device according to an embodiment of the present invention includes a first gate electrode of a first transistor and a second gate electrode of a second transistor adjacent to the first transistor on a substrate. And forming an insulator film covering the first gate electrode and the second gate electrode so that a void is formed between the first gate electrode and the second gate electrode. A step of forming a film; a step of forming a film on the insulator film; and removing a part of the film located on the void across the insulating film by etching to form a light shielding member Forming.

In a method for manufacturing a solid-state imaging device according to another embodiment of the present invention, a direction in which the first gate electrode, the insulator film, and the film to be the light shielding member are stacked on the substrate is defined as a first direction. The ratio of the etching time of the insulator film to the etching time of the film to be the light shielding member is a, the etching selectivity ratio of the insulator film to the film to be the light shielding member is b, and the first of the insulator film is When the film thickness in the direction 1 is t and the film thickness in the first direction of the light shielding member is d ₁ , the insulator film is formed to satisfy the following formula.

  A solid-state imaging device according to another embodiment of the present invention includes a first transistor having a first gate electrode, and a second transistor having a second gate electrode adjacent to the first gate electrode in plan view. A pixel circuit comprising: a transistor; and an insulating film covering the first gate electrode and the second gate electrode; and a light shielding member provided on the insulating film; A void exists in a region surrounded by the electrode, the second gate electrode, and the insulator film, and the light shielding member is opposed to the void with the insulating film interposed therebetween in a direction perpendicular to the plan view. Not in position.

  According to the present invention, it is possible to improve the yield while maintaining the light shielding performance of the solid-state imaging device.

1 is a block diagram of a solid-state imaging device according to a first embodiment of the present invention. It is a schematic sectional drawing which shows the structure of the solid-state imaging device by 1st Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the solid-state imaging device by 1st Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the solid-state imaging device by 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the solid-state imaging device by 2nd Embodiment of this invention. It is a block diagram of the solid-state imaging device by a 3rd embodiment of the present invention. It is a top view which shows the structure of the solid-state imaging device by 3rd Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the solid-state imaging device by 3rd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the solid-state imaging device by 3rd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the solid-state imaging device by 3rd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the solid-state imaging device by 3rd Embodiment of this invention. It is a block diagram of the imaging system by 4th Embodiment of this invention.

(First embodiment)
A solid-state imaging device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a solid-state imaging device according to this embodiment. The solid-state imaging device includes a pixel region 10 having a plurality of pixel circuits 1 arranged in a matrix, and a peripheral region 20 located around the pixel region and provided with peripheral circuits. The pixel circuit 1 includes a photoelectric conversion unit that performs photoelectric conversion and a reading unit for reading out electric charges. The reading unit includes a transfer transistor that transfers charge, a transistor that resets the charge-voltage conversion unit, an amplification transistor that outputs a signal corresponding to the potential of the charge-voltage conversion unit, and a transistor for selecting the amplification transistor. The reading unit may include a charge holding unit that holds charges from the photoelectric conversion unit. In the circuit part other than the photoelectric conversion part, for example, the charge holding part, incident light is blocked by the light shielding member. In addition, the pixel region 10 is provided with a color filter for controlling spectral sensitivity characteristics and a microlens for condensing light on the photoelectric conversion units, and light shielding for preventing color mixture between the photoelectric conversion units. A member may be formed. Further, the pixel region 10 may include pixels that do not output an image, such as an optical black pixel in which the photoelectric conversion unit is shielded from light and a dummy pixel that does not have the photoelectric conversion unit, in addition to effective pixels.

  The peripheral area 20 includes a vertical scanning circuit 21, a column amplifier circuit 22, a horizontal scanning circuit 23, and an output unit 24. The vertical scanning circuit 21 supplies a control signal for controlling the transistor of the pixel circuit 1 to be on (conductive state) or off (non-conductive state). The vertical signal line 11 is provided in each column of the pixel circuit 1 and reads a signal from the pixel circuit 1 for each column. The column amplifier circuit 22 includes a differential amplifier circuit and a sample / hold circuit, and amplifies the pixel signal output to the vertical signal line 11. The horizontal scanning circuit 23 supplies a switch connected to the amplifier of each column and a control signal for controlling the switch on or off. The output unit 24 includes a buffer amplifier, a differential amplifier, and the like, and outputs the pixel signal from the column amplifier circuit 22 to a signal processing unit outside the solid-state imaging device. The output pixel signal is subjected to processing such as analog / digital conversion and correction of input data by a signal processing unit. Note that the solid-state imaging device may be a so-called digital sensor having an analog / digital conversion function.

  FIG. 2 is a schematic cross-sectional view of the solid-state imaging device according to the present embodiment. Here, two arbitrary first transistors 206 and second transistors 207 that are adjacent in plan view are shown. In one example, the transistors 206 and 207 are transistors constituting the pixel circuit 1. Two adjacent transistors 206 and 207 have a pair of adjacent gate electrodes 201 and 202, and a void 302 exists between the gate electrodes 201 and 202. As described above, the transistor having a pair of gate electrodes in which the void 302 is present may be either the transistor of the pixel circuit 1 or the peripheral circuit.

  The semiconductor substrate 100 has a surface parallel to an XY plane including the X-axis direction and the Y-axis direction. The semiconductor substrate 100 has a first conductivity type having a predetermined thickness in the Z-axis direction (first direction). A (for example, P-type) well 101 is provided. An element isolation region 102 that defines an active region is provided on the surface portion of the semiconductor substrate 100 in which the well 101 is formed. In the active region defined by the element isolation region 102, impurity regions 203, 204, and 205 having a conductivity type opposite to that of the well 101 (for example, N type) are provided apart from each other.

  A gate electrode 201 is provided over the semiconductor region (channel region) between the impurity region 203 and the impurity region 204 with the gate insulating film 103 interposed therebetween. As a result, a transistor 206 having impurity regions 203 and 204 constituting source / drain regions and a gate electrode 201 is formed. Here, the source / drain region means a semiconductor region that can function as at least one of a source and a drain of a transistor. Depending on the driving method of a transistor, the same semiconductor region may function as a source or a drain, or the same semiconductor region may function as a source of one transistor and function as a drain of another transistor. There is also. Similarly, the gate electrode 202 is provided over the semiconductor region (channel region) between the impurity region 204 and the impurity region 205 with the gate insulating film 103 interposed therebetween. Thus, a transistor 207 having impurity regions 204 and 205 constituting the source / drain regions and the gate electrode 202 is formed. These two transistors 206 and 207 share one source / drain region (impurity region 204). The distance between the gate electrodes 201 and 202 of the two transistors 206 and 207 is narrowed to about 1.0 μm or less, for example. Typically, the distance between the gate electrode 201 and the gate electrode 202 is smaller than the sum of the thicknesses of the gate electrode 201 and the gate electrode 202 and is 0.5 μm or less. The distance between the gate electrode 201 and the gate electrode 202 may be 0.1 μm or more.

  Note that the thickness and thickness of the members referred to here refer to the length in the Z-axis direction (first direction) perpendicular to the plan view of the semiconductor substrate 100. The direction in which layers such as a gate electrode, an insulating film, and a light shielding member, which will be described later, are stacked on the semiconductor substrate 100 can be defined as the Z-axis direction. In the following description, unless otherwise specified, the thickness and thickness of the member refer to the length in the Z-axis direction.

  An insulator film 301 is provided over the semiconductor substrate 100 over which the transistors 206 and 207 are provided. The insulator film 301 is not completely buried in the gap between the gate electrode 201 and the gate electrode 202, and at least a part of the region between the gate electrode 201 and the gate electrode 202 has a void (vacancy) 302. Is formed. By forming the void 302 in at least part of the region between the gate electrode 201 and the gate electrode 202, the planarity of the surface of the insulator film 301 over this region can be improved. That is, the influence of the base step formed by the gate electrode 201 and the gate electrode 202 is reduced in the surface portion of the insulator film 301 in the region between the gate electrode 201 and the gate electrode 202. A light shielding member 308 made of a light shielding material such as tungsten or tungsten silicide is provided in a partial region on the insulator film 301. By forming the void 302, the surface of the insulator film 301 can be flattened, and it is possible to avoid the generation of a residue when the light shielding film is etched on the insulator film 301 to form the light shielding member 308. it can.

  An interlayer insulating film 310 is disposed on the insulating film 301. Contact holes penetrating the interlayer insulating film 310 and the insulator film 301 are formed, and contact plugs 311a to 311c are provided in the contact holes. The contact plug 311 a is connected to the gate electrode 201, and the contact plug 311 b is connected to the gate electrode 202. The contact plug 311c is connected to the source / drain region (impurity region 205). Contact plugs 311a-c are connected to wirings 312a-c.

  FIG. 3 is a process cross-sectional view illustrating the method of manufacturing the solid-state imaging device according to the first embodiment of the present invention. As shown in FIG. 3A, an element isolation region 102 that defines an active region is formed on the surface of a semiconductor substrate 100 by using, for example, an STI (Shallow Trench Isolation) method or a LOCOS (LOCal Oxidation of Silicon) method. Form. Next, the well 101 is formed in a predetermined region of the semiconductor substrate 100 by ion implantation.

  After the well 101 is formed, a gate insulating film 103 made of, for example, a silicon oxide film is formed on the surface of the active region of the semiconductor substrate 100 by using a thermal oxidation method, a CVD method, or the like. For example, a polysilicon film is deposited on the entire surface of the semiconductor substrate 100 on which the gate insulating film 103 is formed by, for example, a CVD method. The polysilicon film is patterned using photolithography and dry etching to form gate electrodes 201 and 202 made of the polysilicon film. Next, ion implantation is performed using the gate electrodes 201 and 202 as a mask to form impurity regions 203, 204, and 205 to be source / drain regions in the semiconductor substrate 100 in a self-aligned manner with respect to the gate electrodes 201 and 202. To do.

  In this manner, the transistor 206 having the impurity regions 203 and 204 and the gate electrode 201 and the transistor 207 having the impurity regions 204 and 205 and the gate electrode 202 are formed in the active region of the semiconductor substrate 100.

  Next, as shown in FIG. 3B, an insulator film 301 such as a silicon oxide film is deposited on the semiconductor substrate 100 on which the transistors 206 and 207 are formed. At this time, the insulator film 301 is formed so that the insulator film 301 is not completely buried in the gap between the gate electrode 201 and the gate electrode 202. As a result, a void 302 is formed in at least a part of the region between the gate electrode 201 and the gate electrode 202. Typically, in the film formation conditions of the insulating film, voids tend to remain in narrow gaps as the isotropic component increases and the film formation speed increases. In consideration of such points, the insulator film 301 is formed while leaving the void 302 by appropriately setting the film formation conditions of the insulator film 301 according to the interval and the film thickness of the gate electrodes 201 and 202. can do.

As specific film forming conditions, the film is formed by using a CVD method with low anisotropy and fluidity such as a parallel plate type plasma CVD method using a TEOS-O ₂ or SiH ₄ -O ₂ gas species. It is preferable. This is because the void formation 302 is easily formed between the gate electrode 201, the gate electrode 202, and the insulator film 301, while a gap sufficiently narrower than the void 302 is blocked by increasing the deposition rate. This is because the depression of the film on the void can be reduced.

In this example, the gas flow rates were TEOS: 265 sccm, O ₂ : 2.5 sccm, and the pressure was 360 Pa. In addition, a plasma CVD oxide film corresponding to 500 mm was formed with an RF output of an upper electrode 720W and a lower electrode 320W and a film formation time of 4 seconds.

  When the insulator film 301 is formed on the pattern arranged at a narrow interval such as the gate electrodes 201 and 202 so as to fill the interval, the surface portion of the insulator film 301 between the gate electrode 201 and the gate electrode 202 is formed. A fine depression is formed on the surface opposite to the surface in contact with the gate electrodes 201 and 202. If a film is deposited in the fine depression in a later step, it may not be completely removed when the film is etched thereafter, and may remain as a residue. In particular, if this film is a conductive film, this residue causes a short circuit between the wirings, causing a defect. By forming the insulator film 301 so as to leave the void 302 between the gate electrodes 201 and 202, as compared with the case where the insulator film 301 is formed so as to embed between the gate electrodes 201 and 202, the gate electrode 201, Indentations on the area between 202 can be reduced.

  Next, as shown in FIG. 3C, a light shielding film 309 made of, for example, tungsten, tungsten silicide, or the like is formed on the insulator film 301 by using a sputtering method, a CVD method, or the like. Further, after forming the light shielding film 309, the light shielding film 309 is patterned into a predetermined shape using photolithography and dry etching. As a result, a light shielding member 308 is formed from the light shielding film 309 as shown in FIG. In this patterning, a portion of the light shielding film 309 located on the photoelectric conversion unit can be removed. Further, a portion of the light shielding film 309 located on a contact portion to be formed later can be removed. In this example, a portion of the light shielding film 309 located on the impurity region 204 between the gate electrodes 201 and 202, that is, a portion located on the void 302 is removed. At this time, no depression is formed on the surface of the insulator film 301 so that the residue of the light shielding film 309 remains. That is, the flatness of the surface of the insulator film 301 over the region between the gate electrodes 201 and 202 can be improved, and etching residues of the light shielding film 309 can be avoided. Further, even when it is not necessary to remove the light shielding film 309 over the impurity region 204 between the gate electrodes 201 and 202, the flatness of the surface of the insulator film 301 is improved, so that the flatness of the light shielding member 308 is improved. The effect that it can be obtained.

  Moreover, according to this embodiment, the effect that the film thickness of the insulator film 301 can be made thin is also acquired. As another means for relaxing the step on the surface of the insulator film 301, it is conceivable to increase the thickness of the insulator film 301. However, when the thickness of the insulator film 301 is increased, the distance between the light shielding member 308 and the semiconductor substrate 100 is increased, and the light shielding performance is deteriorated. On the other hand, according to this embodiment, the film thickness of the insulating film can be reduced without causing a step on the surface of the insulating film 301. For example, the insulator film 301 can be made thinner than the gate electrodes 201 and 202. For this reason, the distance between the light shielding member 308 and the semiconductor substrate 100 can be shortened, and the light shielding performance can be improved.

  From the viewpoint of light shielding properties, the height of the lower surface of the light shielding member 308 that is not formed on the gate electrode 201 is preferably lower than the height of the upper surfaces of the gate electrodes 201 and 202. That is, the thickness of the insulator film 301 is desirably smaller than the total thickness of the gate insulating film 103 and the gate electrodes 201 and 202. Typically, since the thickness of the gate insulating film 103 is smaller than the thickness of the gate electrodes 201 and 202, the thickness of the insulator film 301 should be smaller than the thickness of the gate electrodes 201 and 202. It is enough.

  Thereafter, as shown in FIG. 2, an interlayer insulating film 310 covering the light shielding member 308 and the gate electrodes 201 and 202 of the plurality of transistors is formed. The interlayer insulating film 310 is planarized by an etch back method, a CMP method, a reflow method, or the like. Then, contact holes that penetrate the interlayer insulating film 310 and the insulator film 301 and reach the semiconductor substrate 100, the gate electrodes 201 and 202, or the light shielding member 308 are formed. Contact plugs 311a to 311c are formed by embedding a conductive material such as tungsten in the contact holes. The contact plugs 311a to 311c are connected to one of the plurality of transistors 206 and 207 through the interlayer insulating film 310 and the insulator film 301. On the other hand, no contact plug is formed on the impurity region 204, that is, on the void 302. When a contact hole is provided so as to penetrate the void 302, a conductive material may enter the void 302 when the contact plug is formed. However, if a contact hole is not provided on the void 302, such a situation can be avoided. When a contact plug needs to be connected to the impurity region 204, the contact plug is preferably formed at a position away from the void 302. The portions through which the contact plugs 311a-c pass are removed from the light shielding film 309, so that the contact plugs 311a-c are formed away from the light shielding member 308. A contact plug (not shown) connected to the light shielding member 308 may be further formed. Further, wirings 312 a to 312 c connected to the contact plugs 311 a to 311 c are formed on the interlayer insulating film 310.

  The insulator film 301 also functions as an etch stopper film when the light shielding member 308 is etched. If the thickness of the insulator film 301 is smaller than the thickness of the insulator film 301 that is etched by overetching when the light shielding member is etched, the surface of the semiconductor substrate 100 is exposed when the light shielding member 308 is etched, and the semiconductor substrate 100 is etched. Damage is added. This etching damage causes dark current and the like.

Here, in the Z-axis direction (first direction) in which the gate electrode 201, the insulator film 301, and the light shielding member 308 of the first transistor 206 are stacked, the thickness of the insulator film 301 is t, and the film of the light shielding member 308 the thickness and _{d 1.} Further, the ratio of the over etching time to the main etching time at the time of etching the light shielding member is a, and the selection ratio of the insulator film 301 to the light shielding member 308 at the time of etching the light shielding member is b. At this time, the thickness of the insulator film 301 etched during the light shielding member etching is a × b × d ₁ . Therefore, the film thickness t of the insulator film 301 is preferably a × b × d ₁ or more.

Further, when the light shielding member 308 and the wirings 312a to 3c are in contact with each other, it may cause leakage. In the Z-axis direction, the thicknesses of the gate electrodes 201 and 202 are d ₂ , the smallest distance among the distances from the wirings 312 a to 3c to the semiconductor substrate 100 is d ₃ , and the thickness of the gate insulating film 103 is d ₄ . At this time, the thickness t of the insulator film 301 is preferably thinner than d ₃ − (d ₁ + d ₂ + d ₄ ).

  From the viewpoint of light shielding properties, the greater the film thickness of the insulator film 301, the greater the distance between the light shielding member 308 and the semiconductor substrate 100 and the lower the light shielding performance. Good light shielding performance.

Specific examples are described below. When using a tungsten light shielding member 308, in order to obtain a sufficient light-shielding ability, it is preferable that the thickness d ₁ is 0.1μm or more. The transmittance of tungsten is 0.2% or less at a thickness of 0.1 μm or more, and a sufficient light shielding ability can be achieved.

  When the ratio a of the over etching time to the main etching time at the time of etching the light shielding member is 0.1 and the selection ratio b of the insulator film 301 to the light shielding member 308 is 0.1, the film thickness t of the insulator film 301 is It must be at least 1.0 nm or more. Actually, it is necessary to consider manufacturing variations and the like. Therefore, the insulator film thickness is preferably 5.0 nm or more.

Further, the thickness d ₁ of the light shielding member 308 is 0.1 μm, the thickness d _{2 of the} gate electrode is 0.2 μm, the distance d ₃ between the wirings 312 a to 3c and the semiconductor substrate 100 is 0.6 μm, and the film of the gate insulating film If a thickness _{d 4} of the 8.0 nm, it is preferable in order not to contact the wire is thinner than at least 0.3μm film thickness t of the insulating film 301. Actually, manufacturing variations of the interlayer insulating film and the light shielding member occur, and the light shielding performance decreases as the film thickness t of the insulator film 301 increases. Therefore, the film thickness t of the insulator film 301 should be 0.1 μm or less. Is preferred.
Therefore, the thickness of the insulator film 301 is preferably 1 nm or more and less than 0.3 μm, more preferably 5 nm or more and 0.1 μm or less.

  As described above, according to this embodiment, the depression of the surface of the insulator film formed between the gate electrodes can be reduced, and the flatness of the base of the structure formed on this region is improved. be able to. In particular, in the case where the conductive film formed on the region between the gate electrodes is removed by etching, it is possible to suppress the residue of the conductive film from remaining in the recess of the insulator film, thereby improving the manufacturing yield. Can be planned.

(Second Embodiment)
A solid-state imaging device and manufacturing method according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a schematic cross-sectional view illustrating the structure of the solid-state imaging device according to the present embodiment, and FIG. 5 is a process cross-sectional view illustrating the method for manufacturing the solid-state imaging device according to the present embodiment. Components similar to those of the solid-state imaging device according to the first embodiment shown in FIGS. 1 to 3 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  As shown in FIG. 4, the solid-state imaging device according to the present embodiment is shown in FIG. 2 except that sidewall spacers 304, 305, 306, and 307 are formed on the side surfaces of the gate electrodes 201 and 202. This is substantially the same as the solid-state imaging device according to the first embodiment. Since the side wall spacers 305 and 306 are formed on the opposite side surfaces of the gate electrodes 201 and 202, the void 302 is formed between the side wall spacers 305 and 306. Also in the present embodiment, the void 302 is formed without being embedded in the gap between the gate electrodes 201 and 202, thereby improving the flatness of the surface of the insulator film 301 on the void 302. Can do.

  Next, the method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIG. 5A, the well 101, the element isolation region 102, the first transistor 206, and the second transistor 207 are formed on the semiconductor substrate 100 in the same manner as in the method for manufacturing the solid-state imaging device according to the first embodiment. . A dielectric film 303 made of, for example, a silicon oxide film is formed on the entire surface by CVD or the like. Subsequently, as shown in FIG. 5B, the dielectric film 303 is etched back to form side wall spacers 304, 305, 306, and 307 on the side surfaces of the gate electrodes 201 and 202. Note that the dielectric film and the insulator film are merely named differently for convenience, and the material constituting the dielectric film and the material constituting the insulator film may be the same.

  Next, as shown in FIG. 5C, an insulator film such as a silicon oxide film is formed on the semiconductor substrate 100 on which the sidewall spacers 304, 305, 306, and 307 are formed by using a plasma CVD method or the like. 301 is deposited. At this time, the insulator film 301 is formed so that the insulator film 301 is not buried in the gap between the side wall spacers 305 and 306 between the gate electrodes 201 and 202. As a result, the void 302 remains in at least a part of the region between the gate electrode 201 and the gate electrode 202. By forming the insulator film 301 so as to form the void 302 between the gate electrodes 201 and 202, the depression formed on the region between the gate electrodes 201 and 202 can be reduced.

  Next, a light shielding film made of tungsten, tungsten silicide, or the like is formed on the insulator film 301 by sputtering, CVD, or the like. Further, the light shielding member 308 is formed by patterning the light shielding film into a predetermined shape using photolithography and dry etching. Here, a portion of the light shielding film located on the impurity region 204 between the gate electrodes 201 and 202 is removed. At this time, since no depression is generated on the surface of the insulator film 301 on the region between the gate electrodes 201 and 202, etching residues of the light shielding film can be suppressed.

  Further, by forming the side wall spacers 304, 305, 306, 307 on the side surfaces of the gate electrodes 201, 202, the step between the gate electrodes 201, 202 is gently inclined. Thereby, the coverage of the light shielding member 308 on the stepped portion, in particular, the sidewall spacer 304 is improved, and the light shielding performance can be improved. Further, as in the first embodiment, the thickness of the insulator film 301 is made thinner than the sum of the thickness of the gate electrodes 201 and 202 and the thickness of the gate insulating film 103, and the light shielding member 308. And the semiconductor substrate 100 can be shortened. Thereby, favorable light-shielding performance can be obtained.

As in the first embodiment, since the insulator film 301 is also an etch stopper film at the time of etching the light shielding member, the film thickness of the insulator film 301 is thicker than the thickness of the insulator film etched at the time of etching the light shielding member. Is preferred. Note that in the Z-axis direction (first direction) in which the gate electrode 201, the insulator film 301, and the light shielding member 308 of the first transistor 206 are stacked, the thickness of the insulator film 301 is t, and the thickness of the light shielding member 308 is Is d ₁ . Further, the ratio of the over-etching time to the main etching time during the light shielding member etching is a, and the etching selection ratio of the insulator film 301 to the light shielding member during the light shielding member etching is b. In that case, since the thickness of the insulator film 301 etched during the light shielding member etching is a × b × d ₁ , t is preferably a thickness of a × b × d ₁ or more.

Further, when the light shielding member 308 and the wiring are in contact with each other, it causes a leak or the like. When the thickness of the gate electrodes 201 and 202 is d ₂ , the smallest distance from the wirings 312 a to 3 c to the semiconductor substrate 100 is d ₃ , and the thickness of the gate insulating film 103 is d ₄ in the Z-axis direction. The film thickness t of the insulator film 301 is preferably thinner than d ₃ − (d ₁ + d ₂ + d ₄ ).
Note that the same method as that of the first embodiment can be used as a method of forming the insulator film 301.

  As described above, according to this embodiment, the depression of the surface of the insulator film formed between the gate electrodes can be reduced, and the flatness of the base of the structure formed on this region is improved. be able to. In particular, in the case where the conductive film formed on the region between the gate electrodes is removed by etching, it is possible to suppress the residue of the conductive film from remaining in the recess of the insulator film, thereby improving the manufacturing yield. Can be planned. Further, by forming a sidewall spacer on the side surface of the gate electrode, the light shielding performance can be improved.

(Third embodiment)
A solid-state imaging device and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a block diagram of the solid-state imaging device of the present embodiment. The solid-state imaging device includes a pixel region 501 including a plurality of pixel circuits 401 and a peripheral region 502 including peripheral circuits such as a vertical scanning circuit 530, a column amplifier circuit 531, and a horizontal scanning circuit 532. Although a pixel circuit 401 of 2 rows and 2 columns is shown in the pixel region 501 of FIG. 6, the number of pixels is not limited. The pixel circuit 401 includes a photoelectric conversion unit 402, a charge holding unit 403, a charge voltage conversion unit 404, a power supply unit 405, a pixel output unit 407, first and second transfer transistors M1, M2, a reset transistor M3, an amplification transistor M4, A selection transistor M5 and an overflow drain (hereinafter referred to as OFD) transistor M6 are provided. The photoelectric conversion unit 402 includes a microlens, a photodiode, and the like, and accumulates charges corresponding to incident light. The photoelectric conversion unit 402 is electrically connected to the OFD transistor M6 and the first transfer transistor M1. The transistor M6 discharges the electric charge of the photoelectric conversion unit 402 to the power supply unit 405 in accordance with the control signal OFD (n) supplied to the gate electrode.

  The first transfer transistor M1 transfers the charge from the photoelectric conversion unit 402 to the charge holding unit 403 according to the control signal TX1 (n) supplied to the gate electrode. The charge holding unit 403 holds the charge transferred via the transfer transistor M1. The second transfer transistor M2 transfers the charge held in the charge holding unit 403 to the charge / voltage conversion unit 404 in accordance with the control signal TX2 (n). The reset transistor M3 resets the voltage of the charge voltage conversion unit 404 to the voltage of the power supply unit 405 in response to the control signal RES (n). The amplification transistor M4 outputs a signal corresponding to the potential of the gate electrode to the signal line OUT (m). The selection transistor M5 is electrically connected between the power supply unit 405 and the amplification transistor M4, and supplies current to the amplification transistor M4 according to the signal SEL (n).

  The power supply unit 405 has the same node as the drain of the reset transistor M3, the drain of the selection transistor M5, and the drain of the OFD. The vertical scanning circuit 530 supplies control signals RES (n), TX1 (n), TX2 (n), SEL (n), and OFD (n) to the unit pixel circuit. The signal output from the signal line OUT is held in the column amplifier circuit 531 and subjected to processing such as amplification and addition. The horizontal scanning circuit 532 sequentially outputs the signals held in the column amplifier circuit 531 to the output terminal OUT.

  The operation of the global shutter in the solid-state imaging device according to the present embodiment will be described. After a certain accumulation period has elapsed, the charge generated in the photoelectric conversion unit 402 is transferred to the charge holding unit 403 via the transfer transistor M1. While the charge holding unit 403 holds the signal charge, the photoelectric conversion unit 402 starts to accumulate charges again. The charge in the charge holding unit 403 is transferred to the charge / voltage conversion unit 404 via the second transfer transistor M2, and is output as a signal from the pixel output unit 407, which is one terminal of the amplification transistor M4. Further, the OFD transistor M6 discharges the photoelectric conversion unit 402 so that the charge generated in the photoelectric conversion unit 402 is not mixed into the charge holding unit 403 while the signal holding unit 403 holds the signal charge. Can be. The reset transistor M3 sets the charge / voltage conversion unit 404 to a predetermined potential before the signal charge is transferred from the charge holding unit 403 (reset operation). At this time, the potential of the charge-voltage conversion unit 404 is output from the pixel output unit 407 to the column amplification circuit 531 as a noise signal. Subsequently, the reset transistor M3 is turned off, and a signal based on photoelectric conversion is output to the column amplifier circuit 531. The column amplifier circuit 531 generates a signal from which the noise signal has been removed by outputting a difference signal between the noise signal and a signal based on photoelectric conversion.

  FIG. 7 is a plan view of the pixel region 501 of the solid-state imaging device according to the present embodiment as viewed from the Z-axis direction. FIG. 7 shows the pixel circuit 401 of 3 rows × 3 columns constituting the pixel region 501, but the number of pixels is not limited as described above. In each pixel circuit 401, a substantially inverted S-shaped active region 102 a is defined by the element isolation region 102. On the active region 102a, gate electrodes 601 to 606 of transistors M1 to M6 constituting the pixel circuit are arranged. That is, a plurality of gate electrodes 601, 602, 603, 604, 605 are arranged in this order from the lower side of the active region 102a in FIG. 7 so as to cross the active region 102a. Here, the gate electrode 601 is the gate electrode of the first transfer transistor M1, and the gate electrode 602 is the gate electrode of the second transfer transistor M2. The gate electrode 603 is the gate electrode of the reset transistor M3, and the gate electrode 604 is the gate electrode of the amplification transistor M4. The gate electrode 605 is a gate electrode of the selection transistor M5. The gate electrodes 604 and 605 are adjacent to each other in plan view.

  An active region 102a on the lower side of the gate electrode 601 is a photoelectric conversion unit 402 configured by a photodiode. An active region 102 a between the gate electrode 601 and the gate electrode 602 is a charge holding unit 403 that temporarily holds charges transferred from the photoelectric conversion unit 402. A first transfer transistor M <b> 1 is formed between the photoelectric conversion unit 402 and the charge holding unit 403. An active region 102 a between the gate electrode 602 and the gate electrode 603 is a charge-voltage conversion unit 404.

  The active region 102a is connected between the photoelectric conversion portion 402 and a connection portion to the power supply voltage line (the active region 102a between the gate electrodes 603 and 604), and on this connection portion, the gate electrode of the OFD transistor M6 606 is arranged. A light shielding member 308 is provided on the charge holding portion 403 and the gate electrodes 601 and 602. In FIG. 7, black circles schematically represent contact portions for connection to upper layer wiring.

  FIG. 8 is a schematic cross-sectional view of the pixel region and the peripheral region of the solid-state imaging device according to the present embodiment. That is, the pixel region 501 on the left side of FIG. 8 shows a cross section from the charge holding unit 403 of the line AA ′ in FIG. 7 to the selection transistor M5, and the peripheral region 502 on the right side of the dotted line is the column amplifier circuit path. A cross section of any two transistors provided adjacent to each other in FIG. FIG. 8 also shows a cross-sectional view parallel to the XY plane and a cross-sectional view parallel to the YZ plane.

  In the semiconductor substrate 100, a well 101 composed of a P-type semiconductor region and an element isolation region 102 are provided. In the pixel region 501, the element isolation region 102 defines a substantially inverted S-shaped active region 102a as shown in FIG. An active region 102 b is defined in the peripheral region 502 by the element isolation region 102.

  On the surface portion of the active region 102a of the pixel region 501, an N-type semiconductor region 421 and a P-type semiconductor region 431, an N-type semiconductor region 422, an N-type semiconductor region 423, an N-type semiconductor region 424, and an N-type semiconductor region 425 are provided. They are separated from each other. The N-type semiconductor region 421 is an impurity region that forms the charge holding portion 403. The P-type semiconductor region 431 is a surface protective layer for the N-type semiconductor region 421. The N-type semiconductor region 422 is an impurity region (floating diffusion region) that constitutes the charge-voltage conversion unit 404. The N-type semiconductor region 423 is an impurity region that constitutes the drains of the reset transistor M3 and the amplification transistor M4. The N-type semiconductor region 424 is an impurity region that constitutes the source of the amplification transistor M4 and the drain of the selection transistor M5. The N-type semiconductor region 425 is an impurity region that constitutes the source of the selection transistor M5, and functions as the pixel output unit 407.

  A gate electrode 602 is provided on the semiconductor substrate 100 between the N-type semiconductor region 421 and the N-type semiconductor region 422 with a gate insulating film 103 interposed therebetween. As a result, a second transfer transistor M2 having a source / drain region constituted by the N-type semiconductor regions 421 and 422 and the gate electrode 602 is formed. A gate electrode 603 is provided on the semiconductor substrate 100 between the N-type semiconductor region 422 and the N-type semiconductor region 423 with a gate insulating film 103 interposed therebetween. Thereby, a reset transistor M3 having a source / drain region constituted by the N-type semiconductor regions 422 and 423 and a gate electrode 603 is formed. A gate electrode 604 is provided on the semiconductor substrate 100 between the N-type semiconductor region 423 and the N-type semiconductor region 424 with the gate insulating film 103 interposed therebetween. Thus, an amplification transistor M4 having a source / drain region constituted by the N-type semiconductor regions 423 and 424 and the gate electrode 604 is formed. A gate electrode 605 is provided over the semiconductor substrate 100 between the N-type semiconductor region 424 and the N-type semiconductor region 425 with the gate insulating film 103 interposed therebetween. Thus, a selection transistor M5 having a source / drain region constituted by N-type semiconductor regions 424 and 425 and a gate electrode 605 is constituted.

  N-type semiconductor regions 426, 427, and 428 are provided apart from each other on the surface portion of the active region 102b of the peripheral region 502. A gate electrode 607 is provided on the semiconductor substrate 100 between the N-type semiconductor region 426 and the N-type semiconductor region 427 with a gate insulating film 103 interposed therebetween. Thus, a peripheral transistor 617 having a source / drain region constituted by N-type semiconductor regions 426 and 427 and a gate electrode 607 is constituted. A gate electrode 608 is provided on the semiconductor substrate 100 between the N-type semiconductor region 427 and the N-type semiconductor region 428 with a gate insulating film 103 interposed therebetween. Accordingly, a peripheral transistor 618 having source / drain regions formed of N-type semiconductor regions 427 and 428 and a gate electrode 608 is formed. A metal silicide film 432 for reducing wiring resistance, diffusion layer resistance, contact resistance, and the like is provided on the surface portions of the N-type semiconductor regions 426, 427, 428 and the gate electrodes 607, 608 of the peripheral transistors 617, 618. Yes. As the metal silicide film 432, cobalt silicide, titanium silicide, or the like is applicable.

  Dielectric films 701 and 702 are provided on the semiconductor substrate 100 in the pixel region 501 so as to cover the upper and side surfaces of the gate electrodes 602, 603, 604, and 605. Side wall spacers 703 a and 704 are provided on the side surfaces of the gate electrodes 602, 603, 604, and 605 covered with the dielectric films 701 and 702.

  Sidewall spacers 701 a are provided on the side surfaces of the pair of gate electrodes 607 and 608 of the peripheral transistors 617 and 618 disposed in the peripheral region 502. A dielectric film 703 is provided on the semiconductor substrate 100 in the peripheral region 502 so as to cover the upper surfaces and the side surfaces of the gate electrodes 607 and 608 whose side surfaces are covered with the sidewall spacers 701a. A sidewall spacer 704 is provided on the side surfaces of the gate electrodes 607 and 608 covered with the sidewall spacer 701 a and the dielectric film 703.

  An insulator film 301 is provided on the entire surface of the semiconductor substrate 100. A gap between the pair of gate electrodes 604 and 605 is not filled with the insulator film 301 and a void 801 is formed. That is, the void 801 exists in a region surrounded by the first and second gate electrodes 604 and 605 and the insulator film 301. The light shielding member 308 is not formed at a position facing the void 801 and the insulator film 301 in the Z-axis direction perpendicular to the plan view. Further, the gap between the pair of gate electrodes 607 and 608 is not filled with the insulator film 301, and a void 802 is formed. A light shielding member 308 is provided on the insulator film 301 in the pixel region 501 so as to cover the charge holding portion 403 and the gate electrode 602 of the second transfer transistor M2. Although not shown in FIG. 8, as in FIG. 2, the insulating film 301 is connected to the interlayer insulating film, the contact hole penetrating the interlayer insulating film and the insulating film 301, and the contact hole. Wiring is provided.

  9 to 11 are process cross-sectional views illustrating the method for manufacturing the solid-state imaging device according to the present embodiment. In FIG. 9A, an element isolation region 102 that defines active regions 102a and 102b is formed on a surface portion of a semiconductor substrate 100 by, for example, an STI method, a LOCOS method, or the like. Next, a well 101 composed of a P-type semiconductor region is formed in predetermined regions of the pixel region 501 and the peripheral region 502 by ion implantation. An N-type semiconductor region 421 and a P-type semiconductor region 431 are formed in the formation region of the charge holding portion 403 in the pixel region 501 by ion implantation.

  A gate insulating film 103 made of a silicon oxide film or the like is formed on the surface portions of the active regions 102a and 102b of the semiconductor substrate 100 by using, for example, a thermal oxidation method or a CVD method. For example, a polysilicon film is deposited by CVD on the entire surface of the semiconductor substrate 100 on which the gate insulating film 103 is formed. Next, the polysilicon film is patterned using photolithography and dry etching to form gate electrodes 602, 603, 604, 605, 607, and 608 made of the polysilicon film. N-type semiconductor regions 422, 423, 424, and 425 are formed in the semiconductor substrate 100 in the pixel region 501 by self-alignment with the gate electrodes 602, 603, 604, and 605 by ion implantation.

  Although an example in which the N-type semiconductor region 421 and the P-type semiconductor region 431 are formed before the gate electrodes 602 to 608 are formed is shown here, the N-type semiconductor region 421 and the gate electrodes 602 to 608 are formed after the gate electrodes 602 to 608 are formed. A P-type semiconductor region 431 may be formed. In this case, the N-type semiconductor region 421 and the P-type semiconductor region 431 can be formed in a self-aligned manner with respect to the gate electrode 602, similarly to the N-type semiconductor regions 422, 423, 424, and 425.

  Next, a dielectric film 701 such as a silicon oxide film is formed on the entire surface of the semiconductor substrate 100 on which the gate electrodes 602 to 608 are formed by a CVD method or the like. The dielectric film 701 may be used as an antireflection film by forming a laminated structure of a silicon oxide layer and a silicon nitride layer. After forming a photoresist film (not shown) that covers the pixel region 501 and exposes the peripheral region 502 by photolithography, the dielectric film 701 in the peripheral region 502 is etched back using the photoresist film as a mask. Thus, the dielectric film 701 is left in the pixel region 501 and the side wall spacer (first dielectric film) made of the dielectric film 701 (first dielectric film) is formed on the side surfaces of the gate electrodes 607 and 608 in the peripheral region 502. Sidewall spacers) 701a are formed. Next, the photoresist film (not shown) used for the mask is removed by, for example, ashing.

  Next, in FIG. 9B, ion implantation is performed on the peripheral region 502 using the gate electrodes 607 and 608 and the sidewall spacer 701a as a mask. Thus, N-type semiconductor regions 426, 427, and 428 to be source / drain regions are formed in a self-aligned manner with respect to the gate electrodes 607 and 608 and the sidewall spacer 701a. Next, a dielectric film 702 is formed on the entire surface by using, for example, a CVD method. The dielectric film 702 is used as a protective film for the pixel region 501 when the metal silicide film 432 is formed in the peripheral region 502. After the dielectric film 702 is formed, a photoresist film (not shown) that covers the pixel region 501 and exposes the peripheral region 502 is formed by photolithography, and then the dielectric of the peripheral region 502 is formed using the photoresist film as a mask. The film 702 is etched. As a result, the dielectric film 702 is selectively left in the pixel region 501. Next, the photoresist film (not shown) used for the mask is removed by, for example, ashing.

  A metal silicide film 432 is selectively formed on the surface portions of the gate electrodes 607 and 608 and the N-type semiconductor region 426 in the peripheral region 502 where silicon is exposed by a salicide (Self-ALIgned siliCIDE) process. Specifically, for example, a metal film such as cobalt is deposited and heat treatment is performed, and silicon in a portion in contact with the metal film is silicided, and then the unreacted metal film is removed. Thereby, the metal silicide film 432 is locally formed.

  Next, as shown in FIG. 10A, a dielectric film (first dielectric film) 703 is formed on the entire surface by using, for example, a sputtering method, a CVD method, or the like. After forming a photoresist film (not shown) that covers the peripheral region 502 and exposes the pixel region 501 by photolithography, the dielectric film 703 in the pixel region 501 is etched back using the photoresist film as a mask. As a result, the dielectric film 703 is left in the peripheral region 502, and sidewall spacers (first layers) made of the dielectric film 703 are formed on the side surfaces of the gate electrodes 602 to 605 in the pixel region 501 covered with the dielectric films 701 and 702. 1 side wall spacer) 703a. Next, the photoresist film (not shown) used for the mask is removed by, for example, ashing.

  Next, as shown in FIG. 10B, after a second dielectric film such as a silicon oxide film is formed on the entire surface by using, for example, a CVD method, the dielectric film is etched back. . Thus, sidewall spacers (second sidewall spacers) 704 are formed on the side surfaces of the gate electrodes 602 to 605 covered with the dielectric films 701 and 702 and the sidewall spacers 703a. In addition, sidewall spacers 704 are formed on the side surfaces of the gate electrodes 607 and 608 covered with the sidewall spacers 701 a and the dielectric film 703. At this time, the dielectric films 701 and 703 may be used as etching stopper films by making the dielectric films 701 and 703 silicon nitride films.

  At this time, a narrow gap is generated or not generated between the sidewall spacers 704 depending on the thickness of the film covering the side surfaces of the gate electrodes 602 to 608 and the distance between the gate electrodes 602 to 608. For example, if the thickness of the film covering the side surfaces of the gate electrodes 602 to 608 is 0.2 μm, a narrow gap is formed between the sidewall spacers 704 when the distance between the gate electrodes 602 to 608 is narrower than 0.3 μm. Occur. Such a narrow gap can be generated, for example, between a pair of adjacent gate electrodes and a place where it is not necessary to provide a contact portion in an impurity region between the gate electrodes. For example, in FIG. 10B, a narrow gap is generated between the first gate electrode 604 and the second gate electrode 605 and between the first gate electrode 607 and the second gate electrode 608. Yes. Here, if the light shielding member 308 is directly formed in a narrow gap and then removed by etching, there is a possibility that a residue of the light shielding member 308 is generated as described above. As will be described later, according to the present embodiment, it is possible to prevent the generation of etching residues by forming voids in narrow gaps. Note that a contact portion is not provided in the impurity region between the first gate electrode 604 and the second gate electrode 605 as shown in FIG. On the other hand, such a narrow gap does not occur at a location where the distance between the gate electrodes 602 to 608 is larger than 0.4 μm.

  Next, as shown in FIG. 11, an insulator film 301 such as a silicon oxide film is formed by using, for example, a plasma CVD method or the like. At this time, the insulator film 301 is embedded in the gap between the first gate electrode 604 and the second gate electrode 605 and the gap between the first gate electrode 607 and the second gate electrode 608. The voids 801 and 802 are formed so as not to exist. By forming the insulator film 301 so as to leave the voids 801 and 802, depressions in the region between the gate electrodes 604 and 605 and between the gate electrodes 607 and 608 are reduced.

Specific film forming conditions, be formed by a TEOS-O2 system and _SiH 4 -O parallel plate plasma CVD method small CVD method anisotropy and fluidity like using ₂ based gas species Is preferred. This is because the void formation 801 is easily formed between the gate electrode 604, the gate electrode 605, and the insulator film 301, while a gap sufficiently narrower than the void 801 is blocked by increasing the deposition rate. This is because the depression of the film on the void can be reduced.

In this example, the gas flow rates were TEOS: 265 sccm, O ₂ : 2.5 sccm, and the pressure was 360 Pa. In addition, a plasma CVD oxide film corresponding to 500 mm was formed with an RF output of an upper electrode 720W and a lower electrode 320W and a film formation time of 4 seconds.

  Next, a light shielding member 308 made of tungsten, tungsten silicide, or the like is formed on the insulator film 301 by sputtering, CVD, or the like. Further, the light shielding member 308 is patterned into a predetermined shape by using photolithography and dry etching.

  By the patterning, the charge holding portion 403, the gate electrode 601 of the transfer transistor, and the light shielding member 308 on the gate electrode 602 of the second transfer transistor 612 remain, and other portions are removed by etching. At this time, the flatness of the surface of the insulator film 301 between the gate electrodes 604 and 605 and the region between the gate electrodes 607 and 608 is improved in the same manner as in the first and second embodiments. It is possible to prevent the etching residue 308 from being generated.

  In addition, by stacking the sidewall spacers 703 a and 704 on the side surface of the gate electrode 602, the step of the gate electrode 602 can be reduced. Thereby, the coverage of the light shielding member 308 is improved, and the light shielding performance is improved. Further, a void 801 is formed between the first gate electrode 604 of the amplification transistor M4 and the second gate electrode 605 of the selection transistor M5. The void 801 which is a void has a lower dielectric constant than the dielectric films 703 and 704 made of silicon oxide, silicon nitride, or the like. Therefore, the parasitic capacitance between the gate electrodes 604 and 605 can be reduced as compared with the case where the gap between the gate electrodes 604 and 605 is filled with the dielectric films 703 and 704. By reducing the parasitic capacitance of the gate electrode 604 of the amplification transistor M4, it is possible to suppress a decrease in amplification efficiency of the amplification circuit.

Similar to the first and second embodiments, the insulator film 301 also functions as an etch stopper film when the light shielding member is etched. In the Z-axis direction (first direction), the thickness of the insulating film 301 t, the thickness of the light-shielding member 308 and d _1, the ratio of the over-etch time for the main etch time when the light shielding member etch a, shielding Let b be the etching selection ratio of the insulator film 301 to the light shielding member during the member etching. At this time, the thickness of the insulator film etched during etching of the light shielding member is a × b × d ₁ .

If the film thickness t of the insulator film 301 is thinner than a × b × d ₁ , the surface of the dielectric film 703 is exposed in the pixel region during etching of the light shielding member. In the case where the dielectric film 703 is used as an antireflection film for a photodiode, the optical characteristics of the photodiode may change when the dielectric film 703 is etched to change the film thickness. Therefore, the film thickness t of the insulator film 301 is preferably a × b × d ₁ or more.

When the dielectric film 703 is not used as an antireflection film for a photodiode, the sum of the film thickness t of the insulator film 301 and the film thickness t ′ of the dielectric film 703 is thinner than a × b × d _1. Good.

Since contact between the light shielding member 308 and the wiring may cause a leak or the like, the film thickness t of the insulator film 301 is preferably such that the light shielding member and the wiring do not contact with each other. When the film thicknesses of the gate electrodes 607 to 608 in the pixel region are different, the sum of the film thickness of the larger gate electrode and the film thickness of the dielectric film 703 is d ₂ , out of the distance between the semiconductor substrate 100 and the wiring. When d ₃ is the smallest distance (film thickness of the interlayer insulating film) and d ₄ is the thickness of the gate insulating film 103, the film thickness t of the insulator film 301 is from d ₃ − (d ₁ + d ₂ + d ₄ ). Thin is preferred.

  From the viewpoint of light shielding properties, the greater the thickness of the insulator film 301, the greater the distance between the light shielding member 308 and the semiconductor substrate 100 and the lower the light shielding performance. Therefore, the thickness of the insulator film 301 should be as thin as possible. Is preferred.

Specific examples are described below. When using a tungsten light shielding member 308, in order to obtain a sufficient light-shielding ability, it is preferable that the thickness d ₁ is 0.1μm or more. The transmittance of tungsten is 0.2% or less at a thickness of 0.1 μm or more, and a sufficient light shielding ability can be achieved.

  When the ratio a of the over etch time to the main etch time during the light shielding member etching is 0.1 and the etching selection ratio b of the insulator film 301 to the light shielding member 308 is 0.1, the film thickness t of the insulator film 301 Needs to be at least 1 nm or more. Actually, it is necessary to consider manufacturing variations and the like, and the thickness of the insulator film 301 is preferably 5 nm or more.

Further, the gate electrode thickness d ₂ is 0.2 μm, the smallest distance (interlayer insulating film thickness) d ₃ of the distance between the substrate and the wiring is 0.6 μm, and the thickness of the gate insulating film 103 is 8. When the thickness is 0 nm, it is preferable that the thickness t of the insulator film 301 is at least smaller than 0.3 μm so as not to contact the wiring. Actually, since it is necessary to consider the manufacturing variations of the interlayer insulating film thickness, the film thickness of the light shielding member 308, and the decrease in the light shielding performance due to the increase in the film thickness t of the insulator film 301, the actual film thickness of the insulator film 301 t is preferably smaller than 0.1 μm.
Therefore, the thickness of the insulator film 301 is preferably 1 nm or more and less than 0.3 μm, more preferably 5 nm or more and less than 0.1 μm.

  As described above, according to this embodiment, the depression of the surface of the insulator film formed between the gate electrodes can be reduced, and the flatness of the base of the structure formed on this region is improved. be able to. In particular, in the case where the conductive film formed on the region between the gate electrodes is removed by etching, the residue of the conductive film can be suppressed in the depression of the insulator film, and the manufacturing yield can be improved. Furthermore, by forming a sidewall spacer on the side surface of the gate electrode, the light shielding performance can be improved.

  In the present embodiment, the case where the gap between the gate electrodes is narrower than 0.3 μm is exemplified as a condition for generating the narrow gap between the sidewall spacers, but the gap between the gate electrodes where the narrow gap is generated is not necessarily 0. However, the present invention is not limited to a case where the width is smaller than 3 μm. If the thickness of the insulator film deposited on the side surface of the gate electrode or the width of the sidewall spacer changes, the width of the gap between the sidewall spacers also changes accordingly. Therefore, the part where the insulator film is formed so that the voids remain is determined in consideration of the size of the depression formed on the insulator film according to the design rules and process conditions required for each solid-state imaging device. It is preferable to set appropriately.

  In this embodiment, the gate electrodes 601 to 605 in the pixel region 501 are covered with dielectric films 701 and 702, sidewall spacers 703 a and 704, and the insulator film 301. However, the structure of the insulator film / dielectric film covering the gate electrodes 601 to 605 is not limited to this. For example, the number of side wall spacers to be stacked may be increased or decreased as appropriate in accordance with the degree of relaxation of the level difference caused by the side wall spacers 703a and 704. Alternatively, either one of the dielectric films 701 and 702 may not be formed. The same applies to the peripheral area 502.

  Further, in the present embodiment, an example is shown in which a void is formed between the gate electrodes of the amplification transistor M4 and the selection transistor M5 in the pixel region 501, but the void is also formed between the gate electrodes of the other transistors M1 to M4 and M6. May be formed.

(Fourth embodiment)
An imaging system according to a fourth embodiment of the present invention will be described. Examples of the imaging system include a digital still camera, a digital camcorder, a copying machine, a facsimile, a mobile phone, an in-vehicle camera, and an observation satellite. FIG. 12 is a block diagram of a digital still camera as an example of an imaging system according to the fourth embodiment.

  In FIG. 12, an imaging system includes a barrier 1001 for protecting a lens, a lens 1002 for forming an optical image of a subject on a solid-state imaging device 1004, an aperture 1003 for changing the amount of light passing through the lens 1002, and a mechanical shutter 1005. Is provided. The imaging system further includes the solid-state imaging device 1004 described in the first to third embodiments, and the solid-state imaging device 1004 converts an optical image formed by the lens 1002 as image data. Here, it is assumed that an AD conversion unit is formed on the semiconductor substrate of the solid-state imaging device 1004. The imaging system further includes a signal processing unit 1007, a timing generation unit 1008, an overall control / arithmetic unit 1009, a memory unit 1010, a recording medium control I / F unit 1011, a recording medium 1012, and an external I / F unit 1013. The signal processing unit 1007 compresses various corrections and data into the imaging data output from the solid-state imaging device 1004. The timing generator 1008 outputs various timing signals to the solid-state imaging device 1004 and the signal processor 1007. The overall control / arithmetic unit 1009 controls the entire digital still camera, and the memory unit 1010 functions as a frame memory for temporarily storing image data. The recording medium control I / F unit 1011 performs recording or reading on the recording medium. The recording medium 1012 includes a detachable semiconductor memory or the like, and records or reads imaging data. The external I / F unit 1013 is an interface for communicating with an external computer or the like. Here, the timing signal or the like may be input from the outside of the imaging system, and the imaging system has at least a solid-state imaging device 1004 and a signal processing unit 1007 that processes the imaging signal output from the solid-state imaging device 1004. Good.

(Other embodiments)
The above-described embodiments are merely specific examples for carrying out the present invention, and the technical scope of the present invention is not limitedly interpreted by these embodiments. In other words, the present invention can be implemented in various forms without departing from the technical idea thereof. For example, the present invention can be widely applied to a circuit configuration in which etching residues of a light shielding member may occur, such as not only a gap between gate electrodes of a transistor but also a fine space between wiring patterns. In the above-described embodiments, the solid-state imaging device using the signal charge as electrons has been described as an example. However, the present invention can be similarly applied to a solid-state imaging device using the signal charge as holes. In this case, the conductivity type of the semiconductor region described above is reversed between the P type and the N type. Further, the planar layout of the pixel circuit of the solid-state imaging device shown in FIG. 6 is an example, and the planar layout of the pixel circuit of the solid-state imaging device to which the present invention can be applied is not limited to this. Absent. Furthermore, the configuration of the readout portion of the pixel circuit is not limited to the example shown in FIG.

  In the third embodiment, the present invention has been described by taking a CMOS image sensor having a global electronic shutter function as an example. However, a solid-state imaging device to which the present invention can be applied is not limited to a CMOS image sensor. For example, the present invention can be applied to a CCD image sensor. In the CCD image sensor, a light shielding member is disposed on a reading unit for reading and transferring charges generated by photoelectric conversion in the photoelectric conversion unit. The same structure and manufacturing method as in the above-described embodiment can be applied to the underlying structure and manufacturing method on which the light shielding member is deposited. In the present specification, the “charge holding unit” means the above-described readout unit when the solid-state imaging device is a CCD image sensor.

100 Semiconductor substrate 101 Well 102 Element isolation region 103 Gate insulating film 201, 202, 601 to 608 Gate electrode 203, 204, 205 Impurity region 301 Insulator film 303, 701 to 703 Dielectric film 302, 801, 802 Void 304 to 307 , 701a, 703a, 704 Side wall spacer 308 Light shielding members 421-425 N-type impurity region 432 P-type impurity region

Claims (24)

A method of manufacturing a solid-state imaging device,
Forming a first gate electrode of a first transistor and a second gate electrode of a second transistor adjacent to the first transistor on a substrate;
Forming an insulating film covering the first gate electrode and the second gate electrode so that a void is formed between the first gate electrode and the second gate electrode;
Forming a film on the insulator film;
Forming a light shielding member by etching away a part of the film located on the void across the insulator film; and
A method for manufacturing a solid-state imaging device. A direction in which the first gate electrode, the insulator film, and the film to be the light shielding member are stacked on the substrate is a first direction,
The ratio of the etching time of the insulator film to the etching time of the film to be the light shielding member is a, the etching selectivity ratio of the film to be the light shielding member and the insulator film is b, and the first of the insulator film is When the film thickness in the direction of t is t and the film thickness of the light shielding member in the first direction is d ₁ ,
The method for manufacturing a solid-state imaging device according to claim 1, wherein the insulator film is formed to satisfy the following formula.

Forming an interlayer insulating film covering the light shielding member, the first gate electrode, and the second gate electrode;
Forming a contact plug penetrating through the interlayer insulating film and the insulator film and connected to either the first transistor or the second transistor;
Forming a wiring connected to the contact plug on the interlayer insulating film;
The method for manufacturing a solid-state imaging device according to claim 1, further comprising:   The method of manufacturing a solid-state imaging device according to claim 3, wherein the contact plug is formed apart from the light shielding member. The void is formed on an impurity region shared by the first transistor and the second transistor,
The method for manufacturing a solid-state imaging device according to claim 3, wherein in the step of forming the contact plug, the contact plug is not formed on the impurity region.   5. The method of manufacturing a solid-state imaging device according to claim 1, wherein the void is formed on an impurity region shared by the first transistor and the second transistor. 6.   The method for manufacturing a solid-state imaging device according to claim 1, wherein the first transistor and the second transistor constitute a pixel circuit. The first gate electrode and the second gate electrode are:
A first transfer transistor that transfers charge from the photoelectric conversion unit to the charge holding unit;
A second transfer transistor that transfers the charge from the charge holding unit to the charge-voltage conversion unit;
A reset transistor for resetting a potential of the charge-voltage converter,
An amplification transistor that outputs a signal corresponding to the potential of the charge-voltage converter,
A selection transistor for selecting the amplification transistor;
The gate electrode of two of the transistors,
The method of manufacturing a solid-state imaging device according to claim 7, wherein the charge holding unit is covered with the light shielding member.   9. The method of manufacturing a solid-state imaging device according to claim 8, wherein the first gate electrode and the second gate electrode are a gate electrode of the amplification transistor and a gate electrode of the selection transistor.   The step of forming the film is performed in a state where a step due to the first gate electrode and the second gate electrode exists on the surface of the insulator film. The manufacturing method of the solid-state imaging device as described in 2. Between the step of forming the first gate electrode and the second gate electrode and the step of forming the insulator film,
Forming a dielectric film covering the first gate electrode and the second gate electrode;
Forming sidewall spacers on side surfaces of the first gate electrode and the second gate electrode by etching back the dielectric film;
The method for manufacturing a solid-state imaging device according to claim 1, further comprising: Between the step of forming the first gate electrode and the second gate electrode and the step of forming the insulator film,
Forming a first dielectric film covering the first gate electrode and the second gate electrode;
Forming a first sidewall spacer on side surfaces of the first gate electrode and the second gate electrode by etching the first dielectric film;
Forming a second dielectric film covering the first sidewall spacer;
Forming a second sidewall spacer on the first sidewall spacer by etching the second dielectric film;
Further comprising
11. The solid-state imaging device according to claim 1, wherein in the step of forming the second sidewall spacer, the second dielectric film is etched using the first dielectric film as an etching stopper. Manufacturing method.   13. The method of manufacturing a solid-state imaging device according to claim 1, wherein a thickness of the insulator film is thinner than thicknesses of the first gate electrode and the second gate electrode.   The method of manufacturing a solid-state imaging device according to claim 1, wherein a material of the film is tungsten or tungsten silicide. A first transistor having a first gate electrode; a second transistor having a second gate electrode adjacent to the first gate electrode in plan view; and the first gate electrode and the second gate. An insulator film covering the electrode;
A pixel circuit having a light shielding member provided on the insulator film,
There is a void in a region surrounded by the first gate electrode, the second gate electrode, and the insulator film,
The solid-state imaging device, wherein the light shielding member is not located at a position facing the void and the insulator film in a direction perpendicular to the planar view. Having side wall spacers respectively provided on side surfaces of the first gate electrode and the second gate electrode;
The solid-state imaging device according to claim 15, wherein the void is in a region surrounded by the insulator film and the sidewall spacer. The ratio of the etching time of the insulator film to the etching time of the film to be the light shielding member is a, the etching selectivity ratio of the insulator film to the film to be the light shielding member is b, and the plan view of the insulator film When the film thickness in the direction perpendicular to t is t and the film thickness in the direction perpendicular to the planar view of the light shielding member is d ₁ ,
The solid-state imaging device according to claim 15 or 16, wherein a film thickness t of the insulator film satisfies the following formula.

In the direction perpendicular to the plan view, the thickness of the insulator film is t, the thickness of the light shielding member is d ₁ , the thickness of the first gate electrode is d ₂ , the first transistor, and the first transistor when the substrate 2 of the transistor is formed the smallest distance among the distances between the wiring and the d _3,
The solid-state imaging device according to claim 15, wherein a thickness t of the insulator film satisfies the following formula.

The pixel circuit includes a charge-voltage conversion unit to which charges from the photoelectric conversion unit are transferred,
The solid-state imaging device according to claim 15, wherein the first gate electrode is connected to the charge-voltage conversion unit.   The solid-state imaging device according to claim 15, wherein one terminal of the second transistor is an output portion of the pixel circuit. The first transistor and the second transistor share an impurity region,
The solid-state imaging device according to claim 15, wherein the void is present on the impurity region. The pixel circuit includes:
A first transfer transistor for transferring the charge of the photoelectric conversion unit to a charge holding unit;
A second transfer transistor that transfers the charge of the charge holding unit to the charge-voltage conversion unit;
Including
The solid-state imaging device according to claim 19, wherein the light shielding member covers the charge holding unit, and the light shielding member does not cover the void.   The solid-state imaging device according to any one of claims 15 to 22, wherein a thickness of the insulator film in a direction perpendicular to the planar view is 1 nm or more and less than 0.3 µm. A first transistor having a first gate electrode;
A second transistor having a second gate electrode adjacent to the first gate electrode;
An insulator film covering the first gate electrode and the second gate electrode;
A light shielding member provided on the insulator film;
A pixel circuit having
There is a void in a region surrounded by the first gate electrode, the second gate electrode, and the insulator film,
The light shielding member is a solid-state imaging device that is not in a position facing the void and the insulator film, and
A signal processing unit for processing a signal output from the solid-state imaging device;
An imaging system.

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