JP3621273B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOS type solid-state imaging device using a metal oxide semiconductor (MOS) transistor for signal readout and a method for manufacturing the same.
[0002]
[Prior art]
Solid-state imaging devices are roughly classified into two types depending on the signal readout method. A CCD (charge coupled device) type that sequentially transfers signal charges and a MOS type that reads out a signal pixel by pixel using a readout circuit including a MOS transistor formed in each pixel. In recent years, MOS type solid-state imaging devices, in particular, so-called CMOS type solid-state imaging devices in which a pixel portion and a peripheral circuit are integrated by a CMOS (complementary MOS) process have low voltage and low power consumption. Therefore, it has been attracting attention as an image input element for portable devices such as small PC cameras.
[0003]
FIG. 4 shows the structure of a conventional MOS solid-state imaging device. Each pixel of the solid-state imaging device includes a light receiving unit and an amplifier circuit for amplifying and outputting an electric signal generated in the light receiving unit. The light receiving unit 42 is an n-type diffusion region formed in the p-type semiconductor substrate 41, and forms a photodiode by bonding with the substrate. Electron / hole pairs generated by incident light are separated by a depletion layer formed at a pn junction between the light receiving unit 42 and the semiconductor substrate 41, and electrons are accumulated in the light receiving unit 42. A change in the potential of the light receiving section 42 caused by this charge accumulation is amplified by an amplifier circuit and output.
[0004]
[Problems to be solved by the invention]
As the number of pixels and the size of solid-state imaging devices increase, improvement in sensitivity has become an issue. In order to improve the sensitivity of the solid-state imaging device, the amount of incident light that is photoelectrically converted may be increased by increasing the area of the light receiving unit. However, when the area of the light receiving portion is increased, the junction area between the light receiving portion and the substrate is increased, so that the charge storage capacity of the photodiode is increased. When the charge storage capacity increases, the conversion rate when converting charges into voltage decreases, and as a result, there has been a problem that sufficient sensitivity improvement of the solid-state imaging device cannot be realized.
[0005]
An object of the present invention is to provide a highly sensitive solid-state imaging device and a method for manufacturing the same.
[0006]
[Means for Solving the Problems]
As a method for achieving the above object, a plurality of pixels including a second conductivity type light receiving portion formed in a first conductivity type semiconductor substrate and an amplifier circuit electrically connected to the light receiving portion are arranged. In the solid-state imaging device, the width of the depletion layer formed at the junction between the light receiving unit and the semiconductor substrate includes at least a part of the bottom surface of the light receiving unit, rather than a region in contact with the surface of the semiconductor substrate. There is a method of enlarging the area in the substrate.
[0007]
According to such a configuration, the charge storage capacity of the photodiode can be reduced by expanding the depletion layer at the junction between the light receiving unit and the substrate in the region inside the semiconductor substrate. Therefore, according to this solid-state imaging device, since the charge / voltage conversion can be performed with a small capacity, a high conversion rate can be obtained and the sensitivity can be improved. Further, since the depletion layer is expanded in the depth direction of the semiconductor substrate, the spectral sensitivity on the long wavelength side can be improved. Moreover, since the depletion layer width at the junction between the light receiving portion and the substrate is narrow in the region on the surface of the semiconductor substrate, an increase in dark current can be suppressed.
[0008]
In the above configuration, it is preferable that the width of the depletion layer is 1.5 to 10 times as large as a region in contact with the semiconductor surface in the semiconductor substrate including at least a part of the bottom surface of the light receiving unit. According to this preferable example, it is possible to reliably achieve both high sensitivity of the solid-state imaging device and suppression of dark current..
[0009]
PreviousTo achieve the above purpose, the present inventionSolidThe body imaging device includes a second conductive type light receiving unit and a charge discharging unit formed in the first conductive type semiconductor substrate, and an insulating film on the semiconductor substrate between the light receiving unit and the charge discharging unit. A solid-state imaging device in which a plurality of pixels including a gate electrode formed through the amplifier and an amplifier circuit electrically connected to the light receiving unit are disposed, and located in the semiconductor substrate below the gate electrode A diffusion region of a first conductivity type having a higher impurity concentration than the semiconductor substrate is formed so as to avoid a region including a region and contacting at least a part of the bottom surface of the light receiving unit.
[0010]
In such a configurationAccording toThe charge storage capacity of the photodiode can be reduced, and a highly sensitive solid-state imaging device can be obtained. Moreover, the depletion layer formed in the junction part of a light-receiving part and a semiconductor substrate can be extended in the depth direction of a semiconductor substrate, and the spectral sensitivity on the long wavelength side can be improved. In addition, this solid-state imaging device can be manufactured by a conventional CMOS process if a mask for forming a p-type well (first conductivity type diffusion region) is a pattern avoiding a part of the region under the light receiving portion. Is possible.
[0011]
PreviousReconciliationIn the body imaging device, it is preferable that the diffusion region is formed so as to include a region on the surface of the semiconductor substrate in contact with the light receiving unit. This is because a depletion layer formed at the junction between the light receiving portion and the semiconductor substrate can be prevented from increasing on the surface of the semiconductor substrate, and an increase in dark current can be suppressed.
[0012]
Also beforeReconciliationIn the body imaging apparatus, it is preferable that the diffusion region is a region that is in contact with the bottom surface of the light receiving unit, and is formed so as to avoid a region having a width of 10 to 100% of the formation width of the light receiving unit. . This is because it becomes easy to form the diffusion region so as to include the region of the semiconductor substrate surface in contact with the light receiving portion.
[0013]
To achieve the above object, the present inventionSolidA method of manufacturing a body imaging device includes: a second conductive type light receiving unit and a charge discharging unit formed in a first conductive type semiconductor substrate; and the semiconductor substrate between the light receiving unit and the charge discharging unit. A method of manufacturing a solid-state imaging device in which a plurality of pixels including a gate electrode formed through an insulating film and an amplifier circuit electrically connected to the light receiving unit are arranged, wherein the gate is formed in the semiconductor substrate. After forming a first conductivity type diffusion region having an impurity concentration higher than that of the semiconductor substrate so as to avoid a region that includes a region located below the electrode and is in contact with at least a part of the bottom surface of the light receiving unit, The method includes a step of forming a gate electrode and a step of forming the light receiving portion and the charge discharging portion.
[0014]
With this configuration, it is possible to manufacture a highly sensitive solid-state imaging device by reducing the junction capacitance of the pn junction formed between the light receiving portion and the semiconductor substrate, that is, the charge storage capacitance of the photodiode. it can. In addition, a depletion layer formed at the junction between the light receiving portion and the semiconductor substrate can be expanded in the depth direction of the semiconductor substrate, so that a solid-state imaging device excellent in spectral sensitivity on the long wavelength side can be obtained. In addition, this manufacturing method can be carried out by the same operation as a conventional CMOS process if the mask for forming the p-type well (first conductivity type diffusion region) is a pattern that avoids a part of the region under the light receiving portion. .
[0015]
PreviousMakingIn the manufacturing method, it is preferable that the diffusion region is formed so as to include a region on the surface of the semiconductor substrate in contact with the light receiving portion. This is because an increase in dark current can be suppressed.
[0016]
Also beforeMakingIn the manufacturing method, it is preferable that the diffusion region is formed so as to avoid a region that is in contact with the bottom surface of the light receiving unit and has a width of 10 to 100% of the light receiving unit formation width. This is because it becomes easy to form the diffusion region so as to include the region of the semiconductor substrate surface in contact with the light receiving portion.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
(FirstReference example)
FIG.According to reference examplesIt is sectional drawing which shows an example of the structure of the pixel part of a solid-state imaging device. This solid-state imaging device employs a method of amplifying and outputting the voltage of the light receiving unit, and each pixel includes a light receiving unit and three transistors for amplifier, reset, and selection. The reset transistor is a transistor having a light receiving portion as a source, and a charge discharging portion which is a drain thereof is electrically connected to a power supply voltage. The amplifier transistor has a gate electrically connected to the light receiving portion, a drain electrically connected to the power supply voltage, and a source electrically connected to the drain of the selection transistor. The source of the selection transistor is connected to the output line.
[0018]
Briefly describing the role of each transistor, the amplifier transistor forms a source follower amplifier circuit with a load transistor (not shown) provided in another region, amplifies the voltage of the light receiving unit, and outputs the output line. It performs the function of reading out. The selection transistor is a switch for taking out the output of the amplifier transistor and functions to select a pixel from which a signal is read out. The reset transistor fulfills the function of discharging the signal charge held by the light receiving unit to the charge discharging unit at regular intervals.
[0019]
Hereinafter, the structure of the area around the light receiving portion shown as a cross-sectional view in FIG. 1 will be described in detail. A light receiving portion 12 and a charge discharging portion 14 are formed in the semiconductor substrate 11 in this region, and the reset transistor is disposed on the semiconductor substrate 11 between the light receiving portion 12 and the charge discharging portion 14 via an insulating film 15. A gate electrode 16 is formed. Although not shown, an interlayer insulating film, a metal light shielding film having an opening on the light receiving portion, a surface protective film, and the like are further formed above the semiconductor substrate 11.
[0020]
The semiconductor substrate 11 is not particularly limited as long as it is a p-type semiconductor substrate having an impurity concentration in a range in which a threshold voltage required for an nMOS such as a reset transistor can be obtained. However, if the impurity concentration of the p-type semiconductor substrate 11 is low, the width of the depletion layer 17 formed at the junction with the light receiving portion 12 becomes large in the region in contact with the surface of the semiconductor substrate, which may increase dark current. There is. Therefore, the impurity concentration of the p-type semiconductor substrate 11 is 1.5 × 10 5.¹⁵cm^-3Above (specific resistance: 10 Ω · cm or less), 3 × 10¹⁵~ 5x10¹⁵cm^-3It is preferable that the specific resistance is about 3 to 5 Ω · cm.
[0021]
Further, as the p-type semiconductor substrate 11, a semiconductor substrate in which a p-type well is formed in the surface layer portion can also be used. The impurity concentration of the p-type well is not particularly limited as long as the threshold voltage required for the nMOS can be obtained, but from the viewpoint of reducing dark current, it is 1 × 10.¹⁷cm^-3Above, further 1.5 × 10¹⁷~ 3x10¹⁷cm^-3It is preferable that Further, the semiconductor substrate used at this time is not particularly limited as long as it can form a p-type well.
[0022]
The light receiving unit 12 is an n-type impurity diffusion region formed in the p-type semiconductor substrate 11, and a photodiode is formed by a pn junction with the semiconductor substrate 11. The impurity concentration of the light receiving unit 12 is not particularly limited as long as it is within a range that can be photoelectrically converted and can be electrically connected to the amplifier circuit.²⁰cm^-3That's it. Further, the diffusion depth of the light receiving unit 12 is suitably about 0.2 to 0.4 μm.
[0023]
Reference exampleIn the solid-state imaging device, the p-type semiconductor substrate 11 has p in a region in contact with at least a part of the bottom surface of the light receiving unit 12.^-A mold diffusion region 13 is formed. This p^-By providing the type diffusion region 13, the width of the depletion layer at the pn junction between the light receiving portion and the substrate can be increased, the charge storage capacity of the photodiode can be reduced, and high sensitivity of the solid-state imaging device can be realized. . P^-Impurity concentration of the light diffusion region 13 and the light receiving portion 12 and p^-The standard sensitivity can be adjusted by adjusting the charge storage capacity of the photodiode according to the junction area with the mold diffusion region 13.
[0024]
p^-The impurity concentration of the type diffusion region 13 is not particularly limited as long as it is lower than that of the p-type semiconductor substrate 11 (or p-type well), and preferably 1 × 10 6.¹⁵cm^-3Or less, more preferably 4 × 10¹⁴~ 6 × 10¹⁴cm^-3Degree. This p^-As the impurity concentration of the type diffusion region 13 is lowered, the charge storage capacity of the photodiode can be reduced.
[0025]
By setting such an impurity concentration, the light receiving unit 12 and p^-The junction capacitance per unit area at the junction with the mold diffusion region 13 is smaller than that at the junction between the light receiving unit 12 and the p-type semiconductor substrate 11. In other words, the light receiving unit 12 and p^-The width of the depletion layer formed at the junction with the type diffusion region 13 is larger than that at the junction between the light receiving unit 12 and the p-type semiconductor substrate 11. Light receiving unit 12 and p^-The depletion layer width (a in FIG. 1) at the junction with the mold diffusion region 13 is preferably about 0.6 to 2.0 μm, more preferably about 1.2 to 1.8 μm. On the other hand, the depletion layer width (b in FIG. 1) at the junction between the light receiving portion 12 and the p-type semiconductor substrate 11 is suitably about 0.2 to 1.0 μm.
[0026]
Light receiving unit 12 and p^-As the junction area with the mold diffusion region 13 increases, the charge storage capacity of the photodiode can be reduced. However, since the dark current may increase on the surface of the semiconductor substrate, the light receiving unit 12 and p^-It is preferable that a bond with the mold diffusion region 13 is not formed. Therefore, p^-It is preferable that the mold diffusion region 13 avoids a region on the surface of the semiconductor substrate that is in contact with the light receiving unit 12 and is entirely buried under the light receiving unit. Therefore, p^-The formation width c of the mold diffusion region 13 is preferably equal to or smaller than the formation width d of the light receiving portion 12, specifically 10 to 100% of the formation width of the light receiving portion, and more preferably 40 to 40%. 80% is preferable. In terms of the formation area, it is preferably 10 to 100%, more preferably 20 to 65% of the formation area of the light receiving portion 12.
[0027]
P^-An appropriate diffusion depth of the mold diffusion region 13 is about 0.8 to 2.0 μm.
[0028]
next,Reference exampleAn example of a method for manufacturing the solid-state imaging device according to the present invention will be described.
[0029]
First, an insulating film is formed on the p-type silicon substrate 11 by thermal oxidation. A polysilicon film is deposited on the insulating film by a low pressure CVD method. The gate electrode 16 is formed by removing a part of the polysilicon film by etching.
[0030]
Next, a resist is formed so as to cover a part of the semiconductor substrate 11 and the gate electrode 16, and n-type impurities are ion-implanted into an appropriate region in the semiconductor substrate 11 within a range in which the conductivity type of the semiconductor substrate is not reversed. P^-A diffusion region 13 is formed. This ion implantation uses, for example, phosphorus as an n-type impurity, an acceleration voltage of 50 to 800 keV, and a dose amount of 1 × 10 6.¹¹~ 1x10¹³cm^-2As implemented.
[0031]
After the resist is removed, n-type impurities are ion-implanted using the gate electrode 16 as a mask to form the light receiving portion 12 and the charge discharging portion 14, and a reset transistor is formed. At this time, at least part of the bottom surface of the light receiving unit 12 is p.^-It is formed in contact with the mold diffusion region. Preferably, the light receiving unit 12 is p^-Adjusted to have a dimension equal to or larger than that of the diffusion region 13, p^-The diffusion region 13 is embedded in the semiconductor substrate 11 by the light receiving unit 12. In this ion implantation, for example, arsenic is used as an n-type impurity, the acceleration voltage is 40 keV, and the dose is 5 × 10.¹⁵cm^-2As implemented.
[0032]
Further, an interlayer insulating film, a metal wiring, and the like are formed, and the light receiving portion and the charge discharging portion are electrically connected to an amplifier transistor or the like formed in another region of the semiconductor substrate as shown in FIG. Although not particularly limited, a silicon oxide film formed by a low pressure CVD method is used as the interlayer insulating film, and an aluminum film is used as the metal wiring. Furthermore, a metal light-shielding film, a surface protective film, and the like having an opening in a portion corresponding to the upper part of the light receiving portion are appropriately formed. An aluminum film can be used as the metal light-shielding film, and a silicon nitride film formed by plasma CVD can be used as the surface protective film.
[0033]
The film formation method such as thermal oxidation or CVD method used in the above manufacturing method, the etching method, etc. may be basically performed according to a conventional method.
[0034]
(SecondReference example)
FIG.According to reference examplesIt is sectional drawing which shows another example of a solid-state imaging device. The structure of each pixel of the solid-state imaging device is the same as that of the first embodiment except for the structure of the area around the light receiving portion shown as a cross-sectional view in FIG.Reference exampleIt is the same. Hereinafter, the area around the light receiving unit will be described in detail. In this region, the light receiving portion 22 and the charge discharging portion 24 are formed in the semiconductor substrate 21, and the reset transistor is disposed on the semiconductor substrate 21 between the light receiving portion 22 and the charge discharging portion 24 via the insulating film 25. A gate electrode 26 is formed. Although not shown, an interlayer insulating film, a metal light shielding film having an opening on the light receiving portion, a surface protective film, and the like are further formed above the semiconductor substrate 21.
[0035]
As the semiconductor substrate 21, the firstReference exampleSimilarly to the above, a p-type semiconductor substrate or a semiconductor substrate in which a p-type well is formed can be used. In addition, the light receiving unit 22 includes the firstReference exampleLike, preferably, the impurity concentration is 1 × 10²⁰cm^-3The n-type diffusion region has a diffusion depth of about 0.2 to 0.4 μm.
[0036]
Reference example, In a region in contact with at least a part of the bottom surface of the light receiving portion 22 in the p-type semiconductor substrate 21, n^-A mold diffusion region 23 is formed. This n^-The mold diffusion region 23 together with the light receiving unit 22 forms a photodiode by a pn junction with the semiconductor substrate 21. n^-By providing the mold diffusion region 23, the depletion layer width of the pn junction between the light receiving portion and the substrate is increased, the charge storage capacity of the photodiode is reduced, and high sensitivity of the solid-state imaging device is realized. N^-Impurity concentration of the n-type diffusion region 23 and n^-The standard sensitivity can be adjusted by appropriately adjusting the charge storage capacity of the photodiode according to the junction area between the mold diffusion region 23 and the semiconductor substrate 21.
[0037]
n^-The impurity concentration of the mold diffusion region 23 is not particularly limited as long as it is lower than the impurity concentration of the light receiving portion 22, but preferably 1 × 10 6.¹⁶cm^-3Or less, more preferably 5 × 10¹⁵~ 8x10¹⁵cm^-3It is. This n^-The lower the impurity concentration in the mold diffusion region 23, the lower the charge storage capacity of the photodiode.
[0038]
By setting such an impurity concentration, n^-The junction capacitance per unit area at the junction between the mold diffusion region 23 and the semiconductor substrate 21 is smaller than that at the junction between the light receiving unit 22 and the semiconductor substrate 21. In other words, n^-The width of the depletion layer formed at the junction between the mold diffusion region 23 and the semiconductor substrate 21 is larger than that at the junction between the light receiving portion 22 and the semiconductor substrate 21. n^-The depletion layer width (a in FIG. 2) at the junction between the mold diffusion region 23 and the semiconductor substrate 21 is preferably about 0.8 to 2.5 μm, and more preferably about 1.2 to 2.0 μm. On the other hand, the depletion layer width (b in FIG. 2) at the junction between the light receiving portion 22 and the semiconductor substrate 21 is suitably about 0.2 to 1.0 μm.
[0039]
n^-As the junction area between the mold diffusion region 23 and the semiconductor substrate 21 increases, the charge storage capacity of the photodiode can be reduced. However, since the dark current may increase on the surface of the semiconductor substrate, the light receiving portions 22 and n^-It is preferable that a bond with the mold diffusion region 23 is not formed. Therefore, n^-It is preferable that the mold diffusion region 23 avoids a region on the surface of the semiconductor substrate that is in contact with the light receiving unit 22, and is entirely embedded under the light receiving unit 22. Therefore, n^-The formation width e of the mold diffusion region 23 is preferably equal to or smaller than the formation width d of the light receiving portion 22, specifically, 10 to 100% of the formation width of the light receiving portion 22, and further 40 It is preferable that it is -80%. In terms of the formation area, it is preferably 10 to 100%, more preferably 20 to 65% of the formation area of the light receiving portion 22.
[0040]
N^-An appropriate diffusion depth of the mold diffusion region 23 is about 0.8 to 2.0 μm.
[0041]
Reference exampleThe solid-state imaging device according to^-Instead of the step of forming the mold diffusion region, n^-Except for performing the step of forming the mold diffusion region,Reference exampleIt can be manufactured in the same manner as the manufacturing method described above.
[0042]
After a resist is formed on the semiconductor substrate 21 on which the insulating film 25 and the gate electrode 26 are formed, n-type impurities are ion-implanted to form an n region in an appropriate region in the semiconductor substrate 21.^-A mold diffusion region 23 is formed. This ion implantation uses, for example, phosphorus as an n-type impurity, an acceleration voltage of 50 to 800 keV, and a dose amount of 1 × 10 6.¹²~ 1x10¹⁵cm^-2As implemented.
[0043]
After removing the resist, n-type impurities are ion-implanted using the gate electrode 26 as a mask to form the light receiving portion 22 and the charge discharging portion 24. At this time, at least a part of the bottom surface of the light receiving unit 22 is n.^-It is formed in contact with the mold diffusion region 23. Preferably, the light receiving unit 22 is n^-Adjusted to have a dimension equal to or larger than the mold diffusion region 23, n^-The mold diffusion region 23 is embedded in the semiconductor substrate 21 by the light receiving unit 22. In this ion implantation, for example, arsenic is used as an n-type impurity, the acceleration voltage is 40 keV, and the dose is 5 × 10.¹⁵cm^-2As implemented.
[0044]
Furthermore, an interlayer insulating film, metal wiring, a metal light-shielding film having an opening in a portion corresponding to the upper part of the light-receiving portion, a surface protective film, and the like are appropriately formed to obtain a solid-state imaging device.
[0045]
The film formation method such as thermal oxidation or CVD method used in the above manufacturing method, the etching method, etc. may be basically performed according to a conventional method.
[0046]
(FirstEmbodiment)
The solid-state imaging device according to this embodiment includes a CMOS solid-state imaging device in which a pixel unit and peripheral circuits (for example, a scanning circuit for pixel selection, a timing generation circuit, a noise cancellation circuit, etc.) are integrated using a CMOS process. It is. This solid-state imaging device has an nMOS and a pMOS in the same semiconductor substrate. Therefore, the semiconductor substrate has an n-type well in a region for forming the pMOS and a p-type well in a region for forming the nMOS. Each is formed.
[0047]
FIG. 3 is a cross-sectional view illustrating the structure of the pixel portion of the solid-state imaging device according to the present embodiment. Each pixel has a firstReference exampleSimilarly, the light receiving unit and three transistors for amplifier, reset, and selection are included. The connection between these members and the function of each member are as follows.Reference exampleAs explained in.
[0048]
Hereinafter, the structure of the area around the light receiving portion shown as a cross-sectional view in FIG. 3 will be described in detail. A p-type well 33 for forming an nMOS reset transistor is formed on the semiconductor substrate 31 in this region. A light receiving portion 32 and a charge discharging portion 34 are formed in the semiconductor substrate 31, and a gate electrode of a resetting transistor is provided on the semiconductor substrate 31 between the light receiving portion 32 and the charge discharging portion 34 via an insulating film 35. 36 is formed.
[0049]
The semiconductor substrate 31 is not particularly limited as long as it is a p-type semiconductor substrate having an impurity concentration within a range in which a p-type well and an n-type well can be formed. Preferably the impurity concentration is 2 × 10¹⁵cm^-3(Specific resistance is 5 Ω · cm or more), more preferably the impurity concentration is 1 × 10¹⁵~ 1.5 × 10¹⁵cm^-3P (specific resistance is about 10-15Ω · cm)^-Type semiconductor substrate can be used.
[0050]
The light receiving unit 32 is p^-An n-type impurity diffusion region formed in the type semiconductor substrate 31, and a photodiode is formed by a pn junction with the semiconductor substrate 31. The impurity concentration of the light receiving unit 32 is not particularly limited as long as it is a range that can be photoelectrically converted and can be electrically connected to the amplifier circuit, but is preferably 1 × 10.²⁰cm^-3That's it. Further, the diffusion depth of the light receiving part 32 is suitably about 0.2 to 0.4 μm.
[0051]
As described above, the p-type well 33 is formed in the surface layer portion of the semiconductor substrate 31 including at least the region located below the gate electrode 36. The impurity concentration of the p-type well 33 is p^-There is no particular limitation as long as it is higher than the impurity concentration of the type semiconductor substrate 31 and can obtain a threshold voltage required for an nMOS such as a reset transistor. However, if the impurity concentration of the p-type well 33 is too low, the width of the depletion layer formed at the junction with the light receiving portion 32 on the surface of the semiconductor substrate becomes large, which may increase the dark current. Therefore, the impurity concentration of the p-type well 33 is 1 × 10.¹⁷cm^-3Above, further 1.5 × 10¹⁷~ 3x10¹⁷cm^-3It is preferable to set the degree. Further, the diffusion depth of the p-type well 33 is suitably about 1.0 μm.
[0052]
The p-type well 33 is formed so as to avoid a region in contact with at least a part of the bottom surface of the light receiving unit 32. That is, at least a part of the bottom of the light receiving portion 32 is p having a lower impurity concentration than the p-type well 33.^-It is in contact with the mold area. In this way, by adjusting the impurity concentration of the semiconductor substrate at the junction with the light receiving portion 32 to be low in a part of the region, the depletion layer width at the pn junction between the light receiving portion and the substrate is increased, thereby increasing the photodiode. The charge storage capacity of the solid-state imaging device can be increased and the sensitivity of the solid-state imaging device can be increased. Further, a substrate region in which the p-type well 33 is not formed (hereinafter referred to as “p^-Type area ”. ) And the light receiving portion 32, the charge storage capacity of the photodiode can be adjusted as appropriate to adjust the standard sensitivity.
[0053]
Light receiving unit 32 and p^-The junction capacitance per unit area at the junction with the mold region 31 is smaller than that at the junction between the light receiving unit 32 and the p-type well 33. In other words, the width of the depletion layer formed at the junction between the light receiving portion 32 and the p-type region 31 is larger than that at the junction between the light receiving portion 32 and the p-type well 33. Light receiving unit 32 and p^-The depletion layer width (a in FIG. 3) at the junction with the mold region 31 is preferably about 1.0 to 3.0 μm, more preferably about 1.5 to 2.0 μm. On the other hand, the depletion layer width (b in FIG. 3) at the junction between the light receiving portion 32 and the p-type well 33 is suitably about 0.2 to 0.5 μm.
[0054]
Light receiving unit 32 and p^-As the junction area with the mold region 31 increases, the charge storage capacity of the photodiode can be reduced. However, since the dark current may increase on the surface of the semiconductor substrate, the light receiving unit 32 and p^-It is preferable that a bond with the mold region 31 is not formed. Therefore, the p-type well 33 is preferably formed so as to include at least a region in contact with the light receiving portion 32 on the surface of the semiconductor substrate. In this case, p on the bottom surface of the light receiving unit 32^-The width f of the portion in contact with the mold region is preferably 10 to 100%, more preferably 40 to 80% of the formation width d of the light receiving portion 32. In addition, p on the bottom surface of the light receiving unit 32^-The area of the portion in contact with the mold region is preferably 10 to 100%, more preferably 20 to 65% of the bottom surface of the light receiving unit 32.
[0055]
Next, an example of a method for manufacturing the solid-state imaging device according to the present embodiment will be described.
[0056]
First, p^-A p-type impurity is ion-implanted into the p-type silicon substrate 31 to form a p-type well 33. This ion implantation is performed so as to avoid the upper part of at least a part of the region to be the light receiving unit 32. In this ion implantation, for example, boron is used as a p-type impurity, the acceleration voltage is 400 keV, and the dose amount is 4 × 10.¹²cm^-2In addition, boron acceleration voltage 50 keV, dose amount 5 × 10¹²cm^-2As implemented.
[0057]
Next, after forming an insulating film on the p-type silicon substrate 31 by thermal oxidation, a polysilicon film is deposited by a low pressure CVD method, and a part thereof is removed by etching to form a gate electrode 36. Next, n-type impurities are ion-implanted using the gate electrode 36 as a mask to form the light receiving portion 32 and the charge discharging portion 34. At this time, at least a part of the bottom surface of the light receiving unit 32 is a region in the semiconductor substrate where the p-type well 33 is not formed (p^-It is formed in contact with the mold region 31). Preferably, the light receiving portion 32 is formed in contact with the p-type well 33 on the surface of the semiconductor substrate. In this ion implantation, for example, arsenic is used as an n-type impurity, the acceleration voltage is 40 keV, and the dose is 5 × 10.¹⁵cm^-2As implemented.
[0058]
Further, an interlayer insulating film, a metal wiring, and the like are formed, and the light receiving portion and the charge discharging portion are electrically connected to an amplifier transistor or the like formed in another region of the semiconductor substrate as shown in FIG. Furthermore, a metal light-shielding film, a surface protective film, and the like having an opening in a portion corresponding to the upper part of the light receiving portion are appropriately formed.
[0059]
The film formation method such as thermal oxidation or CVD method used in the above manufacturing method, the etching method, etc. may be basically performed according to a conventional method.
[0060]
【Example】
(Reference example 1)
A solid-state imaging device having the same structure as that in FIG. 1 was produced. Impurity concentration of 5 × 10 as a semiconductor substrate¹⁵cm^-3A p-type silicon substrate having a specific resistance of 3 Ω · cm was used, and a silicon oxide film was formed on the p-type silicon substrate by thermal oxidation. After depositing a polysilicon film on the silicon oxide film by a low pressure CVD method, it was patterned by etching to form a gate electrode. Next, the acceleration voltage is 600 keV, and the dose is 2 × 10.¹¹cm^-2As phosphorus ions are implanted, p^-A mold diffusion region was formed. Formed p^-The impurity concentration of the mold diffusion region is 2 × 10¹⁵cm^-3Met. Next, using the gate electrode as a mask, the acceleration voltage is 40 keV, and the dose is 5 × 10.¹⁵cm^-2Arsenic was ion-implanted to form a light receiving portion and a charge discharging portion. The area of the formed light receiving part is 60 μm²The impurity concentration is 2 × 10²⁰cm^-3Met. As shown in FIG. 1, the light receiving unit and the charge discharging unit were electrically connected to an amplifier transistor, a selection transistor, and a power supply voltage formed in another region of the semiconductor substrate to obtain a solid-state imaging device.
[0061]
In the above manufacturing method, the light receiving portion and p^-The junction area with the mold diffusion region was adjusted to 30% (sample No. 1) and 60% (sample No. 2) of the light receiving area, and two types of solid-state imaging devices were manufactured. The width of the depletion layer was examined for these solid-state imaging devices.^-It was about 1.6 μm between the mold diffusion regions (a in FIG. 1), and about 0.8 μm between the light receiving portion on the substrate surface and the substrate (b in FIG. 1).
[0062]
For each solid-state imaging device, the output voltage with respect to the photodiode capacity and the incident light quantity of 10 lux (color temperature 3200 K) was evaluated. 1 has a photodiode capacitance of 16.8 fF and an output voltage of 100 mV. In No. 2, the photodiode capacity was 9.6 fF and the output voltage was 160 mV. The output voltage was measured by setting the capacity of the amplifier transistor to 2 fF and the power supply voltage to 5.0V.
[0063]
(Reference example 2)
p^-N instead of the mold diffusion region^-Except for forming the mold diffusion region,Reference example 1In the same manner, a solid-state imaging device having the same structure as that of FIG. 2 was produced. n^-The mold diffusion region is formed by accelerating voltage of 600 keV and dose amount of 1 × 10.¹²cm^-2This was carried out by phosphorus ion implantation. Also formed n^-The impurity concentration of the mold diffusion region is 1 × 10¹⁶cm^-3Met.
[0064]
Light receiver and n^-The junction area with the mold diffusion region was adjusted to 30% (sample No. 3) and 60% (sample No. 4) of the light receiving area, and two types of solid-state imaging devices were manufactured. When the depletion layer width was examined for these solid-state imaging devices, n inside the substrate was^-About 2.0 μm between the mold diffusion region and the substrate (a in FIG. 2), the light receiving portion (n⁺It was about 0.8 μm between the mold diffusion region) and the substrate (b in FIG. 2).
[0065]
For each solid-state imaging device, the output voltage with respect to the photodiode capacity and the incident light quantity of 10 lux (color temperature 3200 K) was evaluated. 3 has a photodiode capacitance of 15 fF and an output voltage of 110 mV. In No. 4, the photodiode capacitance was 9 fF and the output voltage was 170 mV. The output voltage was measured by setting the capacity of the amplifier transistor to 2 fF and the power supply voltage to 5.0V.
[0066]
(Example 1)
A solid-state imaging device having the same structure as FIG. 3 was produced. Impurity concentration of 1.5 × 10 as semiconductor substrate¹⁵cm^-3A p-type silicon substrate having a specific resistance of 10 Ω · cm was used. On this p-type silicon substrate, an acceleration voltage of 400 keV and a dose of 4 × 10¹²cm^-2As an ion implantation of boron, an acceleration voltage of 50 keV and a dose of 5 × 10¹²cm^-2As a result, boron was ion-implanted to form a p-type well. The impurity concentration of the p-type well is 2 × 10¹⁷cm^-3Met. As shown in FIG. 3, the p-type well was formed so as to avoid at least a part of the bottom surface of the light receiving portion that will be formed later. Next, a silicon oxide film was formed on the p-type silicon substrate by thermal oxidation, a polysilicon film was deposited on the silicon oxide film by a low pressure CVD method, and this was then patterned by etching to form a gate electrode. Using the gate electrode as a mask, the acceleration voltage is 40 keV, and the dose is 5 × 10.¹⁵cm^-2Arsenic was ion-implanted to form a light receiving portion and a charge discharging portion. The area of the formed light receiving part is 60 μm²The impurity concentration is 2 × 10²⁰cm^-3Met. As shown in FIG. 3, the light receiving unit and the charge discharging unit were electrically connected to an amplifier transistor, a selection transistor, and a power supply voltage formed in another region of the semiconductor substrate, to obtain a solid-state imaging device.
[0067]
In the above manufacturing method, the area of the bottom surface of the light receiving portion that is not in contact with the p-type well, that is, the light receiving portion and p^-The junction area with the mold region was adjusted to 60% (sample No. 5) and 80% (sample No. 6) of the light receiving area, and two types of solid-state imaging devices were manufactured. For these solid-state imaging devices, the width of the depletion layer formed between the light receiving unit and the substrate was examined.^-It was about 1.2 μm between the mold regions (a in FIG. 3), and about 0.2 μm between the light receiving portion on the substrate surface and the p-type well (b in FIG. 3).
[0068]
For each solid-state imaging device, the output voltage with respect to the photodiode capacity and the incident light quantity of 10 lux (color temperature 3200 K) was evaluated. 5 has a photodiode capacity of 20 fF and an output voltage of 95 mV. 6 had a photodiode capacitance of 10 fF and an output voltage of 155 mV. The output voltage was measured by setting the capacity of the amplifier transistor to 2 fF and the power supply voltage to 5.0V.
[0069]
(Comparative example)
p^-Except not forming the mold diffusion regionReference example 1In the same manner, a solid-state imaging device having the same structure as that of FIG. 4 was obtained. When the width of the depletion layer formed between the light receiving portion and the substrate was examined, it was about 1.0 μm both inside the substrate and on the substrate surface. When the output voltage with respect to the photodiode capacitance and the incident light quantity of 10 lux (color temperature 3200 K) was evaluated, the photodiode capacitance was 25 fF and the output voltage was 70 mV. The output voltage was measured by setting the capacity of the amplifier transistor to 2 fF and the power supply voltage to 5.0V.
[0070]
【The invention's effect】
BookAccording to the solid-state imaging device of the invention, the second conductive type light receiving unit and the charge discharging unit formed in the first conductive type semiconductor substrate, and the semiconductor substrate between the light receiving unit and the charge discharging unit. A plurality of pixels including a gate electrode formed through an insulating film and an amplifier circuit electrically connected to the light receiving portion are disposed, and a region located below the gate electrode is included in the semiconductor substrate. In addition, a highly sensitive solid-state imaging device is formed by forming a first conductivity type diffusion region having a higher impurity concentration than the semiconductor substrate so as to avoid a region in contact with at least a part of the bottom surface of the light receiving unit Can do.
[0071]
MaIn addition, the manufacturing method of the present invention includes a second conductivity type light receiving portion and a charge discharging portion formed in the first conductivity type semiconductor substrate, and the semiconductor substrate between the light receiving portion and the charge discharging portion. A method of manufacturing a solid-state imaging device in which a plurality of pixels including a gate electrode formed through an insulating film and an amplifier circuit electrically connected to the light receiving unit are arranged,A first conductivity type having a higher impurity concentration than the semiconductor substrate so as to avoid a region including a region located below the gate electrode in the semiconductor substrate and in contact with at least a part of the bottom surface of the light receiving unit. Forming a gate electrode after forming a diffusion region, and forming the light receiving portion and the charge discharging portion.Thus, a highly sensitive solid-state imaging device can be manufactured.
[Brief description of the drawings]
FIG. 1 shows the first of the present invention.Reference exampleIt is sectional drawing which shows the structure of 1 pixel of the solid-state imaging device concerning.
FIG. 2 shows a second embodiment of the present invention.Reference exampleIt is sectional drawing which shows the structure of 1 pixel of the solid-state imaging device concerning.
FIG. 3 shows the first aspect of the present invention.1It is sectional drawing which shows the structure of 1 pixel of the solid-state imaging device which concerns on this embodiment.
FIG. 4 is a cross-sectional view showing the structure of one pixel of a conventional solid-state imaging device.
[Explanation of symbols]
11, 21, 41 p-type semiconductor substrate
31 p-type semiconductor substrate
12, 22, 32, 42
13 p-type diffusion region
23 n-type diffusion region
33 p-type well
14, 24, 34, 44 Charge discharging part
15, 25, 35, 45 Insulating film
16, 26, 36, 46 Gate electrode
17, 27, 37, 47 Depletion layer

Claims (6)

A second conductive type light receiving portion and charge discharging portion formed in the first conductive type semiconductor substrate, and an insulating film formed on the semiconductor substrate between the light receiving portion and the charge discharging portion; A solid-state imaging device in which a plurality of pixels including a gate electrode and an amplifier circuit electrically connected to the light receiving unit are arranged, the semiconductor substrate including a region located below the gate electrode, and A solid-state imaging device, wherein a first conductivity type diffusion region having an impurity concentration higher than that of the semiconductor substrate is formed so as to avoid a region in contact with at least a part of the bottom surface of the light receiving unit. The solid-state imaging device according to claim 1, wherein the diffusion region includes a region on the surface of the semiconductor substrate that is in contact with the light receiving unit. 3. The solid-state imaging device according to claim 2, wherein the diffusion region is a region in contact with the bottom surface of the light receiving unit and is formed so as to avoid a region having a width of 10 to 100% of a formation width of the light receiving unit. A second conductive type light receiving portion and charge discharging portion formed in the first conductive type semiconductor substrate, and an insulating film formed on the semiconductor substrate between the light receiving portion and the charge discharging portion; A method of manufacturing a solid-state imaging device in which a plurality of pixels including a gate electrode and an amplifier circuit electrically connected to the light receiving unit are arranged, wherein a region located below the gate electrode is formed in the semiconductor substrate. And forming a gate electrode after forming a first conductivity type diffusion region having an impurity concentration higher than that of the semiconductor substrate so as to avoid a region in contact with a part of the bottom surface of the light receiving unit. And a step of forming the light receiving portion and the charge discharging portion. The manufacturing method of the solid-state imaging device according to claim 4, wherein the diffusion region is formed so as to include a region on the surface of the semiconductor substrate in contact with the light receiving unit. The solid-state imaging device according to claim 5, wherein the diffusion region is formed so as to avoid a region that is in contact with a bottom surface of the light receiving unit and has a width of 10 to 100% of a formation width of the light receiving unit.

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