JP3384509B2 - Solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for reading out charges from a photosensitive section to a charge transfer section by means of a reading gate.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional example of a CCD solid-state image pickup device. In this conventional example, an N type Si substrate 11 is used.
A P-well 12 is formed on the entire surface of the SiO ₂ film 13 as a gate insulating film and a polycrystalline Si film 1 as an electrode.
4 and the like are sequentially formed on the Si substrate 11.

Of the P well 12, a polycrystalline Si film 14
The P ⁺⁺ layer 15 is formed on the surface of the area surrounded by
An N layer 16 is formed under the P ⁺⁺ layer 15 so that these P ⁺⁺ layers are formed.
The layer 15 and the N layer 16 form a photosensitive portion 17. Then, P ⁺⁺ layer 15 has become a hole accumulation layer for reducing the dark current, N layer 16 is in the electron storage layer.

A P layer 21 is formed in a region of the P well 12 under the polycrystalline Si film 14 in contact with the P ⁺⁺ layer 15 and the N layer 16. The polycrystalline Si film 14 and the like and the P layer 21 constitute a read gate 22.
The layer 21 is the channel portion of the read gate 22.

An N layer 23 is formed in a region of the P well 12 under the polycrystalline Si film 14 that is in contact with the P layer 21 on the side opposite to the P ⁺⁺ layer 15 and the N layer 16, and the N layer 23 is formed. Under P
The layer 24 is formed. Then, the polycrystalline Si film 14 and the like, and the N layer 23 and the P layer 24 constitute a vertical CCD register 25.

Of the P well 12 under the polycrystalline Si film 14, the N layer 23 and the P layer 24 and the P ^{+ +} layer 15 and the N ^{+ of the} adjacent pixel are formed.
A P ⁺ layer 26 is formed between the layer 16 and the P ⁺ layer 26.
Is P layer 21 is formed under, these P ⁺ layer 26 and P
A channel stopper 27 is constituted by the layer 21. The P layer 21 which is a part of the channel portion of the read gate 22 and the channel stopper 27 is formed on the Si substrate 11
It is formed on the entire surface of.

In the conventional example as described above, in order to read the electrons accumulated in the N layer 16 to the vertical CCD register 25 by the read gate 22, the N layer 16 is self-aligned with the polycrystalline Si film 14 or the like. Need to be formed. Therefore, the N layer 16 is formed by ion implantation using the polycrystalline Si film 14 or the like as a mask.

[0008]

However, the N layer 16
The polycrystalline Si film 14 is required to have a predetermined thickness so that the ions do not penetrate the polycrystalline Si film 14 during the formation. For this reason, when the unit pixel is miniaturized, the aspect ratio of the patterned polycrystalline Si film 14 becomes large, and the polycrystalline Si film 14 and the Al wiring layer (not shown) and the Al light shielding film (not shown) above it. In addition to the difficulty in processing, the incident light on the photosensitive portion 17 is more likely to be eclipsed by the Al light-shielding film, and the sensitivity is also reduced.

When the unit pixel is miniaturized, the length of the read gate 22 is shortened, the threshold voltage thereof is lowered by the short channel effect, and the blooming margin is reduced. If the impurity concentration of the P layer 21 is increased in order to secure the blooming margin, the threshold voltage of the read gate 22 becomes too high, and the charges cannot be read from the photosensitive unit 17 to the vertical CCD register 25.

On the other hand, in the miniaturization of the unit pixel, not only the lateral reduction but also the acceleration energy at the time of ion implantation for forming the N layer 16 is lowered, and the film thickness of the polycrystalline Si film 14 is thinned. At the same time, it is possible to reduce the aspect ratio of the patterned polycrystalline Si film 14 by making the N layer 16 shallower in the vertical direction.

However, if the N layer 16 is made shallow, the tail portion of the P layer 21 formed on the entire surface of the Si substrate 11 can be compensated for impurities by the N layer 16, as is clear from the impurity profile shown in FIG. Disappear. As a result, N layer 1
The tail portion of 6 is not depleted, the potential of the overflow barrier with respect to the Si substrate 11 remains high, and the blooming margin cannot be secured.

That is, in the conventional example shown in FIG. 3, it is difficult to secure the blooming margin, facilitate the processing, and improve the sensitivity. Further, in this one conventional example, the read gate 22 is of the surface channel type, and the P ⁺⁺ layer 15 has a great influence on the threshold voltage of the read gate 22. Therefore, it is difficult to reduce the read voltage while ensuring the blooming margin.

[0013]

According to another aspect of the present invention, there is provided a solid-state image pickup device comprising: a first impurity layer 15 of a first conductivity type which constitutes a photosensitive portion 17; and a first impurity layer 15 provided below the first impurity layer 15. The second impurity layer 16 of the second conductivity type that constitutes the photosensitive portion 17 and the channel portion of the read gate 22 that reads out charges from the photosensitive portion 17 to the charge transfer portion 25 are included.
A third impurity layer 21 of the first conductivity type formed in
; And a third fourth of the second conductivity type that have a tail portion and a portion where the impurity profile is superimposed impurity layer 21 of impurity layer 28, the impurity profile is superimposed
Is located at least under the second impurity layer 16.
It is characterized by placing .

The solid-state image pickup device according to the second aspect is characterized in that the fourth impurity layer 28 is provided below the third impurity layer 21.

[0015]

[Action] In the solid-state imaging device according to claim 1, the third impurity is formed to include a channel portion of the second impurity layer 1 6 and the and the readout gate 22 of the same conductivity type constituting the light-sensitive portion 17 A fourth impurity layer 28 having a portion where the tail profile of the layer 21 and the impurity profile overlap is provided.
And there are few parts where the impurity profile overlaps.
Both Runode be positioned below the second impurity layer 16, even shallow second impurity layer 16, a tail portion of the second impurity layer 16 is depleted, the potential of the overflow barrier to the semiconductor substrate 11 is low As a result, a blooming margin can be secured.

According to another aspect of the solid-state imaging device of the present invention, the third impurity layer 2 forming the channel portion of the read gate 22 is formed.
Since the fourth impurity layer 28 having a conductivity type opposite to that of the first impurity layer 28 is also provided under the third impurity layer 21, the read gate 2
2 is a buried channel type, and the influence of the first impurity layer 15 forming the photosensitive portion 17 on the threshold voltage of the read gate 22 is small.

[0017]

Embodiment An embodiment of the present invention applied to a CCD solid-state image pickup device will be described below with reference to FIGS. In the present embodiment shown in FIG. 1, the thickness of the polycrystalline Si film 14 is 500 nm or less, which is thinner than the conventional example shown in FIG.
Therefore, the acceleration energy for forming the self-aligned manner N layer 16 of polycrystalline Si film 14 with respect to the polycrystalline Si film 14 by ion implantation using a mask, ions of impurities are polycrystalline Si film 14 The N layer 16 needs to be as low as 0.6 MeV or less so as not to penetrate, and the N layer 16 is shallower than in the conventional example.

However, since the N layer 16 may be buried in the P ⁺⁺ layer 15 only by making the N layer 16 shallow,
The acceleration energy when forming the P ⁺⁺ layer 15 by ion implantation is reduced, the dose amount is reduced, or the heat treatment amount is reduced, and the P ⁺⁺ layer 15 is also shallower than in the conventional example.

Further, if the N layer 16 is made shallow, as described above, the P layer 2 which has been conventionally impurity-compensated by the N layer 16 is used.
Since the tail portion of No. 1 is not compensated for impurities, the Si substrate 11
It becomes impossible to secure the blooming margin while the potential of the overflow barrier against is still high.

Therefore, in this embodiment, the N well is formed in the P well 12 over the entire surface of the imaging region by ion implantation with high acceleration energy of about 1 MeV or more and low dose amount of 2 × 10 ¹¹ cm ⁻² or less. 28 is formed. As shown in FIG. 2, the N well 28 has an impurity profile overlapping the tail portion of the P layer 21. Except for the above points, this embodiment has substantially the same configuration as the conventional example shown in FIG.

In the above-described embodiment, even if the N layer 16 is shallow, the tail portion of the N layer 16 is depleted due to the N well 28, and the overflow barrier of the overflow barrier for the Si substrate 11 in the region of the photosensitive portion 17 is formed. The potential is low and blooming margin is secured. Also, N well 28
Therefore, the read gate 22 is of a buried channel type, and the P ⁺⁺ layer 15 has a small influence on the threshold voltage of the read gate 22, so that the read voltage can be lowered.

Although the N well 28 is formed on the entire surface of the image pickup region in the above embodiments, the blooming margin can be ensured even if the N well 28 is formed only in the region of the photosensitive portion 17, and the reading is performed. Even if the N well 28 is formed only in the region of the gate 22, the read voltage can be lowered. Therefore, the N well 28 is not necessarily formed on the entire surface of the imaging region.
Need not be formed.

[0023]

According to the solid-state image pickup device of the present invention, since the blooming margin can be secured even when the second impurity layer forming the photosensitive portion is shallow, the second impurity layer is formed. It is possible to reduce the film thickness of the electrode of the read gate that serves as a mask during the ion implantation. For this reason,
The aspect ratio can be made small and processing is easy, and the incident light on the photosensitive portion is less eclipsed, and the sensitivity is high.

In the solid-state image pickup device according to the second aspect, the first impurity layer forming the photosensitive portion has little influence on the threshold voltage of the read gate, so that the read voltage can be lowered while ensuring the blooming margin. it can.

[Brief description of drawings]

FIG. 1 is a side sectional view of an embodiment of the present invention.

FIG. 2 is a graph showing an impurity profile at a position along line II-II in FIG.

FIG. 3 is a side sectional view of a conventional example of the invention of the present application.

FIG. 4 is a graph showing an impurity profile at a position along line IV-IV in FIG.

[Explanation of symbols]

15 P ⁺⁺ layer 16 N layer 17 Photosensitive portion 21 P layer 22 Read gate 25 Vertical CCD register 28 N well

Claims (2)

(57) [Claims] 1. A first conductive type first constituting a photosensitive portion.
And an impurity layer of the second conductivity type, which is provided below the first impurity layer and which constitutes the photosensitive section, and a read operation for reading out charges from the photosensitive section to the charge transfer section. a first conductivity type third impurity layer of which is formed to include a channel portion of the gate, the second conductivity type that have a tail portion and a portion where the impurity profile is superimposed in the third impurity layer of ; and a fourth impurity layer of the portion where the impurity profile is superimposed when less
Also under the second impurity layer . 2. The solid-state imaging device according to claim 1, wherein the fourth impurity layer is also provided below the third impurity layer.