JP2912533B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device,
More specifically, the present invention relates to a technique for increasing a signal capacity of a photoelectric conversion unit of a solid-state imaging device.

[0002]

2. Description of the Related Art Conventionally, various types of two-dimensional solid-state imaging devices have been known.
The CD type solid-state imaging device is excellent. Such CCD type solid-state imaging devices are roughly classified into an interline transfer type solid-state imaging device and a frame transfer type solid-state imaging device. At present, short-wavelength sensitivity is high, false signals called smear are small, and An interline transfer type solid-state imaging device, which is practically advantageous in that the chip size can be reduced, has become mainstream.

FIG. 3 shows a pixel structure in the case of an interline transfer type solid-state imaging device. Here, FIG.
(A) is a plan view of a conventional interline transfer type solid-state imaging device, (b) is a cross-sectional view taken along line II 'in the plan view, and (c) is a cross-sectional view taken along line II-II' in the plan view. It is sectional drawing. In FIG. 3, 1 is an n-type silicon substrate, 2 is a p ⁻ -type well region, 3 is a p-type impurity region, 4 is an n-type impurity region, 5 is a p ⁺ -type impurity region for pixel isolation, and 6 is an n-type impurity region. An impurity region, 7 is a p ⁺ -type impurity region, 8 is an insulating film, 9 is a transfer gate portion, 10 is an insulating film, and 11 is a gate polysilicon layer serving as a transfer electrode. The signal charge is shown for the case of electrons. In FIG. 3A, 13 is a CCD transfer unit, and 16, 17, 18, and 19 are four transfer electrodes composed of two layers. The transfer electrodes 16, 17, 18,
19, ΦV1, ΦV2, ΦV3, ΦV4 at four electrode cycles
Are applied.

A window portion not covered by the transfer electrodes 16, 17, 18, 19 has a photoelectric conversion unit 1 for performing photoelectric conversion.
Reference numeral 15 denotes a signal from the photoelectric conversion unit 14 which is a CCD.
This is a transfer gate area to be transferred to the transfer unit 13. As shown in FIG. 3, a method of providing p ⁺ -type impurity regions 5 for pixel separation in a stripe form only between the CCD transfer unit 13 and the photoelectric conversion unit 14 has been known in Japanese Patent Application Laid-Open No. 59-16472. This is a well-known technique.

As shown in FIGS. 3 (b) and 3 (c), in the present example, an n-type silicon substrate 1 is present below a photoelectric conversion portion 14 with a p ^- type well region 2 interposed therebetween. Vertical overflow drain structure. A high concentration p ⁺ -type impurity region 7 is provided on the surface of the photoelectric conversion unit 14. These structures are described, for example, in
124711, etc.

In the configuration of FIG. 3, the transfer electrodes 16, 1
Clocks ΦV1, ΦV2, Φ applied to 7, 18, 19
FIG. 4 shows the timings of V3 and ΦV4. In FIG. 4, the voltage level of each clock is ΦV1, ΦV3 is _VL ,
V _M and V _H have three values, and ΦV 2 and ΦV 4 have two values _VL and V _H.

In FIG. 4, at times t ₁ and t ₂ ΦV
1, .PHI.V3 goes to the _VH level, and the signal charge from the photoelectric conversion unit 14 is read out to the CCD transfer unit 13 via the transfer gate region 15. After that, the clock ΦV
1, .PHI.V2, .PHI.V3, and .PHI.V4 perform a normal transfer operation to sequentially transfer signal charges to the output unit side. One transfer cycle is indicated by a period T. FIG. 4 is a diagram showing the operation timing of the conventional solid-state imaging device.

[0008]

SUMMARY OF THE INVENTION In the configuration of FIG.
FIG. 5 shows the potential distribution in the II ′ direction. FIG (b) shows a case where the clock is a transfer operation with V _L, V _H, for the potential of the transfer gate region 15 is a low level, the photoelectric conversion unit 14 performs the charge accumulation operation. On the other hand, FIG. 5C shows an operation of reading out the electric charge accumulated in the photoelectric conversion unit 14 to the CCD transfer unit 13, and the clocks ΦV1 and ΦV3 become the V _H level, so that the potential of the transfer gate unit 15 becomes the high level. Thus, the charges accumulated in the photoelectric conversion unit 14 are read out to the CCD transfer unit 13.

However, in this case, there are the following problems. That is, as shown in FIG. 5B, the potential distribution of the photoelectric conversion unit 14 becomes shallow at the periphery of the photoelectric conversion unit 14 due to the two-dimensional effect. Here, the two-dimensional effect means that characteristics change depending on the surrounding density. For this reason, the effective capacity of the photoelectric conversion unit 14 decreases, and the maximum charge amount that can be accumulated in the photoelectric conversion unit 14 decreases. In particular, as the area of the photoelectric conversion unit 14 decreases, the two-dimensional effect increases.

As a countermeasure against this problem, Japanese Patent Application Laid-Open No. 63-18 / 1988
665. 6A is a plan view of a pixel, FIG. 6B is a cross-sectional view taken along the line Ib-Ib ′ of the plan view, and FIG. 6C is a potential distribution diagram of the same portion. The feature of the above method is that the concentration of the n-type impurity region 21 of each photoelectric conversion unit is increased in the region 22 provided around the photoelectric conversion unit and in contact with the p ⁺ impurity region 23 for pixel separation. However, this method also has the following problems.

That is, in this method, although there is no high concentration p ⁺ impurity region on the surface of each photoelectric conversion portion, the n-type impurity region 2
It is considered that the signal charge in the n-type impurity region 21 is completely transferred by lowering 1 to complete depletion. In this case, the difference in the concentration of the n-type impurity region 21 greatly changes the potential. Therefore, when the concentration in the periphery is increased, a slight variation in the increase amount causes the peripheral potential to be too deep.
There is a high possibility that signal charges are left behind. That is, FIG.
As shown in (c), the potential 29 in the peripheral portion is deeper than in other regions, and the charge is easily left here.

In FIG. 6C, reference numeral 25 denotes a transfer electrode; 26, a potential below the p ⁺ -type impurity region 23;
7 denotes a potential below the transfer gate portion, and 28 denotes a potential below the n-type impurity region 21.

Further, in this technique, it is necessary to form an n or n ⁺ -type impurity region in two steps, and since the depth of the n ⁺ -type impurity region is deep, the formation can be performed by thermal diffusion or high energy. Need to be injected. And in the case of thermal diffusion,
Since the horizontal direction increases, it is difficult to form only the periphery when the pixel size is small. For high energy implants,
It is necessary to match the surrounding borders in the first and second times,
In the case of self-implantation using a generally used polysilicon electrode, since implantation is performed twice with high energy, there is a problem that implanted ions partially penetrate the electrode.

In view of the above problems, the present invention can suppress the two-dimensional effect in each photoelectric conversion unit by a structure having good controllability of potential and low alignment accuracy, and as a result, the maximum accumulated charge of the photoelectric conversion unit It is an object of the present invention to provide means capable of easily increasing the amount.

[0015]

According to the present invention, there is provided a solid-state imaging device having a plurality of first conductivity type first impurity regions formed under a surface of a first conductivity type semiconductor region and below the first impurity regions. In a solid-state imaging device in which a photoelectric conversion unit including a second impurity region of a second conductivity type is formed, an impurity concentration of the first impurity region is lower in a peripheral part than in a central part. Is what you do.

[0016]

According to the present invention, by optimizing the effect that the potential of each photoelectric conversion portion becomes deeper in the peripheral portion, when the pixel size is reduced, the potential of each photoelectric conversion portion is reduced by the two-dimensional effect. The effect of shallowness in the part is completely negated.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on one embodiment.

FIG. 1A is a plan view of a solid-state imaging device according to an embodiment of the present invention, FIG. 1B is a sectional view taken along the line II ′ of FIG. 1A, and FIG. FIG. 2A is a sectional view taken along the line II-II ′ of FIG. In FIG. 1 (a), p ⁺ -type impurity region formed in a surface of the photoelectric conversion unit 14, the central portion of the p ⁺ impurity region 7a and the p ⁺ -type impurity regions 7a which covers the entire respective photoelectric conversion portion 14 surface And ap ⁺ -type impurity region 7b formed at
As a result, the concentration of the p ⁺ -type impurity region is
Every time it is high at the center and low at the periphery. Further, the impurity concentration of the p ⁺ -type impurity region 7b is substantially the same as the impurity concentration of the conventional p ⁺ -type impurity region 7.

FIG. 2A is a sectional view of a pixel corresponding to a potential distribution, and FIG.
FIG. 4 shows potential distribution diagrams during charge accumulation and charge transfer when ΦV2, ΦV3, and ΦV4 perform transfer operations at the _VL and _VH levels at the same timing as in the prior art, as shown in FIG. At the same timing, the charge of the photoelectric
FIG. 4 shows a potential distribution diagram at the time of charge accumulation and charge transfer when reading out to the CD transfer unit 13.

In FIG. 2A, since the potential of the transfer gate region 15 is low, the photoelectric conversion unit 1
4 performs a charge storage operation. In FIG. 2B, the clocks ΦV1 and ΦV3 are at the V _H level, the potential of the transfer gate section is at a high level, and the charges accumulated in the photoelectric conversion section 14 are read out to the CCD transfer section 13.

As shown in FIG. 2B, the photoelectric conversion unit 14
Is shallow in the peripheral portion due to the two-dimensional effect, but the p ⁺ -type impurity regions 7a and 7b on the surface of the photoelectric conversion portion 14
Accordingly, the potential is deepened in the peripheral portion, and the potential is canceled out, and the bottom of the potential distribution becomes flat for each photoelectric conversion unit 14. For this reason, the effective capacity of the photoelectric conversion unit 14 is increased, and the maximum charge amount that can be stored in the photoelectric conversion unit 14 can be significantly increased. In particular, the effect becomes larger as the area of the photoelectric conversion unit 14 becomes smaller.

Hereinafter, the manufacturing process of the solid-state imaging device according to the embodiment of the present invention will be described.

FIG. 7 is a manufacturing process diagram of the solid-state imaging device according to the first embodiment of the present invention, and FIG. 8 is a manufacturing process diagram of the solid-state imaging device of the second embodiment of the present invention.

The process for forming electrodes other than the transfer gate electrode is omitted, and the process for forming the photoelectric conversion portion will be mainly described.

In FIG. 7, reference numeral 1 denotes an n-type silicon substrate;
Is a p ⁻ -type well region, 3 is a p-type impurity region, 4 is an n-type impurity region, 5 is a p ⁺ -type impurity region, 6 is an n-type impurity region, 7a and 7b are p ⁺ impurity regions, 8a, 8b and 1
Reference numeral 0 denotes an insulating film, 9 denotes a polysilicon layer serving as a second-layer transfer electrode, and 11 denotes a polysilicon layer serving as a first-layer transfer electrode.

[0026] First, the ion implantation of boron into the n-type silicon substrate 1 is a semiconductor substrate, followed by heat treatment, p ^- -type well layer 2, the p ^- photoresist (shown on the type well layer 2 Is applied, exposed and developed, and p
A window is opened in a predetermined region of the p-type impurity region 3, boron ions are implanted, and the p-type impurity region
Is formed, and similarly, ion implantation of phosphorus is performed to form an n-type impurity region 4 which is a charge transfer portion.

Next, after removing the photoresist, an insulating film 8a under the gate, for example, Sin having a thickness of 350 ° or SiO ₂ having a thickness of 600 ° is formed on the silicon substrate 1, and the n-type impurity region 4 is removed. A p ⁺ -type impurity region 5 is formed by opening a window of a p ⁺ -type impurity region using a photoresist (not shown) on the insulating film 8 a on a predetermined region and performing ion implantation.

Next, after removing the photoresist, polysilicon is deposited to a thickness of about 4500 °, a gate pattern is formed using the photoresist, and etching is performed to form a polysilicon layer 9 serving as a first-layer transfer electrode. .

Next, after removing the photoresist, the insulating film 8a is entirely removed using the polysilicon layer 9 as a mask, and an insulating film 8b having a uniform thickness of, for example, about 1100 ° is formed on the silicon substrate 1 again.

Next, a pattern of the n-type impurity region 6 is formed with a photoresist (not shown) so that one side of the polysilicon layer 9 and the insulating film 10 on the polysilicon layer 9 is used as a mask. The ion implantation of phosphorus has an acceleration energy of 20 to 60 keV and a dose of 10 ¹³ to 10 ¹⁵ cm.
Self-aligned under the condition of ^-2 , and the n-type impurity region 6
Is formed (FIG. 7A).

Next, after the photoresist is removed, boron ions are implanted in a self-aligned manner using the polysilicon layer 9 and the insulating film 10 on the polysilicon layer 9 as a mask. ^{A +} type impurity region 7a is formed (FIG. 7B).

Next, a photoresist 30 is opened at a position distant from the polysilicon layer 9 and patterning is performed (FIG. 7).
(C)), then subjected to ion implantation to form the p ⁺ -type impurity region 7b in the central portion of the p ⁺ -type impurity region 7a on the surface (FIG. 7 (d)). The ion implantation conditions may be the same as those for forming the p ⁺ -type impurity region 7a.

Next, a manufacturing process of the solid-state imaging device according to the second embodiment of the present invention will be described with reference to FIG.

First, after steps similar to those shown in FIG.
(A)) After forming the p ⁺ -type impurity region 7a, an insulating film 31, for example, SiO ₂ is deposited to a thickness of about 2000 to 8000 ° (FIG. 8B).

Next, an etch back is performed to form a side wall 31 (FIG. 8C), an ion is implanted, and p
^{A +} type impurity region 7b is formed (FIG. 8D). The conditions for ion implantation may be the same as those in the first embodiment.

FIG. 9 is an impurity concentration distribution diagram in the depth direction of the silicon substrate in the central portion and the peripheral portion of the photoelectric conversion portion in this embodiment. In the photoelectric conversion portion, the impurity concentration of the p ⁺ -type impurity region in the peripheral portion is reduced. It is shown that the concentration is lowered from the central portion to solve the problem of reducing the signal charge storage capacity of the photoelectric conversion unit due to the two-dimensional effect, which is the object of the present invention.

FIG. 10 is a graph showing the depletion potential characteristics of the photoelectric conversion unit with respect to the ion implantation amount when forming the p ⁺ -type impurity regions 7a and 7b and the n-type impurity region 6 in the photoelectric conversion unit 14. is there. According to FIG.
^Since the change in the depletion potential of the light-receiving portion with respect to the relative implantation amount is smaller in the case where the ⁺ -type impurity regions 7a and 7b are formed than in the case where the n-type impurity region 6 is formed, p
^{Since the} influence of the ion implantation at the time of forming the ⁺ type impurity regions 7a and 7b on the potential of the photoelectric conversion portion can be made relatively small, the potential controllability is good.

[0038]

As described in detail above, by using the present invention, the higher the concentration of the p-type impurity region constituting the photoelectric conversion portion becomes, the more the n-type impurity region below the p-type impurity region becomes. The effect of canceling the concentration is enhanced, and the effect of lowering the depletion potential of the n-type impurity region is provided. Therefore, in the present invention, the potential of each photoelectric conversion unit becomes shallower at the center and deeper at the periphery.

By controlling the concentration of the p ⁺ -type impurity region as in the present invention, the influence on the potential distribution of the photoelectric conversion portion is compared with the conventional case where the potential distribution is controlled by the n-type impurity region. Therefore, the potential controllability is good.

In forming the p ⁺ -type impurity region having a two-stage concentration distribution in the present invention, the second ion implantation may be performed at the center of the p ⁺ -type impurity region formed by the first ion implantation. Therefore, the alignment accuracy of both may be loose.

As described above, by optimizing the effect that the potential of each photoelectric conversion portion becomes deeper in the peripheral portion, the effect that the potential of each photoelectric conversion portion becomes shallower in the peripheral portion due to the two-dimensional effect when the pixel size is reduced is reduced. It is possible to completely cancel. Therefore, as a result of the signal accumulation being spread over the entire area of the photoelectric conversion unit, the maximum signal storage capacity of the photoelectric conversion unit is greatly increased. Moreover, the method for realizing it is easy, and its practical value is extremely large.

[Brief description of the drawings]

FIG. 1A is a plan view of a solid-state imaging device according to an embodiment of the present invention, FIG. 1B is a cross-sectional view taken along the line II ′ in FIG. 1A, and FIG.
FIG. 2 is a sectional view taken along the line II-II ′ in FIG.

FIG. 2A is a sectional view of a pixel corresponding to a potential distribution according to the present invention, and FIGS. 2B and 2C are potential distribution diagrams at the time of charge accumulation and charge transfer.

3A is a plan view of a conventional interline transfer type solid-state imaging device, FIG. 3B is a cross-sectional view taken along line II ′ in FIG. 3A, and FIG. 3C is a cross-sectional view taken along line II-II ′ in FIG. It is sectional drawing.

FIG. 4 is a diagram showing operation timing of a conventional solid-state imaging device.

FIG. 5A is a sectional view taken along the line II ′ in FIG. 3A;
(B) is a potential distribution diagram when each clock is transferring at _VL and _VH , and (c) is a case where charges accumulated in the photoelectric conversion unit are read out to the CCD transfer unit. FIG. 4 is a potential distribution diagram of FIG.

FIG. 6A is a pixel plan view of a conventional solid-state imaging device,
(B) is a sectional view taken along the line Ib-Ib 'in (a), and (c) is a potential distribution diagram in (b).

FIG. 7 is a manufacturing process diagram of the solid-state imaging device according to the first embodiment of the present invention.

FIG. 8 is a manufacturing process diagram of the solid-state imaging device according to the second embodiment of the present invention.

FIG. 9 is an impurity concentration distribution diagram in the depth direction of the silicon substrate in the central part and the peripheral part of the photoelectric conversion unit in this example.

FIG. 10 is a diagram showing a depletion potential characteristic of a photoelectric conversion unit with respect to an ion implantation amount when forming ap ⁺ -type impurity region and an n-type impurity region in the photoelectric conversion unit.

[Explanation of symbols]

Reference Signs List 1 n-type silicon substrate 2 p ^- type well region 3 p-type impurity region 4 n-type impurity region 5 p ⁺ -type impurity region 6 n-type impurity region 7 a, 7 b p ⁺ -type impurity region 8 a, 8 b, 10, 31 insulating film 9 , 11 polysilicon layer 13 CCD transfer section 14 photoelectric conversion section 15 transfer gate area 16, 17, 18, 19 transfer electrode 30 photoresist

Claims (1)

(57) [Claims] A plurality of first impurity regions of a first conductivity type and a second impurity region of a second conductivity type formed under the first impurity region on a surface of the semiconductor region of the first conductivity type; A solid-state imaging device including a photoelectric conversion unit, wherein an impurity concentration of the first impurity region is lower in a peripheral portion than in a central portion.