JPH07142696A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To restrain the photoelectric conversion parts of a solid-stage image sensing device in two-dimensional effects by a method wherein first impurity regions of first conductivity-type are so formed as to set impurity concentration higher in their centers than in their peripheries. CONSTITUTION:A p<+>-type impurity region 7 formed on the surfaces of photoelectric conversion parts 14 is composed of a P<+>-impurity region 7a which covers all the surfaces of the photoelectric conversion parts 14 and a P<+>-type impurity region 7b located on the center of the P<+>-impurity region 7a. As a result, the impurity concentration of the P<+>-type impurity region 7 becomes higher in the center than in its periphery every photoelectric conversion part 14. Therefore, the photoelectric conversion part 14 can be restrained in a two-dimensional effect, so that it can be easily enhanced in maximum charge storing capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device,
More specifically, the present invention relates to a technique for increasing the signal capacity of a photoelectric conversion unit of a solid-state imaging device.

[0002]

2. Description of the Related Art Conventionally, various devices have been known as two-dimensional solid-state image pickup devices.
The CD type solid-state imaging device is excellent. Such CCD type solid-state image pickup devices are roughly classified into interline transfer type solid-state image pickup devices and frame transfer type solid-state image pickup devices, but at present, they have high short wavelength sensitivity and few false signals called smear. The interline transfer type solid-state imaging device, which is practically advantageous in that the chip size can be made small, has become the mainstream.

FIG. 3 shows a pixel structure in the case of an interline transfer type solid-state image pickup device. Here, FIG.
(A) is a plan view of a conventional interline transfer type solid-state imaging device, (b) is a cross-sectional view taken along the line I-I 'in the plan view, and (c) is a cross-sectional view taken along the line II-II' in the plan view. FIG. In FIG. 3, 1 is an n-type silicon substrate, 2 is a p ⁻ -type well region, 3 is a p-type impurity region, 4 is an n-type impurity region, 5 is a p ⁺ -type impurity region for pixel separation, and 6 is an n-type Impurity regions, 7 are p ⁺ -type impurity regions, 8 is an insulating film, 9 is a transfer gate portion, 10 is an insulating film, and 11 is a gate polysilicon layer to be a transfer electrode. The signal charges are shown for electrons. Further, in FIG. 3A, 13 is a CCD transfer unit, and 16, 17, 18, and 19 are four transfer electrodes each having two layers. The transfer electrodes 16, 17, 18,
ΦV1, ΦV2, ΦV3, and ΦV4 with a four-electrode period for 19
4 phase clock is applied.

The photoelectric conversion unit 1 in which the window portion not covered with the transfer electrodes 16, 17, 18 and 19 performs photoelectric conversion
4 and 15 are signals from the photoelectric conversion unit 14 to the CCD
This is a transfer gate region transferred to the transfer unit 13. A method of providing the p ⁺ -type impurity region 5 for pixel separation in a stripe pattern only between the CCD transfer section 13 and the photoelectric conversion section 14 as shown in FIG. 3 has been known from Japanese Patent Laid-Open No. 59-16472. This is a well-known technique.

As shown in FIGS. 3B and 3C, in this example, the n-type silicon substrate 1 exists below the photoelectric conversion portion 14 with the p ^- type well region 2 interposed therebetween. Vertical overflow drain structure. Further, a high-concentration p ⁺ type impurity region 7 is provided on the surface of the photoelectric conversion section 14. These structures are disclosed, for example, in JP-A-62-1
124771 and the like.

In the configuration of FIG. 3, the transfer electrodes 16 and 1
Clocks ΦV1, ΦV2, Φ applied to 7, 18, and 19
The timing of V3 and ΦV4 is shown in FIG. In FIG. 4, the voltage level of each clock is ΦV1, ΦV3 is _VL ,
Three values of V _M and V _H are set, and ΦV2 and ΦV4 are set to two values of V _L and V _H.

In FIG. 4, at times t ₁ and t ₂ , ΦV
1, ΦV3 becomes V _H level, and the signal charges from the photoelectric conversion unit 14 are read out to the CCD transfer unit 13 via the transfer gate region 15. After that, clock ΦV
1, ΦV2, ΦV3, and ΦV4 perform the normal transfer operation, and sequentially transfer the signal charges to the output side. One transfer cycle is shown as period T. 4. FIG. 4 is a diagram showing the operation timing of the conventional solid-state imaging device.

[0008]

In the configuration of FIG. 3,
The potential distribution in the I-I 'direction is shown in FIG. FIG. 11B shows a case where each clock is performing transfer operation at V _L and V _H , and since the potential of the transfer gate region 15 is low level, the photoelectric conversion unit 14 performs charge accumulation operation. On the other hand, FIG. 5C shows an operation of reading out the charges accumulated in the photoelectric conversion unit 14 to the CCD transfer unit 13, in which the clocks ΦV1 and ΦV3 are at the V _H level and the potential of the transfer gate unit 15 is at the high level. The charges accumulated in the photoelectric conversion unit 14 are read out to the CCD transfer unit 13.

However, in this case, there are the following problems. That is, as shown in FIG. 5B, the potential distribution of the photoelectric conversion unit 14 becomes shallow in the peripheral portion of the photoelectric conversion unit 14 due to the two-dimensional effect. Here, the two-dimensional effect means that the characteristics change depending on the ambient concentration. Therefore, the effective capacity of the photoelectric conversion unit 14 decreases, and the maximum amount of charge that can be accumulated in the photoelectric conversion unit 14 decreases. In particular, the smaller the area of the photoelectric conversion unit 14, the greater the two-dimensional effect.

As a measure against this problem, Japanese Patent Laid-Open No. 63-18 has been proposed.
There is a method shown in 665. 6A shows a pixel plan view, FIG. 6B shows a cross-sectional view taken along the line Ib-Ib ′ of the plan view, and FIG. 6C shows a potential distribution diagram of the same portion. The feature of the above method is that the concentration of the n-type impurity region 21 of each photoelectric conversion part is increased in the region 22 which is provided in the periphery of the photoelectric conversion part and is in contact with the p ⁺ impurity region 23 for pixel separation. However, this method also has the following problems.

That is, according to this method, although there is no high-concentration p ⁺ impurity region on the surface of each photoelectric conversion portion, the n-type impurity region 2
It is considered that 1 is lowered to completely deplete and the signal charge of the n-type impurity region 21 is completely transferred. In this case, the difference in the concentration of the n-type impurity region 21 greatly changes the potential. Therefore, when the peripheral concentration is increased, a slight variation in the increase amount makes the peripheral potential too deep,
There is a high possibility that the signal charge will be left behind. That is, FIG.
As shown in (c), the potential 29 in the peripheral portion is deeper than the other regions, and it is easy to leave electric charge there.

In FIG. 6C, 25 is a transfer electrode, 26 is a potential under the p ⁺ -type impurity region 23,
Reference numeral 7 indicates the potential under the transfer gate portion, and 28 indicates the potential under the n-type impurity region 21.

Further, in the technique, it is necessary to form the n or n ⁺ type impurity region in two steps, and since the n ⁺ type impurity region is deep, the formation is extended by thermal diffusion or a high energy is applied. Need to inject. And in the case of thermal diffusion,
Since it extends in the lateral direction, it is difficult to form only the periphery when the pixel size is small. In case of high energy injection,
It is necessary to match the borders around the first and second times,
In the case of self-implantation using a commonly used polysilicon electrode, there is a problem that implanted ions partially penetrate the electrode because the implantation is performed twice with high energy.

In view of the above problems, the present invention can suppress the two-dimensional effect in each photoelectric conversion unit by the structure in which the controllability of the potential is good and the alignment accuracy is loose, and as a result, the maximum accumulated charge of the photoelectric conversion unit is suppressed. It is an object of the present invention to provide a means capable of easily increasing the amount.

[0015]

In the solid-state imaging device of the present invention, a plurality of first conductivity type first impurity regions and a plurality of first conductivity type first impurity regions are formed on the surface of a first conductivity type semiconductor region. In a solid-state imaging device including a photoelectric conversion unit including a second impurity region of the second conductivity type, the impurity concentration of the first impurity region is lower in the peripheral portion than in the central portion. To do.

[0016]

By optimizing the effect that the potential of each photoelectric conversion portion becomes deeper in the peripheral portion by using the present invention, the potential of each photoelectric conversion portion is reduced by the two-dimensional effect when the pixel size is reduced. The effect of shallowing the area is completely negated.

[0017]

The present invention will be described in detail below based on an example.

FIG. 1A is a plan view of a solid-state image pickup device according to an embodiment of the present invention, FIG. 1B is a sectional view taken along the line II 'of FIG. 1A, and FIG. FIG. 11A is a sectional view taken along the line II-II ′ of FIG. In FIG. 1 (a), p ⁺ -type impurity region formed in a surface of the photoelectric conversion unit 14, the central portion of the p ⁺ impurity region 7a and the p ⁺ -type impurity regions 7a which covers the entire respective photoelectric conversion portion 14 surface And the p ⁺ -type impurity region 7b formed in.
As a result, the concentration of the p ⁺ -type impurity region becomes
Each time it is high in the central part and low in the peripheral part. The impurity concentration of the p ⁺ type impurity region 7b is set to be substantially the same as that of the conventional p ⁺ type impurity region 7.

FIG. 2A is a sectional view of a pixel corresponding to the potential distribution, and FIG. 2B is each clock ΦV1,
As shown in FIG. 4, ΦV2, ΦV3, and ΦV4 are potential distribution diagrams at the time of charge storage and charge transfer when the transfer operation is performed at the V _L and V _H levels at the same timing as in the conventional case. At the same timing, the electric charge of the photoelectric conversion unit 14 is changed to C
FIG. 6 is a potential distribution diagram during charge storage and charge transfer when reading out to the CD transfer unit 13.

In FIG. 2A, since the potential of the transfer gate region 15 is at a low level, the photoelectric conversion unit 1
4 performs charge accumulation operation. Further, in FIG. 2B, the clocks ΦV1 and ΦV3 are at the V _H level, the potential of the transfer gate unit is at the high level, and the charge accumulated in the photoelectric conversion unit 14 is read out to the CCD transfer unit 13.

As shown in FIG. 2B, the photoelectric conversion unit 14
Of the potential distribution of the p ⁺ -type impurity regions 7a and 7b on the surface of the photoelectric conversion portion 14 becomes shallower due to the two-dimensional effect.
As a result, the potential is canceled by the action that the potential becomes deeper toward the peripheral portion, and the bottom of the potential distribution becomes flat for each photoelectric conversion unit 14. Therefore, the effective capacity of the photoelectric conversion unit 14 increases, and the maximum amount of charge that can be accumulated in the photoelectric conversion unit 14 can be significantly increased. In particular, the smaller the area of the photoelectric conversion unit 14, the greater the effect.

The manufacturing process of the solid-state image pickup device of the embodiment of the present invention will be described below.

FIG. 7 is a manufacturing process drawing of the solid-state imaging device of the first embodiment of the present invention, and FIG. 8 is a manufacturing process drawing of the solid-state imaging device of the second embodiment of the present invention.

The electrode forming process other than the transfer gate electrode is omitted, and the forming process of the photoelectric conversion portion will be mainly described.

In FIG. 7, 1 is an n-type silicon substrate, 2
Is a p ^- type well region, 3 is a p-type impurity region, 4 is an n-type impurity region, 5 is a p ⁺ -type impurity region, 6 is an n-type impurity region, 7a and 7b are p ⁺ impurity regions, 8a, 8b and 1
Reference numeral 0 is an insulating film, 9 is a polysilicon layer serving as a second-layer transfer electrode, and 11 is a polysilicon layer serving as a first-layer transfer electrode.

[0026] First, the ion implantation of boron into the n-type silicon substrate 1 is a semiconductor substrate, followed by heat treatment, p ^- -type well layer 2, the p ^- photoresist (shown on the type well layer 2 No.) is applied, exposed and developed, and p
A window is opened in a predetermined region of the p-type impurity region 3, boron ion implantation is performed, and the p-type impurity region 3 is formed immediately below the charge transfer portion.
Is formed, and phosphorus is ion-implanted in the same manner to form an n-type impurity region 4 which is a charge transfer portion.

Next, after removing the photoresist, an insulating film 8a under the gate, for example, Sin having a film thickness of 350 Å or SiO ₂ having a film thickness of 600 Å is formed on the silicon substrate 1, and the n-type impurity region 4 is formed. A p ⁺ type impurity region 5 is formed by opening a window of a p ⁺ type impurity region pattern using a photoresist (not shown) on the insulating film 8a on a predetermined region and performing ion implantation.

Next, after removing the photoresist, polysilicon is deposited to a film thickness of about 4500Å, a gate pattern is formed using the photoresist, and etching is performed to form a polysilicon layer 9 to be the first-layer transfer electrode. .

Next, after removing the photoresist, the insulating film 8a is entirely removed using the polysilicon layer 9 as a mask, and an insulating film 8b having a uniform film thickness of, for example, about 1100Å is formed on the silicon substrate 1 again.

Next, the pattern of the n-type impurity region 6 is formed by a photoresist (not shown) so that the polysilicon layer 9 and one side of the insulating film 10 on the polysilicon layer 9 serve as a mask, The ion implantation of phosphorus has an acceleration energy of 20 to 60 keV and a dose of 10 ¹³ to 10 ¹⁵ cm.
Self-aligned under the condition of ^-2 , and n-type impurity region 6
Are formed (FIG. 7A).

Next, after removing the photoresist, boron ions are self-aligned so that the polysilicon layer 9 and the insulating film 10 on the polysilicon layer 9 are used as a mask to p-type the surface of the n-type impurity region 6. ^{A +} type impurity region 7a is formed (FIG. 7B).

Next, window patterning is performed on the photoresist 30 at a position away from the polysilicon layer 9 (see FIG. 7).
(C)) Next, ion implantation is performed to form ap ⁺ -type impurity region 7b at the center of the p ⁺ -type impurity region 7a (FIG. 7D). The ion implantation conditions may be the same as when forming the p ⁺ -type impurity region 7a.

Next, the manufacturing process of the solid-state image pickup device of the second embodiment of the present invention will be described with reference to FIG.

First, after a step similar to that of FIG.
(A)) After forming the p ⁺ -type impurity region 7a, an insulating film 31, for example, SiO ₂ is deposited to a film thickness of 2000 to 8000Å (FIG. 8B).

Next, etch back is performed to form sidewalls 31 (FIG. 8C), ion implantation is performed, and p is performed.
^{A +} type impurity region 7b is formed (FIG. 8D). The conditions for ion implantation may be the same as in the first embodiment.

FIG. 9 is an impurity concentration distribution diagram in the depth direction of the silicon substrate in the central portion and the peripheral portion of the photoelectric conversion portion in this embodiment. In the photoelectric conversion portion, the impurity of the p ⁺ -type impurity region in the peripheral portion is formed. It is shown that the concentration is lowered from the central portion to solve the problem that the signal charge storage capacity of the photoelectric conversion portion is reduced by the two-dimensional effect, which is the object of the present invention.

FIG. 10 is a diagram showing the depletion potential characteristics of the photoelectric conversion part with respect to the ion implantation amount when forming the p ⁺ type impurity regions 7a and 7b and the n type impurity region 6 in the photoelectric conversion part 14. is there. According to FIG. 10, p
^{When the +} type impurity regions 7a and 7b are formed, the change amount of the depletion potential of the light receiving portion with respect to the relative implantation amount is smaller than when the n type impurity region 6 is formed.
^The potential controllability is good because the influence of the ion implantation upon forming the ⁺ type impurity regions 7a and 7b on the potential of the photoelectric conversion portion can be made relatively small.

[0038]

As described above in detail, by using the present invention, the higher the concentration of the p-type impurity region forming the photoelectric conversion part is, the more the n-type impurity region below the p-type impurity region is formed. The effect of canceling the concentration is strengthened, and there is an action of lowering the depletion potential of the n-type impurity region. Therefore, in the present invention, the potential of each photoelectric conversion portion is shallow in the central portion and deep in the peripheral portion.

Then, by controlling the concentration of the p ⁺ -type impurity region as in the present invention, the influence on the potential distribution of the photoelectric conversion portion is compared with the case where the potential distribution is controlled by the conventional n-type impurity region. Since it can be made extremely small, the potential controllability is good.

Further, in forming the p ⁺ -type impurity region having the two-stage concentration distribution in the present invention, the second ion implantation may be aligned with the central portion of the p ⁺ -type impurity region formed by the first ion implantation. Therefore, the alignment accuracy between the two may be loose.

From the above, by optimizing the effect that the potential of each photoelectric conversion portion becomes deeper in the peripheral portion, the effect that the potential of each photoelectric conversion portion becomes shallower in the peripheral portion due to the two-dimensional effect when the pixel size is reduced. It is possible to completely cancel it. Therefore, as a result of the signal storage being spread over the entire photoelectric conversion unit, the maximum signal storage capacity of the photoelectric conversion unit is significantly increased. In addition, the method for realizing it is easy and its practical value is extremely large.

[Brief description of drawings]

1A is a plan view of a solid-state imaging device according to an embodiment of the present invention, FIG. 1B is a sectional view taken along the line I-I ′ in FIG. 1A, and FIG.
FIG. 11 is a sectional view taken along line II-II ′ in FIG.

FIG. 2A is a sectional view of a pixel corresponding to the potential distribution of the present invention, and FIGS. 2B and 2C are potential distribution diagrams during charge accumulation and charge transfer.

3A is a plan view of a conventional interline transfer type solid-state imaging device, FIG. 3B is a sectional view taken along the line I-I ′ in FIG. 3A, and FIG. 3C is a line II-II ′ in FIG. FIG.

FIG. 4 is a diagram showing operation timing of a conventional solid-state imaging device.

5A is a cross-sectional view taken along the line I-I ′ in FIG.
(B) the potential distribution diagram when the clock is a transfer operation with _{V L, V H, (c} ) if you are a charge accumulated in the photoelectric conversion unit and the readout operation of the CCD transfer unit FIG. 3 is a potential distribution map of FIG.

FIG. 6A is a pixel plan view of a conventional solid-state imaging device,
(B) is a cross-sectional view taken along the line Ib-Ib 'in (a), and (c) is a potential distribution diagram in (b).

FIG. 7 is a manufacturing process diagram of the solid-state imaging device according to the first embodiment of the present invention.

FIG. 8 is a manufacturing process diagram of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 9 is a distribution diagram of impurity concentration in the central portion and the peripheral portion of the photoelectric conversion portion in the depth direction of the silicon substrate in the present embodiment.

FIG. 10 is a diagram showing a depletion potential characteristic of a photoelectric conversion unit with respect to an ion implantation amount when forming ap ⁺ type impurity region and an n type impurity region in the photoelectric conversion unit.

[Explanation of symbols]

1 n-type silicon substrate 2 p ^- type well region 3 p-type impurity region 4 n-type impurity region 5 p ⁺ -type impurity region 6 n-type impurity region 7a, 7b p ⁺ -type impurity region 8a, 8b, 10, 31 insulating film 9 , 11 polysilicon layer 13 CCD transfer part 14 photoelectric conversion part 15 transfer gate region 16, 17, 18, 19 transfer electrode 30 photoresist

Claims (1)

[Claims] 1. A surface of a first-conductivity-type semiconductor region comprises a plurality of first-conductivity-type first impurity regions and a second-conductivity-type second impurity region formed under the first impurity regions. A solid-state imaging device having a photoelectric conversion part formed therein, wherein the impurity concentration of the first impurity region is lower in the peripheral portion than in the central portion.