JP3723124B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pixel structure of a solid-state imaging device, and more particularly to a photodiode included in a pixel and a peripheral structure thereof.
[0002]
[Prior art]
The solid-state imaging device has a pixel array that converts incident optical image information into an electrical signal. The pixel array is configured in units of pixels. The pixel has a photodiode for converting incident light into an electric signal and storing the electric signal for a certain period. The photodiode is formed on a p-type semiconductor substrate. The photodiode has an n-type semiconductor layer that is formed inside the substrate and stores photoelectrons that are electrical signals, and a p-type semiconductor layer provided on the surface of the substrate above the n-type semiconductor layer. The p-type semiconductor layer suppresses dark current generated on the substrate surface.
[0003]
In addition, the pixel has a transfer transistor that reads the stored electrical signal. This transfer transistor has a read gate and a signal detector.
[0004]
At the time of signal readout, a positive potential is applied to the readout gate, thereby increasing the potential of the channel below the readout gate. Therefore, the signal electrons accumulated in the photodiode flow out to the signal detector through this channel and are read out.
[0005]
However, in the structure of the conventional solid-state imaging device, thermal noise may occur. Therefore, there was a problem that the S / N of the playback screen deteriorated. In addition, there is a problem that dark current noise may occur despite the presence of the p-type semiconductor layer.
[0006]
[Problems to be solved by the invention]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device in which thermal noise and dark current noise are unlikely to occur and the S / N of a reproduction screen is unlikely to deteriorate. There is.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is characterized in that a first conductivity type semiconductor substrate,
A first semiconductor region of a second conductivity type provided inside the substrate apart from the surface of the substrate;
A second semiconductor region of a second conductivity type provided on the substrate including the surface of the substrate and provided apart above the first semiconductor region;
An insulating film provided on the second semiconductor region;
A conductor provided on the insulating film;
A first conductivity type provided on a substrate including a surface of the substrate, wherein a lower surface is in contact with an upper surface of the first semiconductor region, a side surface is in contact with a side surface of the second semiconductor region, and a distance from the conductor is equal to or greater than a film thickness of the insulating film. A third semiconductor region of
A solid-state imaging device including a fourth semiconductor region of a second conductivity type provided on a substrate including a surface of the substrate and having a side surface in contact with a side surface of the second semiconductor region and a distance from the conductor equal to a film thickness of the insulating film is there.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from the actual ones. Of course, parts having different dimensional relationships and ratios are included between the drawings.
[0009]
(First embodiment)
As shown in FIG. 1A, the solid-state imaging device according to the first embodiment sequentially reads out a pixel array 2 that converts incident optical image information into an electrical signal, and signals accumulated in the pixel array 2. A signal scanning circuit 3 for sending a control signal to the pixel array 2 and a signal reading circuit 4 for sequentially reading the signals read from the pixel array 3 out of the solid-state imaging device. The pixel array 2 has pixels 5 which are unit cells arranged in a two-dimensional array.
[0010]
As shown in FIG. 1B, the pixel 5 includes a photodiode PD for converting incident light into an electric signal and accumulating the electric signal for a certain period. Furthermore, the row selection transistor FET4 for selectively reading the electrical signal of the photodiode PD, the amplification transistor FET3 for amplifying the electrical signal, the reset transistor FET2 for resetting the electrical signal, and the electrical power of the photodiode PD. It comprises a transfer transistor FET1 for outputting a signal to a gate electrode serving as an input of the amplification transistor FET3 and reading out an electric signal. The photodiode PD has a signal storage unit 13 provided in the p-type semiconductor substrate 11. The transfer transistor FET1 has a read gate provided above the substrate 11.
[0011]
The structure of the pixel 5 is shown in more detail in FIGS. 2 and 3 (a). FIG. 3A is a cross-sectional view in the II direction of FIG. The pixel 5 has a first conductivity type semiconductor substrate 11 or a first conductivity type well provided on the substrate 11. The first conductivity type first semiconductor region 13 is provided in the substrate 11 away from the surface of the substrate 11. The first conductivity type may be p-type or n-type. When the first conductivity type is p-type, the second conductivity type is n-type. When the first conductivity type is n-type, the second conductivity type is p-type. The insulating film 15 is provided on the substrate 11. The conductor 16 is provided on the insulating film 15. The third semiconductor region 18 of the first conductivity type is provided on the substrate 11 including the surface of the substrate 11. The lower surface of the third semiconductor region 18 is in contact with the upper surface of the first semiconductor region 13. The distance between the third semiconductor region 18 and the conductor 16 is equal to the film thickness of the insulating film 15. The second conductive type fourth semiconductor region 14 is provided in the substrate 11 including the surface of the substrate 11, and the distance from the conductor 16 is equal to the film thickness of the insulating film 15. The insulator 12 has a lower surface provided below the surface of the substrate 11, and a side surface and a lower surface are in contact with the third semiconductor region 18. A p-type well (p-well) 11 is provided on the substrate 11. The first semiconductor region 13 is an n-type semiconductor layer that accumulates photoelectrons. The third semiconductor region 18 is a p-type semiconductor layer provided on the surface of the photodiode PD. The fourth semiconductor region 14 is an n-type semiconductor layer that detects signal electrons read from the photodiode PD. The third semiconductor region suppresses dark current generated on the surface of the substrate 11. The conductor 16 is a gate electrode of the FET 1. The conductor 21 is a gate electrode of the FET 2. The conductor 20 is a gate electrode of the FET 3. The conductor 19 is a gate electrode of the FET 4. The surface of the substrate 11 without the insulator 12 is an active region 17.
[0012]
FIG. 3B is a potential distribution diagram during electrical signal accumulation between I and I in FIG. FIG. 3C is a potential distribution diagram when reading an electric signal. At the time of electrical signal accumulation, as shown in FIG. 3B, a reference potential is applied to the read gate 16, and the potential of the channel below the read gate 16 is low. For this reason, the signal electrons 24 are accumulated in the first semiconductor region 13 of the photodiode PD without leaking. At the time of signal readout, as shown in FIG. 3C, a positive potential is applied to the readout gate 16, thereby increasing the potential of the channel below the readout gate 16. Therefore, the signal electrons 24 accumulated in the first semiconductor region 13 of the photodiode PD flow out to the fourth semiconductor region 14 which is a signal detection unit through the channel of the read gate 16, and an electric signal is read out.
[0013]
However, in the structure of the pixel 5 in FIG. 3A, thermal noise and dark current noise may occur.
[0014]
The third semiconductor region 18 is connected to the reference voltage and fixed at the reference potential. For this reason, it is difficult to raise the potential of the photodiode PD threshold channel of the read gate 16 when the read gate 16 is in the ON state. Further, as the pixel 5 is further miniaturized, the power supply voltage is lowered accordingly, so that the voltage applied to the read gate is lowered. This also makes it difficult to sufficiently raise the channel potential when the read gate is in the on state. Since the channel potential cannot be raised sufficiently during reading, electrons 24 remain in the photodiode PD. Residual electrons 24 are considered to cause thermal noise. Then, it is considered that the S / N ratio of the reproduction screen is deteriorated due to the thermal noise. This indicates that it becomes difficult to achieve both low dark current and low thermal noise as the pixels become finer.
[0015]
The read gate 16 is made of polycrystalline silicon or a silicide material. As a result, local stress is generated at the end of the read gate 16. This stress may induce carrier generation levels that are sources of dark current on the surface of the silicon substrate 11. Electrons generated from the carrier generation level flow into the first semiconductor region 13 which is a signal storage portion during the signal storage period. It is considered that dark current noise is generated by the inflow of electrons.
[0016]
(Example 1 of the first embodiment)
The structure of the pixel 5 according to Example 1 of the first embodiment is shown in FIG. 4 and FIG. Fig.5 (a) is sectional drawing of the II direction of FIG. The pixel 5 has a first conductivity type semiconductor substrate 11. The first conductivity type first semiconductor region 13 is provided in the substrate 11 away from the surface of the substrate 11. The second semiconductor region 22 of the second conductivity type is provided in the substrate 11 including the surface of the substrate 11, and is provided above the first semiconductor region 13. The insulating film 15 is provided on the second semiconductor region 22. The conductor 16 is provided on the insulating film 15. The third semiconductor region 18 of the first conductivity type is provided on the substrate 11 including the surface of the substrate 11. The lower surface of the third semiconductor region 18 is in contact with the upper surface of the first semiconductor region 13, and the side surface of the third semiconductor region 18 is in contact with the side surface of the second semiconductor region 22. The distance between the third semiconductor region 18 and the conductor 16 is larger than the film thickness of the insulating film 15. The second conductivity type fourth semiconductor region 14 is provided on the substrate 11 including the surface of the substrate 11. The side surface of the fourth semiconductor region 14 is in contact with the side surface of the second semiconductor region 22. The distance between the fourth semiconductor region 14 and the conductor 16 is equal to the film thickness of the insulating film 15. The lower surface of the insulator 12 is provided below the surface of the substrate 11. The side surface and the lower surface of the insulator 12 are in contact with the third semiconductor region 18. The first semiconductor region 13 is a signal storage portion of the photodiode PD that stores signal charges obtained by photoelectric conversion. The conductor 16 is a gate electrode of the field effect transistor FET1 that discharges signal charges from the signal storage unit. The second semiconductor region 22 is a channel region of the transistor FET1. The fourth semiconductor region 14 is a drain region of the FET 1 and is a signal detection unit that detects signal charges.
[0017]
The second semiconductor region 22 is an n-type diffusion layer provided in the channel region of the read gate 16. Further, the third semiconductor region 18 and the read gate 16 are offset by the offset distance X. The reason why the offset is provided is as follows. A local stress is generated at the end portion of the read gate 16 made of polycrystalline silicon or silicide material. This stress easily induces a carrier generation level that becomes a dark current generation source at the interface of the silicon substrate 11. The second semiconductor region 22 provided under the read gate 16 extends from the read gate 16 toward the third semiconductor region 18 by a distance X. Dark current electrons generated from the generation level do not flow into the signal storage layer 13 of the photodiode PD during the signal storage period. Dark current electrons flow out to the signal detector 14 through the second semiconductor region. For this reason, no noise is generated on the playback screen.
[0018]
FIG. 5B is a potential distribution diagram during electrical signal accumulation between I and I in FIG. FIG. 5C is a potential distribution diagram when reading an electric signal. At the time of electrical signal accumulation, as shown in FIG. 5B, signal electrons are stored in the storage layer 13 with the potential of the region of the p-type semiconductor substrate 11 sandwiched between the storage layer 13 and the read channel 22 as a barrier. .
[0019]
At the time of signal readout, as shown in FIG. 5C, a positive potential is applied to the readout gate 16, thereby increasing the potential of the channel 22 below the readout gate 16. The potential of the region of the p-type semiconductor substrate 11 sandwiched between the region 13 and the region 22 increases accordingly, and all signal electrons in the signal storage unit 13 are read out to the signal detection unit 14. Accordingly, there are no residual electrons, and noise such as thermal noise and afterimage does not occur.
[0020]
As described above, the signal storage unit 13 and the readout channel 22 of the same conductivity type are formed under the readout gate 16 so as to overlap in the depth direction so as to sandwich the region of the substrate 11 of a different conductivity type. . This makes it possible to easily modulate the potential of the substrate 11 sandwiched between the regions 13 and 22 when the read gate 16 is in the ON state. Signals can be read at a lower read voltage than in the past. For this reason, even if the pixels are miniaturized and the power supply voltage is lowered, there is no occurrence of noise such as thermal noise and afterimage as in the prior art. A clear image with little noise can be obtained on the playback screen. In addition, since the channel 22 of the read gate 16 extends to a position away from the read gate electrode 16 by a predetermined distance X, dark current generated at the gate 16 gate flows into the signal storage unit 13 during the signal storage period. There is no. Therefore, dark current noise is greatly suppressed, and a clear image with little noise can be obtained on the reproduction screen.
[0021]
(Modification 1 of Example 1 of the first embodiment)
As shown in FIG. 6A, the pixel 5 of the solid-state imaging device 1 according to the first modification of the first embodiment of the first embodiment has a structure similar to that in FIG. Further, the depth from the surface of the substrate 11 to the upper surface of the first semiconductor region 13 is deeper than the depth from the surface of the substrate 11 to the lower surface of the insulator 12. The depth from the surface of the substrate 11 to the lower surface of the third semiconductor region 18 in contact with the upper surface of the first semiconductor region 13 is deeper than the depth from the surface of the substrate 11 to the lower surface of the insulator 12. The formation depth of the third semiconductor region 18 which is a p-type semiconductor layer on the surface of the photodiode PD is formed so as to cover the lower end of the insulator 12 of the silicon oxide (SiO2) layer which is an element isolation region. This can more reliably prevent dark current generated on the surface of the substrate 11 from being injected into the first semiconductor region 13.
[0022]
Further, the thickness of the second semiconductor region 22 is also increased. By increasing the thickness, the distance between the lower surface of the second semiconductor region 22 and the upper surface of the first semiconductor region 13 is made equal in FIGS. 5 (a) and 6 (a). This eliminates the need to increase the modulation potential applied to the gate 16.
[0023]
(Modification 2 of Example 1 of the first embodiment)
As shown in FIG. 6B, the pixel 5 of the solid-state imaging device 1 according to Modification 2 of Example 1 of the first embodiment has a structure similar to that shown in FIGS. In addition, a first semiconductor region 13 is provided below the insulator 12. A first semiconductor region 13 of an n-type semiconductor layer that is a signal storage layer is formed below the insulator 12 in the element isolation region. As a result, the light receiving area of the photodiode PD can be increased, and the sensitivity of the photodiode PD is improved.
[0024]
(Example 2 of the first embodiment)
As shown in FIG. 7A, the pixel 5 of the solid-state imaging device 1 according to Example 2 of the first embodiment not only has the same structure as that in FIG. A conductive fifth semiconductor region 26 is provided above the first semiconductor region 13 and below the second semiconductor region 22. A fifth semiconductor region 26 of a p-type semiconductor layer is provided in a region above the first semiconductor region 13 of the signal storage region under the second semiconductor region 22 of the n-type semiconductor layer serving as a channel of the read gate 16. . The impurity concentration of the substrate 11 is 10 ¹⁵ -10 ¹⁶ cm ^-3 Degree. The impurity concentration of the first semiconductor region 13 is 10 ¹⁶ -10 ¹⁷ cm ^-3 Degree. The impurity concentration of the first semiconductor region 13 is 10 ¹⁶ -10 ¹⁷ cm ^-3 Degree. The impurity concentration of the second semiconductor region 22 is 10 ¹⁶ -10 ¹⁷ cm ^-3 Degree. The impurity concentration of the third semiconductor region 18 is 10 ¹⁸ -10 ¹⁹ cm ^-3 Degree. The impurity concentration of the fourth semiconductor region 14 is 10 ¹⁹ -10 ²⁰ cm ^-3 Degree. The impurity concentration of the fifth semiconductor region 26 is 10 ¹⁶ -10 ¹⁷ cm ^-3 Degree.
[0025]
With such a structure, the potential barrier between the signal storage region 13 and the read channel 22 is increased, and the number of electrons stored in the signal storage region 13 can be increased. FIG. 7B is a potential distribution diagram of a path between I and I in FIG. FIG. 7C is a potential distribution diagram of a path between II and II in FIG. As shown in FIG. 7B, the dark current 27 generated at the edge of the read gate 16 is discharged to the signal detector 14 through the read channel 22. As shown in FIG. 7C, the dark current 27 generated at the gate of the gate 16 during the signal accumulation period has a potential of the fifth semiconductor region 26 of the p-type semiconductor layer sandwiched between the signal accumulation region 13 and the channel 22. It becomes a potential barrier against the signal electrons and does not flow into the signal storage region 13.
[0026]
(Modification 1 of Example 2 of the first embodiment)
As shown in FIG. 8A, the pixel 5 of the solid-state imaging device 1 according to the first modification of the second example of the first embodiment has a structure similar to that in FIG. Further, the depth from the surface of the substrate 11 to the upper surface of the first semiconductor region 13 is deeper than the depth from the surface of the substrate 11 to the lower surface of the insulator 12. This can more reliably prevent dark current generated on the surface of the substrate 11 from being injected into the first semiconductor region 13.
[0027]
(Modification 2 of Example 2 of the first embodiment)
As shown in FIG. 8B, the pixel 5 of the solid-state imaging device 1 according to the second modification of the second embodiment of the first embodiment has the same structure as that of FIGS. 7A and 8A. In addition, a first semiconductor region 13 is provided below the insulator 12. As a result, the light receiving area of the photodiode PD can be increased.
[0028]
(Example 3 of the first embodiment)
The structure of the pixel 5 of the solid-state imaging device 1 according to Example 3 of the first embodiment is shown in FIGS. 9 (a) and 9 (b). FIG. 9B is a cross-sectional view in the II direction of FIG. The pixel 5 of the solid-state imaging device 1 according to Example 3 of the first embodiment is different from the first example in that the distance between the third semiconductor region 18 and the conductor 16 is equal to the film thickness of the insulating film 15. This is different from the first embodiment. The third semiconductor region 18 that is a p-type semiconductor layer is formed in a self-aligned manner with no offset with respect to the read gate 16. Also by this, the dark current generated at the gate of the gate 16 is injected into the signal detector 14 due to the potential distribution gradient of the p-type semiconductor region of the third semiconductor region 18 as shown in FIG. 7B. .
[0029]
(Modification 1 of Example 3 of the first embodiment)
As shown in FIG. 10A, the pixel 5 of the solid-state imaging device 1 according to Modification 1 of Example 3 of the first embodiment not only has a structure similar to that in FIG. Further, the depth from the surface of the substrate 11 to the upper surface of the first semiconductor region 13 is deeper than the depth from the surface of the substrate 11 to the lower surface of the insulator 12. This can more reliably prevent dark current generated on the surface of the substrate 11 from being injected into the first semiconductor region 13.
[0030]
(Modification 2 of Example 3 of the first embodiment)
As shown in FIG. 10B, the pixel 5 of the solid-state imaging device 1 according to Modification 2 of Example 3 of the first embodiment has the same structure as that of FIGS. 9B and 10A. In addition, a first semiconductor region 13 is provided below the insulator 12. As a result, the light receiving area of the photodiode PD can be increased.
[0031]
(Example 4 of the first embodiment)
The structure of the pixel 5 of the solid-state imaging device 1 according to Example 4 of the first embodiment is shown in FIG. 11A and FIG. FIG.11 (b) is sectional drawing of the II direction of Fig.11 (a). In the pixel 5 of the solid-state imaging device 1 according to Example 4 of the first embodiment, the offset distance Y of the offset of the first semiconductor region 13 with respect to the third semiconductor region 18 is shorter than the offset distance X. This is different from Example 1 of the embodiment. Also by this, it is considered that signal electrons can be easily injected into the channel 22.
[0032]
(Modification 1 of Example 4 of the first embodiment)
As shown in FIG. 12A, the pixel 5 of the solid-state imaging device 1 according to Modification 1 of Example 4 of the first embodiment not only has a structure similar to that in FIG. Further, the depth from the surface of the substrate 11 to the upper surface of the first semiconductor region 13 is deeper than the depth from the surface of the substrate 11 to the lower surface of the insulator 12. This can more reliably prevent dark current generated on the surface of the substrate 11 from being injected into the first semiconductor region 13.
[0033]
(Modification 2 of Example 4 of the first embodiment)
As shown in FIG. 12B, the pixel 5 of the solid-state imaging device 1 according to the second modification of the fourth example of the first embodiment has the same structure as that of FIGS. 11B and 12A. In addition, a first semiconductor region 13 is provided below the insulator 12. As a result, the light receiving area of the photodiode PD can be increased.
[0034]
(Second Embodiment)
The solid-state imaging device 1 has been increased in number of pixels, the imaging system has been downsized, and the imaging module has been downsized. There is an increasing demand for downsizing the size of the pixels 5. In the future, in order to perform photoelectric conversion effectively in a pixel whose area is further reduced, it is required that a structure that blocks or reflects light is not present in the light incident path as much as possible. Furthermore, in order to improve the signal / noise (S / N) ratio, it is necessary to minimize the number of electrons generated in the silicon (Si) substrate 11 even when no incident light is present. Since the generation of electrons varies with time, it becomes a noise component that causes unevenness in the image. Furthermore, there is a demand for reduction of afterimages at a low voltage.
[0035]
In the first embodiment, the gate length is constant in the shape of the gate 16 of the transfer transistor FET1 that controls the transfer of signal charges. As a result, light is also applied to portions that do not necessarily contribute to the accumulation and transfer of signal charges.
[0036]
In the second embodiment, the S / N ratio is improved, complete transfer is possible at a low voltage, and the light incident path is expanded. In order to transfer and store charges at a low voltage, an appropriate gate length is required. That is, paying attention to the potential distribution of the charge accumulating portion 13, only the portion of the gate 16 necessary for charge accumulation / transfer is provided with a protruding convex portion. The gate length of other portions of the gate 16 is made as short as possible. By these things, a light incident path can be expanded.
[0037]
(Example 1 of the second embodiment)
The structure of the pixel 5 of the solid-state imaging device 1 according to Example 1 of the second embodiment is shown in FIGS. 13 and 14A to 14D. FIG. 14B is a cross-sectional view in the II direction of FIGS. 13 and 14A. FIG.14 (c) is sectional drawing of the II-II direction of FIG. 13 and FIG. 14 (a). FIG.14 (d) is sectional drawing of the III-III direction of Fig.14 (a). The pixel 5 has a first conductivity type semiconductor substrate 11. The first conductivity type first semiconductor region 13 is provided in the substrate 11 away from the surface of the substrate 11. The insulating film 15 is provided on the surface of the substrate 11. The conductor 16 is provided on the insulating film 15. A convex portion 28 of the conductor 16 is provided above the first semiconductor region 13. The third semiconductor region 18 of the first conductivity type is provided on the substrate 11 including the surface of the substrate 11. The third semiconductor region 18 is provided above the first semiconductor region 13. The third semiconductor region 18 is in contact with the side surface of the first semiconductor region 13. The third semiconductor region 18 is provided below the conductor 16. The second conductivity type fourth semiconductor region 14 is provided on the substrate 11 including the surface of the substrate 11. The distance between the fourth semiconductor region 14 and the conductor 16 is equal to the film thickness of the insulating film 15. The sixth semiconductor region 29 is provided below the fourth semiconductor region 14. The sixth semiconductor region 29 prevents punch-through. The second conductivity type second semiconductor region 39 is provided on the substrate 11 including the surface of the substrate 11. The second semiconductor region 39 is provided below the conductor 16, and in particular, below the convex portion 28 of the conductor 16. The second semiconductor region 39 contacts the side surface of the third semiconductor region 18 and also contacts the side surface of the fourth semiconductor region. The lower surface of the insulator 12 is provided below the surface of the substrate 11. Side surfaces and a lower surface of the insulator 12 are in contact with the third semiconductor region 18. The first semiconductor region 13 is a signal storage unit that stores the signal electrons 24 obtained by photoelectric conversion. The conductor 16 is a gate electrode of the field effect transistor FET1 that discharges signal electrons from the signal storage unit 13. The second semiconductor region 39 is a channel region of the transistor FET1. In the conductor 16 that is a gate electrode, the convex portion 28 has the maximum gate length. The convex part 28 is a protrusion. In the conductor 16 that is a gate electrode, the convex portion 28 of the conductor 16 is provided in the center of the section that defines the gate width. The third semiconductor region 18 is provided below the convex portion 28. Note that the side surface of the third semiconductor region 18 may be disposed below the side surface of the convex portion 28.
[0038]
FIG. 14E is a potential distribution diagram during electrical signal accumulation between IV and IV in FIG. In the peripheral portion of the first semiconductor region 13 where the third semiconductor region 18 is joined, the potential 23 has a gradient. Due to this gradient, the signal electrons 31 move in the direction of the arrow 36. The signal electrons 31 are collected at the center of the first semiconductor region.
[0039]
In the pixel 5 of the solid-state imaging device 1 according to Example 1 of the second embodiment, the third semiconductor region 18 that becomes the surface shield layer (PDp) of the photodiode PD includes the gate electrode 16, in particular, the gate electrode 16. Is provided below the convex portion 28. As a result, the depletion layer of the first semiconductor region 13 of the signal storage portion (PDn) is in contact with the damaged layer generated by reactive ion etching (RIE) or the like in the dry etching process such as when the gate electrode 16 is formed. Disappears. An increase in local leakage current caused by the damaged layer, so-called white scratches can be prevented. Furthermore, the occurrence of unevenness in the dark can be reduced.
[0040]
Regarding the reading of the signal charge, the signal storage unit 13 and the surface shield layer 18 are offset below the convex portion 28, and the gate electrodes 16 and 28 are disposed above the signal storage unit 13 without the surface shield layer 18 interposed therebetween. Therefore, complete transfer of signal electrons to the signal detector 14 is possible.
[0041]
A method for manufacturing the solid-state imaging device 1 according to Example 1 of the second embodiment will be described. FIG. 15A is a top view of a part of the pixel 5 of the solid-state imaging device 1. FIGS. 15B to 15F are cross-sectional views in the II direction of FIG.
[0042]
First, as shown in FIG. 15B, an LOCOS or STI insulator 12 for element isolation is formed inside the silicon substrate 11. Next, a p-type semiconductor layer 33 for element isolation is formed. A signal storage region 13 is formed by ion implantation.
[0043]
Next, as shown in FIG. 15C, the surface shield layer 34 is formed. By forming the p-type semiconductor layer 33 and the surface shield layer 34, the third semiconductor region 18 is completed. Thereafter, a process such as annealing may be performed. Further, a channel implantation layer 39 is formed. In parallel, ion implantation is performed to control element isolation regions and transistor threshold values that constitute the transistors of the peripheral circuit.
[0044]
As shown in FIG. 15D, a gate insulating film 15 and a gate electrode 16 or a gate wiring are formed.
[0045]
As shown in FIG. 15E, the detection unit 14 and the source / drain regions of the peripheral circuit are formed.
[0046]
As shown in FIG. 15F, the punch-through prevention region 29 is formed.
[0047]
By this manufacturing method, the signal accumulation / transfer regions 13 and 39 can be formed under the gate electrode 16. Furthermore, a surface shield layer 34 that prevents depletion of the silicon surface can be formed under the gate electrode 16.
[0048]
In addition, the protrusion of the convex part 28 is also formed in the gate electrode 16 when the gate electrode 16 is formed. The convex portion 28 is formed on the movement path for reading signal electrons. And this convex part 28 may be formed thickly as it goes to the moving direction of the reading of signal electrons.
[0049]
The surface shield layer 34 may be formed except for a region where the convex portion 28 is formed. The surface shield layer 34 may be formed except for a region serving as a movement path for reading signal electrons. The surface shield layer 34 may be formed so that the width of the surface shield layer 34 not to be formed increases toward the charge transfer path direction of the read path and the opening area increases in the direction of the detection unit 14.
[0050]
(Modification of Example 1 of the second embodiment)
As shown in FIGS. 16A and 16B, the pixel 5 of the solid-state imaging device 1 according to the modification of Example 1 of the second embodiment has a structure similar to that shown in FIGS. In addition, a lens 35 is provided. The optical axis of the lens 35 coincides with a perpendicular L7 to the substrate surface passing through the center C point of the region excluding the region below the convex portion 28 from the first semiconductor region 13. The lens 35 is provided above the third semiconductor regions 33 and 34 (18). As a result, the light incident path can be further expanded.
[0051]
(Example 2 of the second embodiment)
The structure of the pixel 5 of the solid-state imaging device 1 according to Example 2 of the second embodiment is shown in FIGS. FIG. 17B is a cross-sectional view in the II direction of FIG. FIG.17 (c) is sectional drawing of the II-II direction of Fig.17 (a). In the pixel 5 of the solid-state imaging device 1 according to Example 2 of the second embodiment, the distance between the convex portion 28 of the gate 16 and the third semiconductor region 18 is larger than the thickness of the insulating film 15. This is different from Example 1 of the embodiment. Thus, it is considered that signal electrons can be easily injected into the channel 39.
[0052]
In the pixel 5 of Example 2 of the second embodiment, an offset is provided between the surface shield layer 18 and the gate electrode 16. In a region where this offset exists, a second semiconductor region 39 for controlling the threshold value of the read transistor FET1 is provided. The second semiconductor region 39 prevents depletion of the silicon substrate surface in the region where the offset exists. This offset makes it easier to form a movement path when reading signal charges. Even if the voltage applied to the gate 16 is lower, the signal charge can be completely read out. The signal electrons collected along the arrow 36 move to the signal detection unit 14 via the region 39 along the arrow 37.
[0053]
The impurity concentration of the signal storage region 13 is preferably 10 ¹⁶ -10 ¹⁷ cm ^-3 Degree. The diffusion layer depth of the signal storage region 13 is preferably about 0.3 to 1.0 μm. The impurity concentration of the surface shield layer 18 is 10 ¹⁸ cm ^-3 The degree is preferred. The diffusion layer depth of the surface shield layer 18 is preferably about 0.1 to 0.2 μm. The impurity concentration of the channel forming portion 39 is 10 ¹⁷ cm ^-3 The degree is preferred. The thickness of the silicon oxide film of the insulating film 15 is preferably about 80 nm. The offset distance between the surface shield layer 18 and the ends of the gate electrodes 16 and 28 of the read transistor FET1 is preferably about 0.1 to 0.3 μm in the signal transfer path direction 37 and 0.1 to 0.3 μm in the direction perpendicular to the signal transfer path. It is. The length of the convex portion 28 of the read transistor FET1 is preferably about 0.3 μm. The width of the convex portion 28 is about 0.4 μm. The opening end of the surface shield layer 18 and the ends of the gate electrodes 16 and 28 of the read transistor FET1 are planar distances from above, and preferably about 0.1 to 0.3 μm. The ion implantation of the signal storage unit 13 is, for example, the impurity is phosphorus (P), the acceleration voltage is 320 kV, and the dose amount is 1.35 × 10. ¹² cm ^-2 To the extent. The ion implantation of the region 34 of the surface shield layer 18 is, for example, that the impurity is boron (B), the acceleration voltage is 15 kV, and the dose is 1.0 × 10. ¹³ cm ^-2 Done as a degree. The ion implantation of the region 39 that determines the channel threshold is, for example, boron as an impurity, an acceleration voltage of 15 kV, and a dose of 2.0 × 10. ¹² cm ^-2 Degree. The ion implantation of the element isolation region 33 of the surface shield layer 18 is, for example, boron as an impurity, an acceleration voltage of 140 kV, and a dose amount of 5.0 × 10. ¹² cm ^-2 In addition, the impurity is boron, the acceleration voltage is 80 kV, and the dose is 7.0 × 10. ¹² cm ^-2 Degree.
[0054]
FIG. 18A is a potential distribution diagram during electrical signal accumulation between III and III in FIG. FIG. 18B is a potential distribution diagram at the time of reading an electric signal between III and III in FIG. FIG. 18C is a potential distribution diagram during electrical signal accumulation between IV and IV in FIG. FIG. 18D is a potential distribution diagram at the time of reading an electric signal between IV and IV in FIG.
[0055]
At the time of signal accumulation, as shown in FIG. 18A, signal electrons are stored in the storage layer 13 with the potential of the region of the p-type semiconductor substrate 11 sandwiched between the storage layer 13 and the read channel 39 as a barrier. As shown in FIG. 18C, signal electrons generated in the peripheral portion of the storage layer 13 move to the central portion of the storage layer 13 and are stored. Signal electrons are unlikely to exist in the periphery.
[0056]
At the time of signal readout, as shown in FIG. 18B, a positive potential is applied to the readout gate 16, thereby increasing the potential of the channel 39 below the readout gate 16. The potential of the region of the p-type semiconductor substrate 11 sandwiched between the region 13 and the region 39 increases accordingly, and all the signal electrons in the signal storage unit 13 are read out to the signal detection unit 14 in the direction of arrow 37. A readout path for signal electrons is generated. Since there are no residual electrons, no noise such as thermal noise or afterimage occurs. As shown in FIG. 18D, the signal electrons generated in the peripheral part of the storage layer 13 have moved to the central part of the storage layer 13, and the signal electrons are unlikely to exist in the peripheral part. An electronic readout path is unlikely to exist.
[0057]
(Modification 1 of Example 2 of the second embodiment)
The pixel 5 of the solid-state imaging device 1 according to Modification 1 of Example 2 of the second embodiment has the same structure as that shown in FIGS. 17A to 17C, but as shown in FIG. Further, the shapes of the third semiconductor region 18 and the second semiconductor region 39 are different.
[0058]
The pixel 5 of the solid-state imaging device 1 according to the first modification of the second embodiment of the second embodiment has a surface shield layer in the direction of the signal readout path 37 and from the signal accumulation region 13 to the gate electrode 16. The width of the 18 openings is widened. Since the opening width of the surface shield layer 18 increases along the read path 37, the potential of the signal read path 37 becomes deeper as the distance from the signal detection unit 14 becomes closer, and signal charges can be completely transferred at a low gate voltage. is there.
[0059]
(Modification 2 of Example 2 of the second embodiment)
The pixel 5 of the solid-state imaging device 1 according to Modification 2 of Example 2 of the second embodiment has the same structure as that shown in FIGS. 17A to 17C, but as shown in FIG. Further, the shape of the convex portion 28 is different.
[0060]
The pixel 5 of the solid-state imaging device 1 according to the second modification of the second example of the second embodiment includes the readout transistor FET1 in the direction of the signal readout path 37 from the signal storage region 13 toward the gate electrode 16. The width of the convex portion 28 is widened. Since the gate width increases along the signal readout path 37, the modulation from the gate electrode 16 is more likely to be effective in the signal readout path 37 as it approaches the detection unit 14. Signal charges can be completely transferred with a low gate voltage.
[0061]
(Modification 3 of Example 2 of the second embodiment)
The pixel 5 of the solid-state imaging device 1 according to the third modification of the second embodiment of the second embodiment has the same structure as that illustrated in FIGS. 17A to 17C, but as illustrated in FIG. Further, the shapes of the convex portion 28, the third semiconductor region 18 and the second semiconductor region 39 are different.
[0062]
The pixel 5 of the solid-state imaging device 1 according to Modification 3 of Example 2 of the second embodiment includes a surface shield layer in the direction of the signal readout path 37 from the signal accumulation region 13 toward the gate electrode 16. The width of the opening 18 is widened, and the width of the convex portion 28 of the read transistor FET1 is widened. Thereby, the effects of the first and second modifications of the second embodiment of the second embodiment can be obtained together. A complete transfer of signal charge at a lower gate voltage is possible.
[0063]
(Modification 4 of Example 2 of 2nd Embodiment)
The pixel 5 of the solid-state imaging device 1 according to the modified example 4 of the second example of the second embodiment has the same structure as that in FIG. 19A. However, as illustrated in FIG. The semiconductor region 18 and the second semiconductor region 39 have different shapes and have a semicircular shape.
[0064]
The pixel 5 of the solid-state imaging device 1 according to the first modification of the second embodiment of the second embodiment has a surface shield layer in the direction of the signal readout path 37 and from the signal accumulation region 13 to the gate electrode 16. The width of the 18 openings widens, and the opening draws a semicircle. As a result, the same effect as that of Modification 1 of Example 2 of the second embodiment can be obtained. Furthermore, the electric field distribution near the opening becomes uniform, and the occurrence of white scratches can be reduced.
[0065]
(Modification 5 of Example 2 of the second embodiment)
The pixel 5 of the solid-state imaging device 1 according to the modified example 5 of the second embodiment of the second embodiment has the same structure as that in FIG. 19B, but as illustrated in FIG. 28 has a different shape and a semicircular shape.
[0066]
The pixel 5 of the solid-state imaging device 1 according to the modified example 5 of the second example of the second embodiment includes the readout transistor FET1 in the direction of the signal readout path 37 from the signal storage region 13 toward the gate electrode 16. The width of the convex portion 28 is widened, and the convex portion 28 has a semicircular shape. As a result, the same effect as that of the second modification of the second embodiment of the second embodiment can be obtained. Furthermore, the electric field distribution near the opening becomes uniform, and the occurrence of white scratches can be reduced.
[0067]
(Modification 6 of Example 2 of the second embodiment)
The pixel 5 of the solid-state imaging device 1 according to Modification 6 of Example 2 of the second embodiment has the same structure as that in FIG. 19C, but as illustrated in FIG. 28, the shapes of the third semiconductor region 18 and the second semiconductor region 39 are different and each has a semicircular shape.
[0068]
The pixel 5 of the solid-state imaging device 1 according to Modification 6 of Example 2 of the second embodiment includes a surface shield layer in the direction of the signal readout path 37 from the signal accumulation region 13 toward the gate electrode 16. The width of the 18 openings widens and the opening draws a semicircle. The width of the convex portion 28 of the read transistor FET1 is widened, and the convex portion 28 has a semicircular shape. As a result, the same effect as that of Modification 3 of Example 2 of the second embodiment can be obtained. Furthermore, the electric field distribution near the opening becomes uniform, and the occurrence of white scratches can be reduced.
[0069]
(Modification 7 of Example 2 of the second embodiment)
The pixel 5 of the solid-state imaging device 1 according to the modified example 7 of the second example of the second embodiment has the same structure as that illustrated in FIGS. 17A to 17C and FIG. As shown in (b), the position of the opening of the third semiconductor region 18 with respect to the first semiconductor region 13 is different. Similarly, the positions of the convex portions of the second semiconductor region 39 are different. Similarly, the position of the convex portion 28 of the conductor 16 is different. This also provides the same effect as that of Example 2 of the second embodiment.
[0070]
(Modification 8 of Example 2 of the second embodiment)
The pixel 5 of the solid-state imaging device 1 according to the modification 8 of the second embodiment of the second embodiment has the same structure as that illustrated in FIGS. 17A to 17C and FIG. As shown in (c), the position of the opening of the third semiconductor region 18 with respect to the first semiconductor region 13 is different. Similarly, the positions of the convex portions of the second semiconductor region 39 are different. Similarly, the position of the convex portion 28 of the conductor 16 is different. This also provides the same effect as that of Example 2 of the second embodiment.
[0071]
FIG. 22A shows the number of pixels 5 with white scratches with respect to the peripheral length of the gate of the convex portion 28 in the solid-state imaging device 1 according to Example 2 and Modifications 1 to 6 of the second embodiment. is there. From this, it can be seen that white scratches are less likely to occur as the peripheral length of the gate of the convex portion 28 is smaller. Note that when the peripheral length of the gate of the convex portion 28 is set to zero, the solid-state imaging device 1 does not operate.
[0072]
FIG. 22B also shows the number of pixels 5 in which white scratches occur with respect to the gate area of the convex portion 28 in the solid-state imaging device 1 according to Example 2 and Modifications 1 to 6 of the second embodiment. From this, it can be seen that white scratches are less likely to occur as the gate area of the protrusion 28 is smaller. If the gate area of the convex portion 28 is set to zero, the solid-state imaging device 1 does not operate. From the above results, it was found that the shape of the convex portion 28 in which white scratches are difficult to occur is a shape having a small gate peripheral length and a small gate area. That is, the shape of the convex portion 28 is preferably a semicircular shape as shown in FIGS.
[0073]
(Example 3 of the second embodiment)
The structure of the pixel 5 of the solid-state imaging device 1 according to Example 3 of the second embodiment is shown in FIGS. FIG. 23B is a cross-sectional view in the II direction of FIG. FIG.23 (c) is sectional drawing of the II-II direction of Fig.23 (a). The pixel 5 of the solid-state imaging device 1 according to Example 3 of the second embodiment is different from Example 2 of the second embodiment in the structure of the first semiconductor regions 13 and 38. As a result, the signal electrons can be easily injected into the channel 39, and the dark current can be reduced.
[0074]
The pixel 5 of Example 3 of the second embodiment has a convex portion 38 that forms part of the signal storage portions 13 and 38 below the gate electrode 16. By providing the convex portion 38, the depth of the signal storage portion 13 can be made deeper in the substrate 11. Therefore, the position of the depletion layer extending from the signal storage unit 13 can be formed deeper in the substrate 11. This is also clear from the fact that the position of the pn junction can be increased from the depth d1 to the depth d2, as shown in FIG. Generation of noise caused by damage in the dry process of the gate processing process is less likely to be taken into the depletion layer of the signal storage region 13, so that noise generation is suppressed. On the other hand, since the same potential distribution as that of Example 2 of the second embodiment is provided around the convex portion 38, signal electrons can be read with the same low gate voltage.
[0075]
(Third embodiment)
The solid-state imaging device 1 including a CMOS sensor has a first semiconductor region 13 of an n-type diffusion layer and a third semiconductor region 18 of a p-type diffusion layer that constitute a photodiode PD that performs photoelectric conversion. As shown in FIG. 24, the regions 13 and 18 are formed by ion implantation 46 that is self-aligned with the gate electrode 16 of the readout MOS transistor FET1 adjacent to the photodiode PD. The depth of these diffusion layers 13 and 18 from the surface of the silicon substrate 11 is formed at a position much deeper than the source / drain (S / D) diffusion layer of a normal CMOS device. However, when a CMOS sensor is manufactured in accordance with a standard CMOS manufacturing process, such as a CMOS sensor, the thickness of the gate electrode of the CMOS sensor is reduced with the miniaturization of the CMOS sensor. As a result, the thickness of the read gate electrode 16 is also reduced. If the diffusion layers 13 and 18 are to be formed on the thinned readout gate electrode 16 in a self-aligned manner, the ion species penetrates through the gate electrode 16 during the ion implantation 46 and penetrates into the channel portion 45 of the readout gate 16. End up. The threshold value of the read transistor FET1 changes.
[0076]
As shown in FIGS. 25A and 25B, the pixel 5 included in the solid-state imaging device 1 according to the third embodiment has a deep first semiconductor region 13 even when the gate electrode 16 is thin. In addition, the gate electrode 16 can be provided in a self-aligning manner. The fourth semiconductor region 14 is shallow and can be provided in a self-aligned manner with respect to the gate electrode 16. FIG. 25B is a cross-sectional view in the II direction of FIG.
[0077]
Conventionally, even when the thickness of the gate electrode is increased to 300 to 400 nm, the depth of the first semiconductor region 13 is at most 200 to 300 nm. In the third embodiment, the depth of the first semiconductor region 13 is 400 to 700 nm even if the thickness of the gate electrode is reduced to 200 to 300 nm. The depth of the first semiconductor region 13 depends on the performance of the resist used for ion implantation and does not depend on the thickness of the gate electrode 16. It can be made deeper depending on the resist formation conditions.
[0078]
A method for manufacturing the solid-state imaging device 1 according to the third embodiment will be described. In the third embodiment, the read gate electrode 16 is formed by pattern etching twice. In the first pattern etching, a pattern in which the pattern of the gate electrode 16 and the pattern of the photodiode PD are combined is used. The pattern of the second pattern etching is made the pattern of the photodiode PD. A second pattern etching is performed. Without removing the photoresist, ion implantation is performed using the photoresist as a mask. By this ion implantation, the n-type diffusion layer 13 or the p-type diffusion layer 18 constituting the photodiode PD is formed.
[0079]
That is, as shown in FIGS. 26A and 26B, the gate insulating film 15 is formed on the substrate 11. FIG. 26B is a cross-sectional view in the II direction of FIG. A polycrystalline silicon film 47 to be the gate electrode 16 is deposited on the gate insulating film 15. Photoresist patterns 48, 49, 50 are formed on the polycrystalline silicon film 47. The pattern 48 is a pattern of the photodiode PD. Patterns 49 and 50 are patterns of the gate electrodes 16 and 19 to 21. Patterns 48 and 49 are integrated. Next, the first pattern etching is performed. The polycrystalline silicon film 47 is etched. By the first pattern etching, the integrated patterns 47 and 16 of the polycrystalline silicon film and the gate electrodes 19 to 21 are formed. The resist 49 is removed.
[0080]
As shown in FIGS. 27A and 27B, the fourth semiconductor region 14 and the sixth semiconductor region 29 are formed by performing ion implantation using the patterns 47 and 16 and the gate electrodes 19 to 21 as a mask. A resist film 52 is formed on the polycrystalline silicon pattern 16, the gate electrodes 19 to 21 and the substrate 11. The resist film 52 forms an opening 51 that overlaps the pattern 47 on the pattern 47. The pattern of the opening 51 is the same as the pattern of the photodiode PD. 27 (b) and 27 (c) are cross-sectional views in the II direction of FIG. 27 (a).
[0081]
As shown in FIG. 27C, the second pattern etching is performed. The polycrystalline silicon film 47 is etched. The gate electrode 16 is formed by the second pattern etching. Ion implantation 53 is performed using the resist film 52 as a mask. A first semiconductor region 13 and a third semiconductor region 18 are formed. The resist film 52 is peeled off. The exposed polycrystalline silicon surface of the gate electrodes 16, 18 to 21 is oxidized.
[0082]
According to the manufacturing method of the third embodiment, the resist film 52 used for the second pattern etching is left, and ion implantation of the photodiode PD is performed using the resist film 52 as a mask. Since the resist film 52 is used as a mask, ions do not penetrate the gate electrode 16 and reach the silicon substrate 11 even if ion implantation is performed at a position deeper than usual.
[0083]
(Fourth embodiment)
In a solid-state imaging device, an antireflection film is formed for the purpose of improving photosensitivity. As a solid-state imaging device, CMOS sensors have recently attracted attention due to low power consumption and single power supply driving. In the CMOS sensor, since the height of the metal film that defines the opening of the irradiation light is high, even if the irradiation light is defined by the metal film, the optical path is likely to spread before the irradiation light reaches the photodiode PD. This makes it difficult to increase the photosensitivity. Since a CMOS sensor transfers signal charges through a wiring made of polysilicon or the like, a metal film structure that defines an opening is formed above the wiring. The metal film that defines the opening is arranged at a high position.
[0084]
In the fourth embodiment, an amplification type solid-state imaging device including means for condensing irradiation light onto a photodiode PD will be described. And the solid-state imaging device which improved the photosensitivity is provided.
[0085]
(Example 1 of the fourth embodiment)
As shown in FIGS. 28A to 28D, the solid-state imaging device 1 according to the fourth embodiment includes pixels CB, CR, and CG. FIG. 28B is a cross-sectional view in the II direction of FIG. FIG.28 (c) is sectional drawing of the II-II direction of Fig.28 (a). FIG. 28D is a cross-sectional view in the III-III direction of FIG. The pixels CB, CR, and CG constitute the pixel array 2 in FIG. The pixels CB, CR, and CG have a first conductivity type semiconductor substrate 11. The lower surface of the insulator 12 is provided below the surface 11 of the substrate 11. The side surface of the insulator 12 is in contact with the substrate 11. The first semiconductor region 13 of the second conductivity type is provided in the substrate 11 away from the surface of the 11 substrate. The side surface of the first semiconductor region 13 faces the side surface of the insulator 12 through the substrate 11. The silicon oxide films 52 to 54 are provided above the first semiconductor region 13 on the substrate 11. Silicon nitride films 55 to 57 (antireflection film: Si 3 N 4) are provided on the silicon oxide films 52 to 54. The total thickness of the silicon nitride films 55 to 57 and the silicon oxide films 52 to 54 above the first semiconductor region 13 is greater than 600 mm. The silicon nitride films 55 to 57 are different in refractive index from the silicon oxide films 52 to 54.
[0086]
In the pixel CB, as shown in FIG. 28B, the total of the film thickness T2B of the silicon nitride film 55 and the film thickness T1B of the silicon oxide film 52 above the first semiconductor region 13 is larger than 600 mm.
[0087]
In the pixel CR, as shown in FIG. 28C, the total of the film thickness T2R of the silicon nitride film 56 and the film thickness T1R of the silicon oxide film 53 above the first semiconductor region 13 is larger than 700 mm.
[0088]
In the pixel CG, as shown in FIG. 28D, the sum of the film thickness T2G of the silicon nitride film 57 and the film thickness T1G of the silicon oxide film 54 above the first semiconductor region 13 is thicker than 650 mm.
[0089]
Gate electrodes 16, 19 to 21 are provided on the silicon substrate 11. The first semiconductor region serving as the signal storage portion of the photodiode PD is formed by patterning using a resist and implanting phosphorus (P) ions with an accelerator or the like.
[0090]
In order to protect the photodiode PD, silicon oxide films 52 to 54 are deposited to a thickness of about 100 to 200 mm. A preferable film thickness is about 150 to 200 mm. Thus, the photosensitivity can be improved in the laminated structure of the silicon nitride films 55 to 57. The silicon oxide films 52 to 54 are deposited by a chemical vapor deposition (CVD) method or the like. As the antireflection film, for example, silicon nitride (Si3 N4) films 55 to 57 are deposited by a CVD method with a film thickness of about 400 to 700 mm. Then, patterning is performed so that the resist remains in a region 0.2 μm wider than the region of the photodiode PD, for example. The exposed silicon nitride films 55 to 57 are removed by chemical dry etching (CDE: Chemical Dry Etching) or the like to form a desired antireflection film pattern. At this time, the total thickness of the oxide film on the photodiode PD and the film thickness of the antireflection film is preferably 600 mm or more. This is because the antireflection films 55 to 57 have an optimum film thickness of about 500 to 600 mm with respect to the wavelength of green (G) light of 550 nm, and the oxide films 52 to 54 on the photodiode PD. This is because the film thickness is required to be 100 mm or more. The reason why the oxide film thicknesses 52 to 54 on the PD are required to be 100 mm or more is that when the antireflection films 55 to 57 are patterned by CDE, the antireflection films 55 to 57 and the oxide films 52 to 54 on the photodiode PD are This is because damage below the oxide films 52 to 54 can be prevented even if the etching is performed under conditions where the etching selectivity cannot be sufficiently secured (one digit or more).
[0091]
Further, when forming the antireflection films 55 to 57, the film thickness of the antireflection films 55 to 57 is changed for each of the pixels CB, CR, and CG, and the sensitivity is highest in each of the RGB pixels CB, CR, and CG. It is also possible to make the antireflection film thicknesses T2B, T2R, and T2G. As a forming method, a silicon nitride film is deposited to a thickness of about 400 to 500 mm, preferably about 450 mm. Then, for the blue (B) pixel CB, the silicon nitride film is patterned by the CDE method. Again, a silicon nitride film is deposited to a thickness of about 500 to 600 mm, preferably about 550 mm. Then, for the green (G) pixel CG, the silicon nitride film is patterned by the CDE method. Further, a silicon nitride film is deposited to a thickness of about 600 to 700 mm, preferably about 650 mm. Then, for the red (R) pixel CR, the silicon nitride film is patterned by the CDE method. Accordingly, the antireflection films 55 to 57 can be formed with different thicknesses for each of the RGB pixels. Since the RGB photosensitivity can be improved by forming the antireflection films 55 to 57, light of other colors is not irradiated to the photodiode PD in each pixel CB, CR, CG, thereby reducing color mixing. You can also
[0092]
(Example 2 of the fourth embodiment)
As shown in FIGS. 29A to 29D, the pixel 5 of the solid-state imaging device 1 according to Example 2 of the fourth embodiment is illustrated in FIG. 28A of Example 1 of the fourth embodiment. ) To (d), and the width of the silicon nitride films 58 to 60 is narrower than the distance between the side surfaces of the insulator 12. The silicon nitride films 58 to 60 are wider than the first semiconductor region 13. The region where the antireflection films 58 to 60 are formed is wider than the end of the first semiconductor region 13 and narrower than the end of the element isolation region 12.
[0093]
In Example 2 of the fourth embodiment, up to the photodiode PD is formed as in Example 1 of the fourth embodiment. Thereafter, as shown in FIGS. 30A to 30C, silicon oxide films 52 to 54 and silicon nitride films 55 to 57 are formed in the same manner as in Example 1 of the fourth embodiment. Resist patterns 61 to 63 are formed on the silicon nitride films 55 to 57. As shown in FIGS. 30D to 30F, the silicon nitride films 55 to 57 are subjected to pattern etching so that the width of the silicon nitride films 55 to 57 is larger than the photodiode PD (first semiconductor region 13) by about 0.1 μm or more on one side. To do. Antireflection films 58 to 60 are formed. The reason why the antireflection films 58 to 60 are formed in a region wider than the photodiode PD is that side etching is performed during processing by the CDE method. For this reason, when the antireflection films 58 to 60 are left by patterning, it is necessary to provide a width that is at least twice as large as the film thicknesses T2B, T2R, and T2G. This width allows not only side etching by the CDE method but also incidence of a wide range of irradiation light that takes into account the spread of the depletion layer and light refraction. Further, this width hardly causes misalignment in patterning.
[0094]
In addition, the upper limit of the antireflection films 58 to 60 formed in a region wider than the photodiode PD is preferably set to the boundary of the element isolation region 12 at the maximum. This is because stress is likely to occur at the end of the element isolation region 12 when the element isolation region (LOCOS) is formed. This is to prevent crystal defects from occurring in the substrate 11 due to the stress at the end of the element isolation region 12 and the stress of the silicon nitride films 58 to 60.
[0095]
(Example 3 of the fourth embodiment)
As shown in FIG. 31A, the solid-state imaging device 1 according to Example 3 of the fourth embodiment includes pixels C1 and C2. FIG. 31B is a cross-sectional view in the II direction of FIG. The pixels C1 and C2 constitute the pixel array 2 in FIG. The pixel array 2 has a first conductivity type semiconductor substrate 11. The lower surface of the insulator 12 is provided below the surface of the substrate 11. The side surface of the insulator 12 is in contact with the substrate 11. The first conductivity type first semiconductor region 13 is provided in the substrate 11 away from the surface of the substrate 11. The side surface of the first semiconductor region 13 faces the side surface of the insulator 12 through the substrate 11. The silicon oxide region 66 is provided above the first semiconductor region 13. The silicon oxide region 66 has a concave surface above the first semiconductor region 13. The silicon nitride region 67 is provided above the first semiconductor region 13. The silicon nitride region 67 has a convex surface that matches the concave surface of the silicon oxide region 66 above the first semiconductor region 13. The conductors 65 and 64 are provided on the sides of the silicon oxide region 66 and the silicon nitride region 67. The conductors 65 and 64 are metal films such as an aluminum alloy. The silicon nitride region 67 has a refractive index different from that of the silicon oxide regions 66 and 30 serving as an interlayer film. As a result, the silicon nitride region 67 can have a convex lens effect. The conductors 65 and 64 define the opening of the irradiation light between the conductors 65 and 64. A silicon nitride region 67 having a convex lens effect is formed at substantially the same height as this opening.
[0096]
In Example 3 of the fourth embodiment, a convex lens is formed of a material 67 having a refractive index different from that of the interlayer film materials 30 and 66 for the purpose of condensing between the metal film defining the opening of the irradiation light and the photodiode PD. To do. That is, the gate electrodes 16 and 19 to 21 and the photodiode PD are formed. An interlayer insulating film 30 is deposited by about 4000 mm by a low pressure (LP) -CVD method or the like. Next, the conductors 65 and 66 are deposited by sputtering and patterned by RIE. A so-called buried silicon oxide film 66 is deposited by about 1000 mm. A silicon nitride film 67 is deposited by, for example, 15000 by CVD. Thereafter, the surface of the silicon nitride film 67 is flattened by a chemical mechanical polishing (CMP) method or a resist etch back method. As a result, the silicon nitride film 67 is thick on the photodiode PD and thin on the conductor 64 or the like, so that a convex lens convex downward can be formed.
[0097]
(Example 4 of the fourth embodiment)
The solid-state imaging device 1 according to Example 4 of the fourth embodiment includes pixels C1 and C2, as shown in FIG. FIG. 32B is a cross-sectional view in the II direction of FIG. The solid-state imaging device 1 according to Example 4 of the fourth embodiment has a structure similar to that of FIG. 31B of Example 3 of the fourth embodiment, as shown in FIG. . However, it has a partially different structure. That is, the silicon oxide region 69 is provided above the first semiconductor region 13. The silicon oxide region 69 has a concave surface above the first semiconductor region 13. The silicon nitride region 68 is provided above the first semiconductor region 13. The silicon nitride region 68 has a convex surface that matches the concave surface of the silicon oxide region 69 above the first semiconductor region 13. The conductors 65 and 64 are provided on the sides of the silicon oxide region 69 and the silicon nitride region 68. As a result, the silicon nitride region 68 can have a convex lens effect. The conductors 65 and 64 define the opening of the irradiation light between the conductors 65 and 64. A silicon nitride region 68 having a convex lens effect is formed at substantially the same height as this opening.
[0098]
In Example 4 of the fourth embodiment, the in-layer lens is formed at the same height as or lower than the conductors 64 and 65 that define the opening. The formation method of Example 4 of the fourth embodiment is similar to Example 3 of the fourth embodiment, in which the gate electrode 16 and the like, the photodiode PD, and, if necessary, an antireflection film are formed. To do. An interlayer film 30 such as a silicon oxide film is deposited by, for example, the LP-CVD method. The interlayer film 30 is planarized by a CMP method, a resist etch back (EB) method, or the like. As the conductors 64 and 65 that define the openings, for example, a metal film such as aluminum (Al) is deposited by a sputtering method or the like, for example, to a thickness of about 4000 mm. The metal film is patterned by resist coating, resist patterning, RIE, or the like. The metal film in a desired region is removed, an opening region is secured, and conductors 64 and 65 that define the opening are formed. At this time, a step is formed on the surface by the thickness of the conductors 64 and 65. Here, for example, the silicon nitride film 68 is deposited by an LP-CVD method or the like, corresponding to a film thickness smaller than the level difference between the conductors 64 and 65, for example, about 2000 mm. As a result, a silicon nitride film 68 is deposited on the conductors 64 and 65 with a thickness of 2000 mm. However, in the openings of the conductors 64 and 65, the silicon nitride film 68 is hardly deposited at the ends of the openings of the conductors 64 and 65 due to shadow wing or the like when the silicon nitride film 68 is deposited. Becomes thinner. In the vicinity of the center of the openings of the conductors 64 and 65, the film thickness is about 2000 mm. As a result, a convex lens of the silicon nitride film 68 can be formed at the openings of the conductors 64 and 65. After that, a silicon oxide film 69 is deposited by LP-CVD or the like, and planarized by CMP or resist EB.
[0099]
(Example 5 of the fourth embodiment)
The solid-state imaging device 1 according to Example 5 of the fourth embodiment includes pixels C1 and C2, as shown in FIG. FIG. 33B is a cross-sectional view in the II direction of FIG. As shown in FIG. 33B, the solid-state imaging device 1 according to Example 5 of the fourth embodiment has the same structure as FIG. 32B of Example 4 of the fourth embodiment. . However, it has a partially different structure. That is, the silicon oxide region 71 is provided above the first semiconductor region 13. The silicon oxide region 71 has a concave surface above the first semiconductor region 13. The silicon nitride region 70 is provided above the first semiconductor region 13. The silicon nitride region 70 has a convex surface that matches the concave surface of the silicon oxide region 71 above the first semiconductor region 13. The conductor 16 is provided on the side of the silicon oxide region 71 and the silicon nitride region 70. As a result, the silicon nitride region 70 can have a convex lens effect. The conductors 65 and 64 define the opening of the irradiation light between the conductors 65 and 64. A silicon nitride region 70 having a convex lens effect is formed below the opening.
[0100]
In Example 5 of the fourth embodiment, the in-layer lens is formed at a height lower than the conductors 64 and 65 defining the opening. The formation method of Example 5 of the fourth embodiment is the same as that of Example 3 of the fourth embodiment, in which the gate electrode 16 and the like, the photodiode PD, and, if necessary, an antireflection film are formed. To do. At this time, a step is generated on the surface by the gate electrode 16 and the insulator 12. Here, the silicon nitride film 70 is deposited by about 2000 mm. As a result, a convex lens of the silicon nitride film 70 can be formed as in Example 4 of the fourth embodiment. After that, a silicon oxide film 71 is deposited by LP-CVD or the like, and planarized by CMP or resist EB. The conductors 64 and 65 defining the opening are deposited to a thickness of about 4000 mm. Conductors 64 and 65 are patterned to form conductors 64 and 65 that define openings. After that, a silicon oxide film 72 is deposited by LP-CVD or the like, and planarized by CMP or resist EB.
[0101]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a solid-state imaging device in which thermal noise and dark current noise are unlikely to occur and the reproduction screen S / N is unlikely to deteriorate.
[Brief description of the drawings]
FIG. 1 is a top view of a solid-state imaging device according to a first embodiment and a schematic diagram of pixels included in the solid-state imaging device.
FIG. 2 is a top view of pixels included in the solid-state imaging device according to the first embodiment.
FIG. 3 is a cross-sectional view of a pixel included in the solid-state imaging device according to the first embodiment and an energy level diagram for explaining a basic operation.
FIG. 4 is a top view of pixels included in the solid-state imaging device according to Example 1 of the first embodiment;
5 is a cross-sectional view of a pixel included in the solid-state imaging device according to Example 1 of the first embodiment and an energy level diagram for explaining a basic operation. FIG.
6 is a cross-sectional view of a pixel included in a solid-state imaging device according to Modification 1 and Modification 2 of Example 1 of the first embodiment; FIG.
7 is a cross-sectional view of a pixel included in a solid-state imaging device according to Example 2 of the first embodiment and an energy level diagram for explaining a basic operation. FIG.
8 is a cross-sectional view of pixels included in a solid-state imaging device according to Modification 1 and Modification 2 of Example 2 of the first embodiment. FIG.
FIGS. 9A and 9B are a top view and a cross-sectional view of a pixel included in a solid-state imaging device according to Example 3 of the first embodiment. FIGS.
10 is a cross-sectional view of a pixel included in a solid-state imaging device according to Modification 1 and Modification 2 of Example 3 of the first embodiment. FIG.
FIGS. 11A and 11B are a top view and a cross-sectional view of a pixel included in a solid-state imaging device according to Example 4 of the first embodiment; FIGS.
12 is a cross-sectional view of pixels included in a solid-state imaging device according to Modification Example 1 and Modification Example 2 of Example 4 of the first embodiment; FIG.
FIG. 13 is a top view of pixels included in the solid-state imaging device according to Example 1 of the second embodiment;
FIG. 14 is a detailed top view, cross-sectional view, and energy level diagram of a pixel included in the solid-state imaging device according to Example 1 of the second embodiment;
15A and 15B are a top view and a cross-sectional view for explaining a method of manufacturing a pixel included in the solid-state imaging device according to Example 1 of the second embodiment.
FIG. 16 is a detailed cross-sectional view of a pixel included in a solid-state imaging device according to a modification of Example 1 of the second embodiment.
17 is a detailed top view and cross-sectional view of a pixel included in a solid-state imaging device according to Example 2 of the second embodiment; FIG.
FIG. 18 is an energy level diagram of a pixel included in a solid-state imaging device according to Example 2 of the second embodiment;
FIG. 19 is a detailed top view of pixels included in a solid-state imaging device according to Modifications 1 to 3 of Example 2 of the second embodiment;
FIG. 20 is a detailed top view of pixels included in a solid-state imaging device according to Modifications 4 to 6 of Example 2 of the second embodiment;
FIG. 21 is a detailed top view of pixels included in a solid-state imaging device according to Modification Example 7 and Modification Example 8 of Example 2 of the second embodiment;
FIG. 22 is a graph showing the shape dependency of the number of pixels in which white scratches are observed in the solid-state imaging device according to Example 2 of the second embodiment, and the shape of the convex portion of the gate electrode.
FIG. 23 is a detailed top view, cross-sectional view, and impurity concentration distribution diagram of a pixel included in a solid-state imaging device according to Example 3 of the second embodiment;
FIG. 24 is a cross-sectional view of a pixel included in a solid-state imaging device according to a comparative example of the third embodiment.
FIGS. 25A and 25B are a top view and a cross-sectional view of a pixel included in a solid-state imaging device according to a third embodiment. FIGS.
26A and 26B are a top view and a cross-sectional view (No. 1) for describing a method for manufacturing a pixel included in the solid-state imaging device according to the third embodiment.
27A and 27B are a top view and a cross-sectional view (No. 2) for describing a method for manufacturing a pixel included in the solid-state imaging device according to the third embodiment.
FIG. 28 is a top view and a cross-sectional view of a pixel included in a solid-state imaging device according to Example 1 of the fourth embodiment;
FIGS. 29A and 29B are a top view and a cross-sectional view of a pixel included in a solid-state imaging device according to Example 2 of the fourth embodiment. FIGS.
30 is a cross-sectional view illustrating a method for manufacturing a pixel included in a solid-state imaging device according to Example 2 of the fourth embodiment; FIG.
FIG. 31 is a top view and a cross-sectional view of a pixel included in a solid-state imaging device according to Example 3 of the fourth embodiment;
32 is a top view and a cross-sectional view of a pixel included in a solid-state imaging device according to Example 4 of the fourth embodiment; FIG.
FIG. 33 is a top view and a cross-sectional view of a pixel included in a solid-state imaging device according to Example 5 of the fourth embodiment;
[Explanation of symbols]
1 Solid-state imaging device
2 pixel array
3 signal scanning circuit
4 signal readout circuit
5 pixels
11 p-type semiconductor substrate
12 Device isolation region
13 Photodiode (PD) signal storage
14 detector (detect node, drain region of FET1)
15 Gate insulation film of FET1
16 Gate electrode of FET1
17 Active region
18 Channel stopper and dark current suppression area
19 Gate electrode of FET4
20 Gate electrode of FET3
21 Gate electrode of FET2
22 n-type semiconductor region
23 conduction band
24 Accumulated signal electrons
25 Signal electron moved
26 p-type semiconductor region
27 Distribution of electrons generated at the gate electrode and causing dark current
28 Projection (convex)
29 Punch-through prevention area
30 Interlayer insulation film
31 electrons
32 element isolation region
33 Channel stopper area
34 Dark current suppression region
35 Microlens
36, 37 Direction of electron movement
38 Convex
39 Impurity region
Impurity concentration distribution of 40 PDp
Impurity concentration distribution of 41 PDn (13)
Impurity concentration distribution of 42 PDn (13 and 38)
43 Impurity concentration distribution of PDn (38)
44 resist
45 Impurity diffusion layer
46, 53 Ion beam
47 Polysilicon film
48, 49, 50, 52 resist
51 resist opening
52 to 54 Silicon oxide film
55 to 60 silicon nitride film
61-63 resist
64, 65 metal wiring
66, 69, 71, 72 Silicon oxide film
67, 68, 70 Silicon nitride film
FET1 Read transistor (transfer transistor)
FET2 reset transistor
FET3 amplification transistor
FET4 row selection transistor

Claims (10)

A first conductivity type semiconductor substrate;
A first semiconductor region of a second conductivity type provided inside the substrate and serving as a signal storage region;
An insulating film provided on the substrate surface;
A conductor which is provided on the insulating film and has a convex portion, and becomes a gate electrode provided above the first semiconductor region in the center of the section where the convex portion defines the gate width ;
Provided on the substrate including the surface of the substrate, in contact with a side surface of the first semiconductor region , provided above the first semiconductor region and below the conductor, and provided with an offset between the convex portions. A third semiconductor region of the first conductivity type that becomes a surface shield layer;
The second conductive type fourth semiconductor region which is provided on the substrate and is located on the opposite side to the first semiconductor region from the substrate located below the conductor and serves as a signal detection unit. A solid-state imaging device.   The first provided on the substrate including the surface of the substrate, provided below the conductor including the convex portion, and provided between the third semiconductor region and the fourth semiconductor region and serving as a channel region. The solid-state imaging device according to claim 1, further comprising a conductive second semiconductor region. The first semiconductor region is the signal storage unit that stores signal charges obtained by photoelectric conversion,
The conductor is the gate electrode of a field effect transistor that discharges the signal charge from the signal storage unit,
The solid-state imaging device according to claim 1, wherein the gate electrode has a maximum gate length at the convex portion of the conductor. 4. The solid-state imaging device according to claim 1, wherein a width of the first semiconductor region is larger than a width of the convex portion. 5.   The second semiconductor region extends from below the conductor toward the third semiconductor region, the second semiconductor region is provided in a region where the offset exists, and a distance between the convex portion and the third semiconductor region is The solid-state imaging device according to claim 2, wherein the solid-state imaging device is larger than the thickness of the insulating film.   The width of the opening that opens from the first semiconductor region to the conductor in the third semiconductor region widens from the first semiconductor region toward the conductor. 6. The solid-state imaging device according to any one of items 1 to 5.   7. The solid-state imaging device according to claim 1, wherein a width of the convex portion increases from the first semiconductor region toward the conductor. 8.   The solid-state imaging device according to claim 6, wherein the opening draws a semicircle.   The solid-state imaging device according to claim 1, wherein the convex portion has a semicircular shape.   10. The solid-state imaging device according to claim 1, wherein a distance between the third semiconductor region and the convex portion is 0.1 to 0.3 μm.

Images