JP2003188367A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image device which is hard to generate thermal noise and dark current noise, and is hard to deteriorate S/N of a regenerated image plane. <P>SOLUTION: Apart from a surface of a first conductive semiconductor substrate, a first second-conductive-type semiconductor field is provided in an inside of the substrate. Apart upwardly from the first semiconductor region, a second second-conductive-type semiconductor region is provided on a substrate including a surface of the substrate. An insulating film is provided on the second semiconductor region, and a conductor is provided on the insulating film. A first conductive type of a third semiconductor region, such that a back plane contacts to an upper plane of the first semiconductor field and a side plane contacts to a side plane of the second semiconductor field, and such that a distance from the conductor is larger than a film thickness of the insulating film on the substrate including the surface of the substrate. The second conductive type of a fourth semiconductor region is provided on the substrate including the surface of the substrate, such that the side plane contacts to the side plane of the second semiconductor region and the distance from the conductor is equal to the film thickness of the insulating film. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel structure of a solid-state image pickup device, and more particularly to a photodiode of the pixel and a structure around the photodiode.

[0002]

2. Description of the Related Art A solid-state image pickup device has a pixel array for converting incident optical image information into an electric signal. The pixel array is made up of pixels. The pixel has a photodiode for converting incident light into an electric signal and storing the electric signal for a certain period. The photodiode is formed on the p-type semiconductor substrate. The photodiode has an n-type semiconductor layer formed inside the substrate for accumulating photoelectrons which are electric signals, and a p-type semiconductor layer provided on the surface of the substrate above the n-type semiconductor layer. The p-type semiconductor layer suppresses dark current generated on the substrate surface.

Further, the pixel has a transfer transistor for reading out the stored electric signal. This transfer transistor has a read gate and a signal detector.

At the time of reading a signal, a positive potential is applied to the read gate to increase the potential of the channel below the read gate. Therefore, the signal electrons accumulated in the photodiode flow out to the signal detector through this channel and are read out.

However, in the structure of the conventional solid-state image pickup device,
Thermal noise was sometimes generated. That ’s why the playback screen
There was a problem that S / N deteriorated. Further, there is a problem that dark current noise may occur even though there is a p-type semiconductor layer.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and its object is to:
It is to provide a solid-state imaging device in which thermal noise and dark current noise are less likely to occur and the S / N of a playback screen is less likely to deteriorate.

[0007]

In order to solve the above problems, a feature of the present invention is that a semiconductor substrate of the first conductivity type and a second conductivity type provided inside the substrate apart from the surface of the substrate. A first semiconductor region of the mold, and a second substrate provided on the substrate including the surface of the substrate and spaced above the first semiconductor region.
A second semiconductor region of conductivity type, an insulating film provided on the second semiconductor region, a conductor provided on the insulating film, and a substrate including the surface of the substrate, the lower surface of which is the first semiconductor. Provided on the substrate including the surface of the substrate and the third semiconductor region of the first conductivity type, which is in contact with the upper surface of the region, the side face is in contact with the side face of the second semiconductor region, and the distance from the conductor is not less than the thickness of the insulating film. And a side surface of the second semiconductor region is in contact with the side surface of the second semiconductor region, and the fourth semiconductor region of the second conductivity type has a distance from the conductor equal to the thickness of the insulating film.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from the actual ones. Further, it is a matter of course that the drawings include parts having different dimensional relationships and ratios.

(First Embodiment) As shown in FIG. 1A, the solid-state image pickup device according to the first embodiment is as follows.
Pixel array 2 that converts incident light image information into electrical signals
A signal scanning circuit 3 for sending to the pixel array 2 a control signal for sequentially reading the signals stored in the pixel array 2, and a signal reading circuit 4 for sequentially reading the signals read from the pixel array 3 out of the solid-state imaging device. have. The pixel array 2 has pixels 5 which are unit cells arranged in a two-dimensional array.

As shown in FIG. 1B, the pixel 5 has a photodiode PD for converting incident light into an electric signal and accumulating the electric signal for a certain period. Further, a row selection transistor FET4 for selectively reading out the electric signal of the photodiode PD, an amplification transistor FET3 for amplifying the electric signal, a reset transistor FET2 for resetting the electric signal, and an electricity of the photodiode PD. It comprises a transfer transistor FET1 for outputting a signal to a gate electrode which is an input of the amplification transistor FET3 and reading an electric signal. The photodiode PD has a signal storage unit 13 provided in the p-type semiconductor substrate 11. The transfer transistor FET1 has a read gate provided above the substrate 11.

The structure of the pixel 5 is shown in more detail in FIGS.
It shows in (a). FIG. 3A is a sectional view taken along the line II of FIG. The pixel 5 has a first conductivity type semiconductor substrate 11 or a first conductivity type well (we) provided on the substrate 11.
11). Second conductivity type first semiconductor region 13
Is provided inside the substrate 11 apart from the surface of the substrate 11. The first conductivity type may be p-type or n-type.
When the first conductivity type is p-type, the second conductivity type is n-type. When the first conductivity type is n-type, the second conductivity type is p-type. The insulating film 15 is provided on the substrate 11. The conductor 16 is provided on the insulating film 15. First
The conductive third semiconductor region 18 is provided in the substrate 11 including the surface of the substrate 11. The lower surface of the third semiconductor region 18 contacts the upper surface of the first semiconductor region 13. Third semiconductor region 18
The distance between the conductor 16 and the conductor 16 is equal to the thickness of the insulating film 15. The second conductivity type fourth semiconductor region 14 is provided in the substrate 11 including the surface of the substrate 11, and the distance from the conductor 16 is the insulating film 1.
5 is equal to the film thickness. The lower surface of the insulator 12 is provided below the surface of the substrate 11, and the side surface and the lower surface of the insulator 12 are in the third semiconductor region 18.
Touch. A p-well 11 is formed on the substrate 11.
It is provided. The first semiconductor region 13 is an n-type semiconductor layer that stores photoelectrons. The third semiconductor region 18 is a p-type semiconductor layer provided on the surface of the photodiode PD. The fourth semiconductor region 14 is an n-type semiconductor layer that detects signal electrons read from the photodiode PD. The third semiconductor region suppresses dark current generated on the surface of the substrate 11. The conductor 16 is the gate electrode of the FET 1. The conductor 21 is the gate electrode of the FET 2. Conductor 20
Is a gate electrode of FET3. The conductor 19 is FE
It is a gate electrode of T4. The surface of the substrate 11 without the insulator 12 is the active region 17.

FIG. 3B is a potential distribution diagram during electric signal accumulation between I and I in FIG. 3A. FIG. 3C is a potential distribution diagram at the time of reading an electric signal. When electric signals are accumulated, as shown in FIG. 3B, the reference potential is applied to the read gate 16, and the potential of the channel below the read gate 16 is low. Therefore, the photodiode PD
The signal electrons 24 are accumulated in the first semiconductor region 13 without leaking. At the time of signal reading, as shown in FIG. 3C, a positive potential is applied to the read gate 16, so that the potential of the channel below the read gate 16 becomes high. Therefore, the signal electrons 24 accumulated in the first semiconductor region 13 of the photodiode PD flow out to the fourth semiconductor region 14 which is the signal detecting portion through the channel of the read gate 16 and the electric signal is read.

However, in the structure of the pixel 5 shown in FIG. 3A, thermal noise and dark current noise may occur.

The third semiconductor region 18 is connected to a reference voltage and fixed at the reference potential. Therefore, the read gate 1
It is difficult to raise the potential of the channel of the photodiode PD of 6 when the read gate 16 is in the ON state. further,
As the pixel 5 becomes finer, the power supply voltage becomes lower accordingly, so that the voltage applied to the read gate becomes lower. This also makes it difficult to raise the potential of the channel sufficiently when the read gate is in the ON state. Electrons 24 remain in the photodiode PD because the potential of the channel cannot be raised sufficiently during reading. The residual electrons 24 are considered to be the cause of thermal noise. Then, it is considered that the thermal noise deteriorates the S / N ratio of the reproduction screen. This means that it becomes difficult to achieve both low dark current and low thermal noise as the pixels become finer.

The read gate 16 is made of polycrystalline silicon or a silicide material. As a result, local stress is generated at the end of the read gate 16. This stress may induce a carrier generation level, which is a source of dark current, on the surface of the silicon substrate 11. The electrons generated from this carrier generation level are
The first semiconductor region 13 which is a signal storage portion during the signal storage period
Flow into. It is considered that dark current noise is generated by the inflow of electrons.

Example 1 of First Embodiment The structure of a pixel 5 according to Example 1 of the first embodiment is shown in FIGS.
It shows in (a). FIG. 5A is a sectional view taken along the line II of FIG. The pixel 5 has a first conductivity type semiconductor substrate 11. The first semiconductor region 13 of the second conductivity type is the substrate 1
It is provided inside the substrate 11 apart from the surface of the substrate 1. The second conductivity type second semiconductor region 22 is provided in the substrate 11 including the surface of the substrate 11, and is provided above the first semiconductor region 13 so as to be separated therefrom. The insulating film 15 is provided on the second semiconductor region 22. The conductor 16 is provided on the insulating film 15. The third semiconductor region 18 of the first conductivity type is formed on the substrate 11
Is provided on the substrate 11 including the surface of. Third semiconductor region 1
The lower surface of 8 contacts the upper surface of the first semiconductor region 13, and the side surface of the third semiconductor region 18 contacts the side surface of the second semiconductor region 22. The distance between the third semiconductor region 18 and the conductor 16 is larger than the film thickness of the insulating film 15. Second conductivity type fourth semiconductor region 1
4 is provided on the substrate 11 including the surface of the substrate 11. The side surface of the fourth semiconductor region 14 contacts the side surface of the second semiconductor region 22. The distance between the fourth semiconductor region 14 and the conductor 16 is equal to the film thickness of the insulating film 15. The lower surface of the insulator 12 is the substrate 11
Is provided below the surface of the. The side surface and the lower surface of the insulator 12 are in contact with the third semiconductor region 18. The first semiconductor region 13 is
The signal storage unit of the photodiode PD stores the signal charges obtained by photoelectric conversion. The conductor 16 is a field effect transistor FE that discharges signal charges from the signal storage unit.
It is the gate electrode of T1. The second semiconductor region 22 is a channel region of the transistor FET1. The fourth semiconductor region 14 is a drain region of the FET 1 and is a signal detector that detects signal charges.

The second semiconductor region 22 includes the read gate 16
Is an n-type diffusion layer provided in the channel region. Also,
The third semiconductor region 18 and the read gate 16 are offset by the offset distance X. The offset is provided for the following reason. Local stress is generated at the end of the read gate 16 made of polycrystalline silicon or a silicide material. This stress easily induces carrier generation levels that are sources of dark current at the interface of the silicon substrate 11. The second semiconductor region 22 provided below the read gate 16 extends from the read gate 16 toward the third semiconductor region 18 by the distance X. The dark current electrons generated from the generated level do not flow into the signal storage layer 13 of the photodiode PD during the signal storage period. The dark current electrons flow out to the signal detection unit 14 through the second semiconductor region.
Therefore, noise is not generated on the reproduction screen.

FIG. 5 (b) is a potential distribution diagram during electric signal accumulation between I and I in FIG. 5 (a). FIG. 5C is a potential distribution diagram at the time of reading an electric signal. When electric signals are accumulated, signal electrons are accumulated in the accumulation layer 13 as shown in FIG.
P-type semiconductor substrate 1 sandwiched between the read channel 22 and the read channel 22.
The potential in the region 1 serves as a barrier and is stored in the storage layer 13.

At the time of reading a signal, as shown in FIG. 5C, a positive potential is applied to the read gate 16, so that the potential of the channel 22 below the read gate 16 becomes high. The potential of the region of the p-type semiconductor substrate 11 sandwiched between the regions 13 and 22 increases accordingly, and the signal electrons of the signal storage unit 13 are all read out to the signal detection unit 14. Therefore, there are no residual electrons, and noise such as thermal noise and afterimage does not occur.

As described above, the signal storage section 13 and the read channel 22 of the same conductivity type as that of the signal storage section 13 are formed below the read gate 16 so as to overlap in the depth direction while sandwiching the region of the substrate 11 of a different conductivity type. Has been done. This makes it easier to read the region 13 when the read gate 16 is in the ON state.
The electric potential of the substrate 11 sandwiched between 22 and 22 can be modulated. The signal can be read with a lower read voltage than before. Therefore, even if the pixel is miniaturized and the power supply voltage is reduced, noise such as thermal noise and afterimage that have been present in the past does not occur.
A clear image with little noise can be obtained on the playback screen. Further, since the channel 22 of the read gate 16 extends to a position separated from the read gate electrode 16 by a predetermined distance X, the dark current generated at the edge of the gate 16 flows into the signal storage unit 13 during the signal storage period. There is no. Therefore, dark current noise is significantly suppressed, and a clear image with little noise can be obtained on the reproduction screen.

(Modification 1 of Example 1 of the First Embodiment) A pixel 5 of a solid-state imaging device 1 according to Modification 1 of Example 1 of the first embodiment is shown in FIG. As shown in FIG.
In addition to having the same structure as that of (a), the depth from the surface of the substrate 11 to the upper surface of the first semiconductor region 13 is deeper than the depth from the surface of the substrate 11 to the lower surface of the insulator 12. The depth from the surface of the substrate 11 to the lower surface of the third semiconductor region 18, which is in contact with the upper surface of the first semiconductor region 13, is deeper than the depth from the surface of the substrate 11 to the lower surface of the insulator 12.
Third p-type semiconductor layer on the surface of the photodiode PD
The formation depth of the semiconductor region 18 is formed deeper so as to cover the lower end of the insulator 12 of the silicon oxide (SiO2) layer which is the element isolation region. As a result, it is possible to more reliably prevent the dark current generated on the surface of the substrate 11 from being injected into the first semiconductor region 13.

The thickness of the second semiconductor region 22 is also changed to be thick. By increasing the thickness, the distance between the lower surface of the second semiconductor region 22 and the upper surface of the first semiconductor region 13 can be reduced as shown in FIGS.
Same as in (a). As a result, it is not necessary to increase the modulation potential applied to the gate 16.

(Modification 2 of Example 1 of First Embodiment) A pixel 5 of a solid-state image pickup device 1 according to Modification 2 of Example 1 of the first embodiment is shown in FIG. As shown in FIG.
(A), not only has a structure similar to FIG. 6 (a),
Further, the first semiconductor region 13 is provided below the insulator 12. The first semiconductor region 13 of the n-type semiconductor layer which is a signal storage layer is formed below the insulator 12 of the element isolation region. As a result, the light receiving area of the photodiode PD can be increased, and the sensitivity of the photodiode PD is improved.

Example 2 of First Embodiment The pixel 5 of the solid-state imaging device 1 according to Example 2 of the first embodiment is
As shown in FIG. 7A, in addition to having a structure similar to that of FIG. 5A, a fifth semiconductor region 26 of the first conductivity type is formed on the first semiconductor region 13 to form a second semiconductor region. Semiconductor region 2
It is provided under 2. A fifth semiconductor region 26 of a p-type semiconductor layer is provided in a region above the first semiconductor region 13 of the signal storage region below the second semiconductor region 22 of the n-type semiconductor layer that serves as a channel of the read gate 16. . The impurity concentration of the substrate 11 is about 10 ¹⁵ to 10 ¹⁶ cm ⁻³ . The impurity concentration of the first semiconductor region 13 is 10 ¹⁶
It is about 10 ¹⁷ cm ⁻³ . The impurity concentration of the first semiconductor region 13 is about 10 ¹⁶ to 10 ¹⁷ cm ⁻³ . The impurity concentration of the second semiconductor region 22 is 10 ¹⁶ to 1
It is about 0 ¹⁷ cm ⁻³ . The impurity concentration of the third semiconductor region 18 is about 10 ¹⁸ to 10 ¹⁹ cm ⁻³ . The impurity concentration of the fourth semiconductor region 14 is 10 ¹⁹ to 10 ^20.
It is about cm ⁻³ . The impurity concentration of the fifth semiconductor region 26 is about 10 ¹⁶ to 10 ¹⁷ cm ⁻³ .

With such a structure, the signal storage region 13
The potential barrier between the read channel 22 and the read channel 22 is increased, and the number of electrons stored in the signal storage region 13 can be increased. FIG. 7B is a potential distribution diagram of the path between I and I in FIG. 7A. FIG. 7C shows II-II of FIG. 7A.
It is an electric potential distribution map of the path between. As shown in FIG. 7B, the dark current 27 generated at the edge of the read gate 16
Are discharged to the signal detection unit 14 through the read channel 22. As shown in FIG. 7C, the dark current 27 generated by the gate of the gate 16 during the signal accumulation period is the signal accumulation region 1
The potential of the fifth semiconductor region 26 of the p-type semiconductor layer sandwiched between the channel 3 and the channel 22 serves as a potential barrier for signal electrons and does not flow into the signal storage region 13.

(Modification 1 of Example 2 of the First Embodiment) A pixel 5 of a solid-state imaging device 1 according to Modification 1 of Example 2 of the first embodiment is shown in FIG. As shown in FIG.
In addition to having the same structure as that of (a), the depth from the surface of the substrate 11 to the upper surface of the first semiconductor region 13 is deeper than the depth from the surface of the substrate 11 to the lower surface of the insulator 12. As a result, it is possible to more reliably prevent the dark current generated on the surface of the substrate 11 from being injected into the first semiconductor region 13.

(Modification 2 of Example 2 of the First Embodiment) A pixel 5 of a solid-state imaging device 1 according to Modification 2 of Example 2 of the first embodiment is shown in FIG. As shown in FIG.
(A), not only has a structure similar to FIG. 8 (a),
Further, the first semiconductor region 13 is provided below the insulator 12. As a result, the light receiving area of the photodiode PD can be increased.

Example 3 of First Embodiment The structure of the pixel 5 of the solid-state imaging device 1 according to Example 3 of the first embodiment is shown in FIGS. 9 (a) and 9 (b). Show. FIG. 9B shows
It is sectional drawing of the II line | wire of FIG.9 (a). The pixel 5 of the solid-state imaging device 1 according to Example 3 of the first exemplary embodiment is the third
This example differs from Example 1 of the first embodiment in that the distance between the semiconductor region 18 and the conductor 16 is equal to the film thickness of the insulating film 15. the third semiconductor region 18, which is a p-type semiconductor layer,
The read gate 16 is formed in a self-aligned manner without offset. Due to this, the dark current generated at the edge of the gate 16 is the third current as shown in FIG.
The signal is injected into the signal detection unit 14 due to the gradient of the potential distribution of the p-type semiconductor region of the semiconductor region 18.

(Modification 1 of Example 3 of the First Embodiment) A pixel 5 of a solid-state image pickup device 1 according to Modification 1 of Example 3 of the first embodiment is shown in FIG. As shown in the figure, in addition to having the same structure as in FIG. 9B, the depth from the surface of the substrate 11 to the upper surface of the first semiconductor region 13 is from the surface of the substrate 11 to the lower surface of the insulator 12. Deeper than. As a result, it is possible to more reliably prevent the dark current generated on the surface of the substrate 11 from being injected into the first semiconductor region 13.

(Modification 2 of Example 3 of the first embodiment) A pixel 5 of a solid-state image pickup device 1 according to Modification 2 of Example 3 of the first embodiment is shown in FIG. As shown, in addition to having the same structure as in FIGS. 9B and 10A, the first semiconductor region 13 is further provided below the insulator 12. As a result, the photodiode P
The light receiving area of D can be expanded.

Example 4 of First Embodiment A structure of a pixel 5 of a solid-state image pickup device 1 according to Example 4 of the first embodiment is shown in FIGS. 11 (a) and 11 (b). Show. Figure 11
11B is a cross-sectional view taken along the line I-I of FIG.
The pixel 5 of the solid-state imaging device 1 according to the example 4 of the first embodiment includes the first semiconductor region 1 with respect to the third semiconductor region 18.
The offset distance Y of the offset of 3 is shorter than the offset distance X, which is different from Example 1 of the first embodiment. This also enables the channel 22 of the signal electron
It is thought that injection into the can be done easily.

(Modification 1 of Example 4 of the First Embodiment) A pixel 5 of a solid-state image pickup device 1 according to Modification 1 of Example 4 of the first embodiment is shown in FIG. As shown, in addition to having a structure similar to that of FIG.
The depth from the surface of the substrate 11 to the upper surface of the first semiconductor region 13 is deeper than the depth from the surface of the substrate 11 to the lower surface of the insulator 12. As a result, it is possible to more reliably prevent the dark current generated on the surface of the substrate 11 from being injected into the first semiconductor region 13.

(Modification 2 of Example 4 of the first embodiment) A pixel 5 of a solid-state imaging device 1 according to Modification 2 of Example 4 of the first embodiment is shown in FIG. As shown in the figure, in addition to having the same structure as in FIGS. 11B and 12A, the first semiconductor region 13 is formed below the insulator 12.
Is provided. As a result, the light receiving area of the photodiode PD can be increased.

(Second Embodiment) The number of pixels of the solid-state image pickup device 1, the size of the image pickup system, the size of the image pickup module, etc. are being reduced. There is an increasing demand for miniaturization of the size of the pixel 5. In the future, in order to effectively perform photoelectric conversion in a pixel whose area is further reduced, it is required that there be as few structures as possible that block or reflect light in the incident path of light. Furthermore, in order to improve the signal / noise (S / N) ratio, it is necessary to minimize the electrons generated in the silicon (Si) substrate 11 even when there is no incident light. Since the generation of the electrons varies with time, it becomes a noise component causing unevenness in the image. Furthermore,
There is also a demand for reduction of afterimages at low voltage.

In the first embodiment, the gate length of the gate 16 of the transfer transistor FET1 that controls the transfer of the signal charge is constant. As a result, light is also applied to the portion that does not necessarily contribute to the storage / transfer of signal charges.

In the second embodiment, the S / N ratio is improved, complete transfer is possible at a low voltage, and the light incident path is expanded. In order to carry out charge transfer / accumulation at a low voltage, an appropriate gate length is required. That is, paying attention to the potential distribution of the charge accumulating portion 13, only the portion of the gate 16 required for charge accumulating / transferring is provided with a projecting protrusion. The gate length of the other parts of the gate 16 is made as short as possible. With these, the light incident path can be expanded.

Example 1 of Second Embodiment The structure of the pixel 5 of the solid-state imaging device 1 according to Example 1 of the second embodiment is shown in FIGS. 13 and 14A to 14D. Shown in. 14
13B is a sectional view taken along line I-I of FIGS. 13 and 14A. FIG. 14C shows II of FIG. 13 and FIG. 14A.
It is a sectional view of the -II direction. FIG. 14D is the same as FIG.
It is sectional drawing of the III-III direction of (a). Pixel 5
Has a first conductivity type semiconductor substrate 11. The first semiconductor region 13 of the second conductivity type is provided inside the substrate 11 apart from the surface of the substrate 11. The insulating film 15 is provided on the surface of the substrate 11. The conductor 16 is the insulating film 1
5 is provided above. The protrusion 28 of the conductor 16 is provided above the first semiconductor region 13. The third semiconductor region 18 of the first conductivity type is provided on the substrate 11 including the surface of the substrate 11. The third semiconductor region 18 is provided above the first semiconductor region 13. The third semiconductor region 18 contacts the side surface of the first semiconductor region 13. The third semiconductor region 18 is provided below the conductor 16. The second conductivity type fourth semiconductor region 14 is provided in the substrate 11 including the surface of the substrate 11.
The distance between the fourth semiconductor region 14 and the conductor 16 is the insulating film 15
Equal to the film thickness of. The sixth semiconductor region 29 is provided below the fourth semiconductor region 14. The sixth semiconductor region 29 prevents punch through. Second semiconductor region 39 of the second conductivity type
Are provided on the substrate 11 including the surface of the substrate 11. Second
The semiconductor region 39 is provided below the conductor 16, and particularly below the convex portion 28 of the conductor 16. The second semiconductor region 39 is in contact with the side surface of the third semiconductor region 18 and the fourth semiconductor region 39.
Also contacts the side surface of the semiconductor region. The lower surface of the insulator 12 is
It is provided below the surface of the substrate 11. The side surface and the lower surface of the insulator 12 are in contact with the third semiconductor region 18. The first semiconductor region 13 is a signal storage unit that stores the signal electrons 24 obtained by photoelectric conversion. The conductor 16 is the signal storage unit 13
Field-effect transistor FET1 that discharges signal electrons from the
Of the gate electrode. The second semiconductor region 39 is a channel region of the transistor FET1. In the conductor 16 that is the gate electrode, the convex portion 28 has the maximum gate length. The convex portion 28 is a protrusion. Conductor 1 that is the gate electrode
6, the convex portion 28 of the conductor 16 is provided at the center of the section that defines the gate width. The third semiconductor region 18 is provided below the convex portion 28. The side surface of the third semiconductor region 18 may be disposed below the side surface of the convex portion 28.

FIG. 14E shows the IV-I of FIG. 14D.
FIG. 7 is a potential distribution diagram when electric signals between V are accumulated. The potential 23 has a gradient in the peripheral portion of the first semiconductor region 13 that joins with the third semiconductor region 18. Due to this gradient, the signal electrons 31
Moves in the direction of arrow 36. The signal electron 31 is the first
Collected in the center of the semiconductor region.

In the pixel 5 of the solid-state image pickup device 1 according to Example 1 of the second embodiment, the third semiconductor region 18 serving as the surface shield layer (PDp) of the photodiode PD, the gate electrode 16, and particularly, It is provided below the convex portion 28 of the gate electrode 16. As a result, the depletion layer of the first semiconductor region 13 of the signal accumulating portion (PDn) is in contact with the damaged layer generated by the reactive ion etching (RIE) or the like in the dry etching process such as the formation of the gate electrode 16. Disappears. It is possible to prevent an increase in local leakage current due to the damaged layer, that is, the occurrence of so-called white scratches. Further, it is possible to reduce the occurrence of unevenness in the dark.

Regarding the reading of the signal charge, the signal storage portion 13 and the surface shield layer 18 are offset below the convex portion 28, and the gate electrode 16 is provided above the signal storage portion 13 without the surface shield layer 18 interposed therebetween. , 28 exist, it is possible to completely transfer the signal electrons to the signal detection unit 14.

A method of manufacturing the solid-state imaging device 1 according to Example 1 of the second embodiment will be described. FIG. 15A is a top view of a part of the pixel 5 of the solid-state imaging device 1. Figure 15
15B to 15F are cross-sectional views taken along the line I-I of FIG. 15A.

First, as shown in FIG. 15B, a LOCOS or STI insulator 1 for element isolation is provided inside the silicon substrate 11.
Form 2. Next, the p-type semiconductor layer 33 for element isolation is formed. The signal storage region 13 is formed by ion implantation.

Next, as shown in FIG. 15C, the surface shield layer 34 is formed. By forming the p-type semiconductor layer 33 and the surface shield layer 34, the third semiconductor region 1
8 is completed. After this, steps such as annealing may be performed. Further, the channel implantation layer 39 is formed. In parallel, element isolation regions that form the transistors of the peripheral circuit,
Ion implantation is performed to control the threshold value of the transistor.

As shown in FIG. 15D, the gate insulating film 15 and the gate electrode 16 or the gate wiring are formed.

As shown in FIG. 15E, the source / drain regions of the detector 14 and the peripheral circuit are formed.

As shown in FIG. 15F, the punch-through prevention area 29 is formed.

By this manufacturing method, the signal storage / transfer regions 13 and 39 can be formed under the gate electrode 16. Further, the surface shield layer 34 that prevents depletion of the silicon surface can be formed under the gate electrode 16.

The gate electrode 16 is the gate electrode 16
The protrusion of the convex portion 28 is also formed at the time of forming. This convex portion 28
Are formed on the moving path for reading out the signal electrons. Then, the convex portion 28 may be formed thicker as it goes in the moving direction for reading out the signal electrons.

The surface shield layer 34 may be formed except the region where the convex portion 28 is formed. Surface shield layer 34
May be formed excluding a region serving as a movement path for reading out the signal electrons. The surface shield layer 34 may be formed such that the width of the surface shield layer 34 that is not formed increases toward the charge transfer path of the read path, and the opening area increases in the direction of the detection unit 14.

(Modification of Example 1 of the Second Embodiment)
As shown in FIGS. 16A and 16B, the pixel 5 of the solid-state imaging device 1 according to the modification of Example 1 of the second embodiment has the same structure as that of FIGS. 14A to 14C. In addition to the above, a lens 35 is further provided. Lens 35
The optical axis of is coincident with the perpendicular line L7 to the substrate surface passing through the center C of the region excluding the region below the convex portion 28 from the first semiconductor region 13. The lens 35 includes the third semiconductor region 33,
It is provided above 34 (18). As a result, the light incident path can be further expanded.

Example 2 of Second Embodiment The structure of the pixel 5 of the solid-state imaging device 1 according to Example 2 of the second embodiment is shown in FIGS. 17 (a) to 17 (c). FIG. 17 (b)
FIG. 18A is a cross-sectional view taken along the line I-I of FIG. FIG. 17
17C is a sectional view taken along line II-II in FIG. Solid-state imaging device 1 according to Example 2 of the second embodiment
Of the pixel 5 of the third semiconductor region 1 and the convex portion 28 of the gate 16.
The distance 8 is larger than the film thickness of the insulating film 15, which is different from Example 1 of the second embodiment. Therefore, it is considered that the signal electrons can be easily injected into the channel 39.

The pixel 5 of Example 2 of the second embodiment is
An offset is provided between the surface shield layer 18 and the gate electrode 16. In the area where this offset exists, the second transistor that controls the threshold value of the read transistor FET1
A semiconductor region 39 is provided. Second semiconductor region 39
Prevents depletion of the silicon substrate surface in the region where the offset exists. This offset facilitates the formation of a movement path when reading the signal charge. Even if the voltage applied to the gate 16 is lower, the signal charges can be completely read out. The signal electrons collected along the arrow 36 are
7 to the signal detection unit 14 via the area 39.

The impurity concentration of the signal storage region 13 is desired.
Ku 10¹⁶-10¹⁷cm^-3It is a degree. Signal storage
The diffusion layer depth of the product region 13 is preferably 0.3 to 1.0 μm.
Yes. The impurity concentration of the surface shield layer 18 is 10¹⁸cm
^-3A degree is preferable. Diffusion layer depth of surface shield layer 18
Is preferably about 0.1 to 0.2 μm. Channel forming part 39
Impurity concentration of 10¹⁷cm^-3A degree is preferable. Absence
The film thickness of the silicon oxide film of the edge film 15 is preferably 80 n.
It is about m. Surface shield layer 18 and read transistor
Offset distance between the ends of the gate electrodes 16 and 28 of the FET 1
The separation is in the signal transfer path direction 37, preferably 0.1 to 0.3 μ.
m, about 0.1 to 0.3μ in the direction perpendicular to the signal transfer path.
m. Length of the convex portion 28 of the read transistor FET1
The thickness is preferably about 0.3 μm. The width of the convex portion 28 is
It is about 0.4 μm. Opening end of surface shield layer 18
And the gate electrodes 16 and 2 of the read transistor FET1
The edge of 8 is the plane distance from above, and is preferably 0.1
It is about 0.3 μm. Ion implantation of signal storage unit 13
For example, the impurity is phosphorus (P), the acceleration voltage is 320 kV,
Dose amount 1.35 × 10¹²cm^-2The degree. Surface
The ion implantation of the region 34 of the shield layer 18 is performed by, for example, impure
The material is boron (B), the acceleration voltage is 15kV, the dose is 1.0 ×
10^Thirteencm^-2Done as a degree. Channel threshold
The ion implantation of the region 39 that determines the
Elementary, acceleration voltage 15kV, dose 2.0x10 ¹²cm
^-2It is a degree. Element isolation region of the surface shield layer 18
The ion implantation of 33 is performed by using, for example, boron as an impurity and accelerating charge.
Pressure is 140kV, Dose is 5.0 × 10¹²cm^-2Degree
The impurity is boron, the acceleration voltage is 80kV, and the dose is 7.0.
× 10^{1 Two}cm^-2It is a degree.

FIG. 18A shows the line III- of FIG. 17B.
It is a potential distribution map at the time of accumulating an electric signal between III. FIG.
17B is a potential distribution diagram at the time of reading an electric signal between III and III in FIG. 17B. FIG. 18C is the same as FIG.
It is a potential distribution diagram at the time of electric signal accumulation between IV-IV of (c). FIG. 18D is a potential distribution diagram at the time of reading an electric signal between IV and IV in FIG. 17C.

At the time of signal storage, as shown in FIG. 18A, signal electrons are stored in the storage layer 13 by the potential of the region of the p-type semiconductor substrate 11 sandwiched between the storage layer 13 and the read channel 39. It is stored. As shown in FIG. 18C, the signal electrons generated in the peripheral portion of the storage layer 13 move to the central portion of the storage layer 13 and are stored therein. Signal electrons do not easily exist in the peripheral area.

At the time of reading a signal, as shown in FIG. 18B, a positive potential is applied to the read gate 16, so that the potential of the channel 39 below the read gate 16 becomes high. The potential of the region of the p-type semiconductor substrate 11 sandwiched between the regions 13 and 39 increases accordingly,
All the signal electrons of the signal storage unit 13 are read out to the signal detection unit 14 in the direction of arrow 37. A signal electron readout path is created. Since there are no residual electrons, noise such as thermal noise and afterimage does not occur. As shown in FIG. 18D, the storage layer 1
The signal electrons generated in the peripheral portion of No. 3 move to the central portion of the storage layer 13, and the signal electrons do not easily exist in the peripheral portion, so that the signal electron read path does not easily exist.

(Modification 1 of Example 2 of the Second Embodiment) A pixel 5 of a solid-state image pickup device 1 according to Modification 1 of Example 2 of the second embodiment is shown in FIGS. Although it has the same structure as (c), the shapes of the third semiconductor region 18 and the second semiconductor region 39 are different as shown in FIG.

The pixel 5 of the solid-state image pickup device 1 according to the first modification of the second embodiment of the second embodiment is arranged in the direction of the signal readout path 37, from the signal storage region 13 toward the gate electrode 16. The width of the opening of the surface shield layer 18 is widened. Since the opening width of the surface shield layer 18 expands along the read path 37, as the distance from the signal detection unit 14 increases,
The potential of the signal reading path 37 becomes deeper, and the signal charges can be completely transferred at a low gate voltage.

(Modification 2 of Example 2 of the Second Embodiment) A pixel 5 of a solid-state imaging device 1 according to Modification 2 of Example 2 of the second embodiment is shown in FIGS. It has a structure similar to that of FIG. 19C, but as shown in FIG.
The shape of 8 is different.

The pixel 5 of the solid-state image pickup device 1 according to the second modification of the second embodiment of the second embodiment is in the direction of the signal readout path 37 from the signal storage region 13 toward the gate electrode 16. The width of the convex portion 28 of the read transistor FET1 is widened. Since the gate width widens along the signal read path 37, the modulation from the gate electrode 16 is more likely to be effective on the signal read path 37 as the gate width becomes closer to the detection unit 14. It is possible to completely transfer the signal charge at a low gate voltage.

(Modification 3 of Example 2 of the Second Embodiment) A pixel 5 of a solid-state image pickup device 1 according to Modification 3 of Example 2 of the second embodiment is shown in FIGS. It has a structure similar to that of FIG. 19C, but as shown in FIG.
8. The shapes of the third semiconductor region 18 and the second semiconductor region 39 are different.

The pixel 5 of the solid-state image pickup device 1 according to the third modification of the second embodiment of the second embodiment is in the direction of the signal readout path 37 from the signal storage region 13 toward the gate electrode 16. The width of the opening of the surface shield layer 18 is widened, and the width of the convex portion 28 of the read transistor FET1 is widened. As a result, the effects of Modifications 1 and 2 of Example 2 of the second embodiment can be obtained together. It is possible to completely transfer the signal charge at a lower gate voltage.

(Modification 4 of Example 2 of the Second Embodiment) A pixel 5 of a solid-state image pickup device 1 according to Modification 4 of Example 2 of the second embodiment is as shown in FIG. It has a similar structure, but as shown in FIG.
8 and the second semiconductor region 39 have different shapes and have a semicircular shape.

The pixel 5 of the solid-state image pickup device 1 according to the first modification of the second embodiment of the second embodiment is arranged in the direction of the signal readout path 37, from the signal storage region 13 toward the gate electrode 16, The width of the opening of the surface shield layer 18 is widened, and the opening forms a semicircle. As a result, the same effect as that of Modification 1 of Example 2 of the second embodiment can be obtained. Further, the electric field distribution in the vicinity of the opening becomes uniform, and the occurrence of white scratches can be reduced.

(Fifth Modification of Second Embodiment of Second Embodiment) The pixel 5 of the solid-state imaging device 1 according to the fifth modification of the second embodiment of the second embodiment is as shown in FIG. Although it has a similar structure, as shown in FIG. 20B, the shape of the convex portion 28 is different and has a semicircular shape.

The pixel 5 of the solid-state image pickup device 1 according to the fifth modification of the second embodiment of the second embodiment is in the direction of the signal read path 37 from the signal storage region 13 toward the gate electrode 16. The width of the convex portion 28 of the read transistor FET1 is widened, and the convex portion 28 has a semicircular shape. As a result, the same effect as that of the second modification of the second example of the second exemplary embodiment can be obtained. Further, the electric field distribution in the vicinity of the opening becomes uniform, and the occurrence of white scratches can be reduced.

(Modification 6 of Example 2 of the Second Embodiment) A pixel 5 of a solid-state image pickup device 1 according to Modification 6 of Example 2 of the second embodiment is as shown in FIG. Although it has a similar structure, as shown in FIG. 20C, the convex portion 28, the third semiconductor region 18 and the second semiconductor region 39 have different shapes and each has a semicircle.

The pixel 5 of the solid-state image pickup device 1 according to the modification 6 of the example 2 of the second embodiment is directed in the direction of the signal read path 37 from the signal storage region 13 toward the gate electrode 16. The width of the opening of the surface shield layer 18 is widened and the opening forms a semicircle. The width of the convex portion 28 of the read transistor FET1 is widened and the convex portion 28 has a semicircular shape. As a result, the same effect as that of Modification 3 of Example 2 of the second embodiment can be obtained. Further, the electric field distribution in the vicinity of the opening becomes uniform, and the occurrence of white scratches can be reduced.

(Modification 7 of Example 2 of the Second Embodiment) The pixel 5 of the solid-state imaging device 1 according to Modification 7 of Example 2 of the second embodiment is shown in FIGS. (C) and FIG.
Although it has the same structure as 1 (a), the position of the opening of the third semiconductor region 18 with respect to the first semiconductor region 13 is different as shown in FIG. 21 (b). Similarly, the second semiconductor region 39
The position of the convex part of is different. Similarly, the position of the convex portion 28 of the conductor 16 is different. Also by this, the same effect as that of Example 2 of the second exemplary embodiment can be obtained.

(Modification 8 of Example 2 of the Second Embodiment) The pixel 5 of the solid-state imaging device 1 according to Modification 8 of Example 2 of the second embodiment is shown in FIGS. (C) and FIG.
Although it has the same structure as 1 (a), the position of the opening of the third semiconductor region 18 with respect to the first semiconductor region 13 is different as shown in FIG. 21 (c). Similarly, the second semiconductor region 39
The position of the convex part of is different. Similarly, the position of the convex portion 28 of the conductor 16 is different. Also by this, the same effect as that of Example 2 of the second exemplary embodiment can be obtained.

FIG. 22A shows a solid-state image pickup device 1 according to Example 2 and Modifications 1 to 6 of the second embodiment, in which a pixel 5 having a white defect with respect to the peripheral length of the gate of the convex portion 28 is generated. Is the number of From this, it can be seen that the smaller the peripheral length of the gate of the convex portion 28, the less likely white scratches occur. The solid-state imaging device 1 does not operate when the peripheral length of the gate of the convex portion 28 is set to zero.

FIG. 22B is also the solid-state image pickup device 1 according to Example 2 and Modifications 1 to 6 of the second embodiment, in which the number of pixels 5 having white defects with respect to the gate area of the convex portion 28 is large. Is. From this, it is understood that the smaller the gate area of the convex portion 28 is, the less the white scratches are generated. The solid-state imaging device 1 does not operate when the gate area of the convex portion 28 is set to zero. From the above results, it was found that the shape of the convex portion 28 in which white scratches are unlikely to occur is a shape having a small gate peripheral length and a small gate area. That is, the convex portion 28
The shape of is preferably a semicircle as shown in FIGS.

Example 3 of Second Embodiment The structure of the pixel 5 of the solid-state imaging device 1 according to Example 3 of the second embodiment is shown in FIGS. 23 (a) to 23 (c). FIG. 23 (b)
FIG. 24 is a sectional view taken along line II of FIG. 23 (a). FIG. 23
23C is a sectional view taken along line II-II of FIG. Solid-state imaging device 1 according to example 3 of the second embodiment
The pixel 5 is different from Example 2 of the second embodiment in the structure of the first semiconductor regions 13 and 38. As a result, the injection of the signal electrons into the channel 39 can be similarly facilitated, and the dark current can be reduced.

The pixel 5 of Example 3 of the second embodiment is
Below the gate electrode 16, there is a convex portion 38 forming a part of the signal storage portions 13 and 38. By providing the convex portion 38, the depth of the signal storage unit 13 can be made deeper in the substrate 11. Therefore, the position of the depletion layer extending from the signal storage unit 13 can be formed deeper in the substrate 11. This is also clear from the fact that the position of the pn junction can be increased from the depth d1 to the depth d2, as shown in FIG. Since it is difficult for the charge generated due to the damage in the dry process of the gate processing process to be taken into the depletion layer of the signal storage region 13, noise generation is suppressed. On the other hand, in the vicinity of the convex portion 38, since the same potential distribution as that of Example 2 of the second embodiment is provided, the signal electrons can be read with the same low gate voltage.

(Third Embodiment) In the solid-state image pickup device 1 including the CMOS sensor, the first semiconductor region 13 of the n-type diffusion layer forming the photodiode PD for photoelectric conversion.
And a third semiconductor region 18 of the p-type diffusion layer. Area 1
3 and 18 are photodiodes P as shown in FIG.
It is formed by ion implantation 46 self-aligned with the gate electrode 16 of the read MOS transistor FET1 adjacent to D. Silicon substrate 1 of these diffusion layers 13 and 18
The depth from the surface of 1 is formed at a position much deeper than the source / drain (S / D) diffusion layer of a normal CMOS device. However, when the CMOS sensor is manufactured according to the standard CMOS manufacturing process like the CMOS sensor, the gate electrode of the CMOS sensor becomes thinner as the CMOS sensor becomes finer. As a result, the read gate electrode 16
Also reduce the thickness of. If the diffusion layers 13 and 18 are to be formed in the thinned read gate electrode 16 in a self-aligned manner, the ion species penetrate through the gate electrode 16 during the ion implantation 46 and ion species penetrate into the channel portion 45 of the read gate 16. Will end up. The threshold value of the read transistor FET1 changes.

In the pixel 5 included in the solid-state imaging device 1 according to the third embodiment, as shown in FIGS. 25A and 25B, even if the gate electrode 16 has a small thickness, the first semiconductor region 13 has a small thickness. Can be provided deeply and in self-alignment with the gate electrode 16. The fourth semiconductor region 14 is shallow,
Moreover, it can be provided in a self-aligned manner with respect to the gate electrode 16. 25B is a cross-sectional view taken along the line I-I of FIG.

Conventionally, the thickness of the gate electrode is increased to 300
Even if the depth is up to 400 nm, the depth of the first semiconductor region 13 is
It was at most 200 to 300 nm. In the third embodiment, the depth of the first semiconductor region 13 is 400 to 700 n even if the thickness of the gate electrode is thin and 200 to 300 nm.
It was m. The depth of the first semiconductor region 13 is
Depending on the performance of the resist used for ion implantation,
It does not depend on the thickness of the gate electrode 16. The depth can be increased depending on the resist forming conditions.

A method of manufacturing the solid-state image pickup device 1 according to the third embodiment will be described. In the third embodiment, the pattern formation of the read gate electrode 16 is performed by pattern etching twice. In the first pattern etching, the gate electrode 1
A pattern in which the pattern of 6 and the pattern of the photodiode PD are combined is used. The pattern of the second pattern etching is used as the pattern of the photodiode PD. A second pattern etching is performed. Ion implantation is performed using the photoresist as a mask without stripping the photoresist. By this ion implantation, the photodiode P
The n-type diffusion layer 13 or the p-type diffusion layer 18 forming D is formed.

That is, as shown in FIGS. 26A and 26B, the gate insulating film 15 is formed on the substrate 11. FIG. 26
FIG. 26B is a sectional view taken along the line I-I of FIG.
A polycrystalline silicon film 47 to be the gate electrode 16 is deposited on the gate insulating film 15. Photoresist patterns 48, 49 and 50 are formed on the polycrystalline silicon film 47. The pattern 48 is a pattern of the photodiode PD. The patterns 49 and 50 are the gate electrodes 16 and 1.
9 to 21 patterns. The patterns 48 and 49 are integrated. Next, the first pattern etching is performed. The polycrystalline silicon film 47 is etched. By the first pattern etching, the integrated patterns 47 and 16 of the polycrystalline silicon film and the gate electrodes 19 to 21 are formed. The resist 49 is peeled off.

As shown in FIGS. 27A and 27B, ion implantation is performed using the patterns 47 and 16 and the gate electrodes 19 to 21 as masks to form the fourth semiconductor region 14 and the sixth semiconductor region 2.
9 is formed. A resist film 52 is formed on the polycrystalline silicon pattern 16, the gate electrodes 19 to 21, and the substrate 11. The resist film 52 forms an opening 51 on the pattern 47 so as to overlap the pattern 47. The pattern of the opening 51 is the same as the pattern of the photodiode PD. 27B and 27C are cross-sectional views taken along the line II of FIG. 27A.

As shown in FIG. 27C, the second pattern etching is performed. The polycrystalline silicon film 47 is etched. The gate electrode 16 is formed by the second pattern etching. Ion implantation 53 is performed using the resist film 52 as a mask. The first semiconductor region 13 and the third semiconductor region 18 are formed. The resist film 52 is peeled off. The exposed polycrystalline silicon surface of the gate electrodes 16 and 18 to 21 is oxidized.

According to the manufacturing method of the third embodiment, 2
The resist film 52 used for the second pattern etching is left, and the photodiode PD is ion-implanted using the resist film 52 as a mask. Since the resist film 52 is used as a mask, ions do not penetrate the gate electrode 16 and reach the silicon substrate 11 even if ions are implanted deeper than usual.

(Fourth Embodiment) In a solid-state image pickup device, an antireflection film is formed for the purpose of improving photosensitivity. CMOS sensors have recently been used as solid-state image pickup devices.
It is attracting attention for its low power consumption and single power supply drive. CMOS
In the sensor, since the height of the metal film that defines the opening of the irradiation light is high, even if the irradiation light is defined by the metal film, the optical path is likely to widen before the irradiation light reaches the photodiode PD. As a result, the photosensitivity is unlikely to increase. CMOS
Since the sensor transfers the signal charge through a wiring made of polysilicon or the like, a metal film structure that defines an opening is formed above the wiring. Then, the metal film defining the opening is arranged at a high position.

In the fourth embodiment, an amplification type solid-state image pickup device having means for condensing the irradiation light on the photodiode PD will be described. Then, a solid-state imaging device with improved light sensitivity is provided.

Example 1 of Fourth Embodiment As shown in FIGS. 28A to 28D, the solid-state imaging device 1 according to the fourth embodiment includes pixels CB, CR, and CG. Have 28B is a cross-sectional view taken along the line I-I of FIG. FIG. 28 (c) shows II-II of FIG. 28 (a).
It is sectional drawing of a direction. 28D is a cross-sectional view taken along the line III-III of FIG. Pixels CB, CR,
The CG constitutes the pixel array 2 of FIG. Pixels CB, C
The R and CG have a semiconductor substrate 11 of the first conductivity type. The lower surface of the insulator 12 is provided below the surface 11 of the substrate 11. The side surface of the insulator 12 contacts the substrate 11. The second conductivity type first semiconductor region 13 is separated from the surface of the 11 substrate,
It is provided inside the substrate 11. The side surface of the first semiconductor region 13 faces the side surface of the insulator 12 via the substrate 11. The silicon oxide films 52 to 54 are provided on the substrate 11 and above the first semiconductor region 13. The silicon nitride films 55 to 57 (antireflection film: Si3N4) are provided on the silicon oxide films 52 to 54. The total thickness of the silicon nitride films 55 to 57 and the silicon oxide films 52 to 54 above the first semiconductor region 13 is thicker than 600Å. The silicon nitride films 55 to 57 are the silicon oxide film 5
The refractive index is different from 2 to 54.

The pixel CB is, as shown in FIG.
Silicon nitride film 55 above the first semiconductor region 13
The total thickness T2B and the thickness T1B of the silicon oxide film 52 is greater than 600Å.

The pixel CR is, as shown in FIG. 28 (c),
Silicon nitride film 56 above the first semiconductor region 13
The total thickness T2R and the thickness T1R of the silicon oxide film 53 is greater than 700Å.

The pixel CG is, as shown in FIG.
Silicon nitride film 57 above the first semiconductor region 13
Of the total thickness T2G and the thickness T1G of the silicon oxide film 54 are thicker than 650Å.

The gate electrodes 16 and 1 are formed on the silicon substrate 11.
9 to 21 are provided. The first semiconductor region serving as a signal storage portion of the photodiode PD is formed by patterning using a resist and implanting phosphorus (P) ions with an accelerator or the like.

In order to protect the photodiode PD,
Silicon oxide films 52 to 54 with a film thickness of 100 to 200 Å
Deposit to a degree. A preferable film thickness is about 150 to 200Å. As a result, the photosensitivity can be improved in the laminated structure of the silicon nitride films 55 to 57.
The silicon oxide films 52 to 54 are deposited by a chemical vapor deposition (CVD) method or the like. As the antireflection film, for example,
Silicon nitride film (Si3N4) films 55 to 57 are formed to a film thickness of 4
It is deposited by the CVD method in the range of about 00 to 700Å. Then, patterning is performed so that the resist remains in a region wider than the photodiode PD region by 0.2 μm, for example. Chemical dry etching (CDE: Chemical D)
The exposed silicon nitride films 55 to 57 are removed by a dry etching method or the like to form a desired antireflection film pattern. At this time, the total thickness of the oxide film on the photodiode PD and the film thickness of the antireflection film is 600Å
The above is preferable. The reason for this is that the antireflection film 5
The film thickness of 5 to 57 is an optimum film thickness of about 500 to 600 Å for a wavelength of green (G) light of 550 nm, and
This is because the oxide films 52 to 54 on the photodiode PD need to have a film thickness of 100 Å or more. The reason why the oxide film thicknesses 52 to 54 on the PD are required to be 100 Å or more is that the CDE
When patterning the antireflection films 55 to 57 with, even if processing is performed under the condition that the etching selection ratio between the antireflection films 55 to 57 and the oxide films 52 to 54 on the photodiode PD cannot be secured sufficiently (one digit or more). Oxide films 52 to 54
This is because damage to the bottom can be prevented.

When the antireflection films 55 to 57 are formed, the antireflection film 55 is provided for each of the pixels CB, CR and CG.
To 57 by changing the film thickness of each RGB pixel CB, CR, C
Antireflection film thickness T2 where sensitivity is highest in G
It is also possible to have B, T2R, and T2G. As a forming method, a silicon nitride film having a film thickness of 400 to
Deposit about 500Å, preferably about 450Å. Then, for the blue (B) pixel CB, the silicon nitride film is patterned by the CDE method. Again, a silicon nitride film with a film thickness of about 500 to 600 Å, preferably 550 Å
Deposit to a degree. Then, regarding the green (G) pixel CG,
Patterning of the silicon nitride film is performed by the CDE method. Further, a silicon nitride film is deposited to a film thickness of about 600 to 700Å, preferably about 650Å. Then, for the red (R) pixel CR, the silicon nitride film is patterned by the CDE method. By these things RGB
The antireflection films 55 to 57 can be formed with different thicknesses for each pixel. By forming the antireflection films 55 to 57, the photosensitivity of RGB can be improved, so that the photodiode PD is not irradiated with light of another color in each of the pixels CB, CR, and CG.
Color mixing can also be reduced.

Example 2 of Fourth Embodiment The pixel 5 of the solid-state image pickup device 1 according to Example 2 of the fourth embodiment is
As shown in FIGS. 29A to 29D, not only does it have a structure similar to that of FIGS. 28A to 28D of the first embodiment of the fourth embodiment, but also a silicon nitride film 58. Through 6
The width of 0 is narrower than the distance between the side surfaces of the insulator 12. And
The width of the silicon nitride films 58 to 60 is equal to the width of the first semiconductor region 1
Wider than 3. The region where the antireflection films 58 to 60 are formed is wider than the end of the first semiconductor region 13 and narrower than the end of the element isolation region 12.

In Example 2 of the fourth embodiment, photodiodes PD up to the photodiode PD are formed as in Example 1 of the fourth embodiment. After that, the silicon oxide films 52 to 54 and the silicon nitride films 55 to 57 are formed in the same manner as in Example 1 of the fourth embodiment, as shown in FIGS. Resist patterns 61 to 63 are formed on the silicon nitride films 55 to 57. FIG. 30 (d)
Through (f), silicon nitride films 55 through 57
Is pattern-etched to be a region wider than the photodiode PD (first semiconductor region 13) on the one side by about 0.1 μm or more. Antireflection films 58 to 60 are formed. The reason why the antireflection films 58 to 60 are formed in a region wider than the photodiode PD is that side etching occurs during processing by the CDE method. Therefore, when the antireflection films 58 to 60 are left by patterning, it is necessary to provide a width twice or more the film thickness T2B, T2R, and T2G. With this width, not only side etching by the CDE method, but also irradiation light in a wide range in which the expansion of the depletion layer and the refraction of light are taken into consideration becomes possible. Also, due to this width, misalignment in patterning is unlikely to occur.

The upper limit of the antireflection films 58 to 60 formed in a region wider than the photodiode PD is preferably up to the boundary of the element isolation region 12. The reason is that stress is likely to occur at the end of the element isolation region 12 when the element isolation region (LOCOS) is formed. This is to prevent crystal defects from occurring in the substrate 11 due to the stress at the edges of the element isolation region 12 and the stress of the silicon nitride films 58 to 60.

Example 3 of Fourth Embodiment A solid-state imaging device 1 according to Example 3 of the fourth embodiment is shown in FIG.
As shown in (a), it has pixels C1 and C2. 31B is a cross-sectional view taken along the line I-I of FIG. The pixels C1 and C2 form the pixel array 2 of FIG. The pixel array 2 has a first conductivity type semiconductor substrate 11. The lower surface of the insulator 12 is provided below the surface of the substrate 11. The side surface of the insulator 12 contacts the substrate 11. The first semiconductor region 13 of the second conductivity type is provided inside the substrate 11 apart from the surface of the substrate 11. The side surface of the first semiconductor region 13 faces the side surface of the insulator 12 with the substrate 11 in between. The silicon oxide region 66 is the first semiconductor region 13
Is provided above. The silicon oxide region 66 has a concave surface above the first semiconductor region 13. The silicon nitride region 67 is provided above the first semiconductor region 13. The silicon nitride region 67 has a convex surface above the first semiconductor region 13 that corresponds to the concave surface of the silicon oxide region 66. The conductors 65 and 64 are provided on the sides of the silicon oxide region 66 and the silicon nitride region 67. The conductors 65 and 64 are metal films such as aluminum alloys. Silicon nitride region 6
7 has a refractive index different from that of the silicon oxide regions 66 and 30 which will be the interlayer film. This allows the silicon nitride region 67 to have a convex lens effect. The conductors 65 and 64 define a space between the conductors 65 and 64 as an opening for irradiation light. A silicon nitride region 67 having a convex lens effect is formed at substantially the same height as this opening.

In Example 3 of the fourth embodiment, the interlayer film materials 30 and 66 and the material 67 having a different refractive index are used for the purpose of focusing light between the metal film that defines the opening of the irradiation light and the photodiode PD. Form a convex lens. That is, the gate electrodes 16, 19 to 21 and the photodiode PD are formed. An interlayer insulating film 30 is deposited by about 4000 Å by a low pressure (LP) -CVD method or the like. Next, the conductors 65 and 6
6 is deposited by the sputtering method and pattern-etched by the RIE method. A so-called buried silicon oxide film 66 is deposited on the order of 1000 Å. A silicon nitride film 67 is deposited by, for example, 15000Å by the CVD method or the like. After this, chemical mechanical polishing (CM
The surface of the silicon nitride film 67 is flattened by the P) method or the resist etch back method. As a result, the silicon nitride film 67 has a large film thickness on the photodiode PD, and the silicon nitride film 67 has a small film thickness on the conductor 64 or the like, so that a convex lens convex downward can be formed.

Example 4 of Fourth Embodiment FIG. 32 shows a solid-state image pickup device 1 according to Example 4 of the fourth embodiment.
As shown in (a), it has pixels C1 and C2. 32B is a cross-sectional view taken along the line I-I of FIG. Solid-state imaging device 1 according to example 4 of the fourth embodiment
As shown in FIG. 32 (b), has the same structure as FIG. 31 (b) of Example 3 of the fourth exemplary embodiment. But,
It has a partially different structure. That is, the silicon oxide region 69 is provided above the first semiconductor region 13.
The silicon oxide region 69 has a concave surface above the first semiconductor region 13. The silicon nitride region 68 is provided above the first semiconductor region 13. The silicon nitride region 68 is
Above the first semiconductor region 13, there is a convex surface that matches the concave surface of the silicon oxide region 69. The conductors 65 and 64 are provided on the sides of the silicon oxide region 69 and the silicon nitride region 68. As a result, the silicon nitride region 68 can have a convex lens effect. The conductors 65 and 64 define a space between the conductors 65 and 64 as an opening for irradiation light. A silicon nitride region 68 having a convex lens effect is formed at substantially the same height as this opening.

In Example 4 of the fourth embodiment, the height is almost the same as that of the conductors 64 and 65 which define the openings, or
The in-layer lens is formed at a height lower than that. The formation method of Example 4 of the fourth embodiment is similar to that of Example 3 of the fourth embodiment, in which the gate electrode 16 and the like, the photodiode PD, and, if necessary, the antireflection film are formed. To do. The interlayer film 30 such as a silicon oxide film is formed by LP-
It is deposited by the CVD method or the like. The interlayer film 30 is flattened by a CMP method, a resist etch back (EB) method, or the like. As the conductors 64 and 65 defining the openings, for example, a metal film of aluminum (Al) or the like is deposited by a sputtering method or the like to have a film thickness of about 4000 Å.
Resist coating, resist patterning, patterning of the metal film by the RIE method or the like is performed. A conductor 6 that removes the metal film in a desired area, secures an opening area, and defines the opening
4 and 65 are formed. At this time, a step is formed on the surface by the thickness of the conductors 64 and 65. Here, the silicon nitride film 68 is deposited by, for example, the LP-CVD method or the like by a thickness corresponding to a film thickness smaller than the level difference between the conductors 64 and 65, for example, about 2000 Å. As a result, the conductor 6
Silicon nitride film 68 with a thickness of 2000Å on 4 and 65
Is deposited. However, in the openings of the conductors 64 and 65, the silicon nitride film 68 is hardly deposited at the end portions of the openings of the conductors 64 and 65 due to the shadowing of the silicon nitride film 68 at the time of film deposition, or the film thickness is reduced. Becomes thin. In the vicinity of the central portions of the openings of the conductors 64 and 65, the film thickness is approximately 2000 Å. As a result,
A convex lens of the silicon nitride film 68 can be formed in the openings of the conductors 64 and 65. After this, LP-CV
A silicon oxide film 69 is deposited by the D method or the like, and CMP is performed.
Method or a resist EB method.

Example 5 of Fourth Embodiment A solid-state image pickup device 1 according to Example 5 of the fourth embodiment is shown in FIG.
As shown in (a), it has pixels C1 and C2. 33B is a cross-sectional view taken along the line I-I of FIG. Solid-state imaging device 1 according to example 5 of the fourth embodiment
As shown in FIG. 33 (b), has the same structure as FIG. 32 (b) of Example 4 of the fourth exemplary embodiment. But,
It has a partially different structure. That is, the silicon oxide region 71 is provided above the first semiconductor region 13.
The silicon oxide region 71 has a concave surface above the first semiconductor region 13. The silicon nitride region 70 is provided above the first semiconductor region 13. The silicon nitride region 70 is
Above the first semiconductor region 13, there is a convex surface that matches the concave surface of the silicon oxide region 71. The conductor 16 is provided on the side of the silicon oxide region 71 and the silicon nitride region 70. This allows the silicon nitride region 70 to have a convex lens effect. The conductors 65 and 64 define a space between the conductors 65 and 64 as an opening for irradiation light. A silicon nitride region 70 having a convex lens effect is formed below the opening.

In Example 5 of the fourth embodiment, the intralayer lens is formed at a height lower than that of the conductors 64 and 65 which define the openings. The formation method of Example 5 of the fourth embodiment is similar to that of Example 3 of the fourth embodiment, in which the gate electrode 16, the photodiode PD, and the antireflection film are formed if necessary. To do. At this time, the gate electrode 16,
The insulator 12 causes a step on the surface. Here, the silicon nitride film 70 is deposited to about 2000 Å.
As a result, a convex lens of the silicon nitride film 70 can be formed as in Example 4 of the fourth embodiment. After that, the silicon oxide film 7 is formed by the LP-CVD method or the like.
1 is deposited and flattened by the CMP method or the resist EB method. The conductors 64 and 65 that define the openings are formed into a film having a thickness of 4000.
Å Deposit about. The conductors 64 and 65 are patterned to form conductors 64 and 65 that define the openings. After that, the silicon oxide film 72 is formed by the LP-CVD method or the like.
Is deposited and planarization is performed by the CMP method or the resist EB method.

[0101]

As described above, according to the present invention, it is possible to provide a solid-state image pickup device in which thermal noise and dark current noise are less likely to occur, and the S / N ratio of a reproduction screen is less likely to deteriorate.

[Brief description of drawings]

FIG. 1 is a top view of a solid-state imaging device according to a first embodiment and a schematic diagram of pixels included in the solid-state imaging device.

FIG. 2 is a top view of a pixel included in the solid-state imaging device according to the first embodiment.

FIG. 3 is a cross-sectional view of a pixel included in the solid-state imaging device according to the first embodiment and an energy level diagram for explaining a basic operation.

FIG. 4 is a top view of a pixel included in the solid-state imaging device according to Example 1 of the first embodiment.

5A and 5B are a cross-sectional view of a pixel included in the solid-state imaging device according to Example 1 of the first embodiment, and an energy level diagram for explaining a basic operation.

FIG. 6 is a cross-sectional view of a pixel included in a solid-state imaging device according to Modification 1 and Modification 2 of Example 1 of the first embodiment.

7A and 7B are a cross-sectional view of a pixel included in the solid-state imaging device according to Example 2 of the first embodiment, and an energy level diagram for explaining a basic operation.

FIG. 8 is a cross-sectional view of a pixel included in a solid-state imaging device according to Modifications 1 and 2 of Example 2 of the first embodiment.

9A and 9B are a top view and a cross-sectional view of a pixel included in the solid-state imaging device according to Example 3 of the first embodiment.

FIG. 10 is a cross-sectional view of a pixel included in a solid-state imaging device according to Modifications 1 and 2 of Example 3 of the first embodiment.

11A and 11B are a top view and a cross-sectional view of a pixel included in the solid-state imaging device according to Example 4 of the first embodiment.

FIG. 12 is a cross-sectional view of a pixel included in a solid-state imaging device according to Modification 1 and Modification 2 of Example 4 of the first embodiment.

FIG. 13 is a top view of a pixel included in the solid-state imaging device according to Example 1 of the second embodiment.

FIG. 14 is a detailed top view, cross-sectional view, and energy level diagram of a pixel included in the solid-state imaging device according to Example 1 of the second embodiment.

15A and 15B are a top view and a cross-sectional view for explaining the manufacturing method of the pixel included in the solid-state imaging device according to the first example of the second embodiment.

FIG. 16 is a detailed cross-sectional view of a pixel included in a solid-state imaging device according to a modification of Example 1 of the second embodiment.

FIG. 17 is a detailed top view and cross-sectional view of a pixel included in the solid-state imaging device according to Example 2 of the second embodiment.

FIG. 18 is an energy level diagram of a pixel included in the solid-state imaging device according to Example 2 of the second embodiment.

FIG. 19 is a detailed top view of a pixel included in the solid-state imaging device according to Modifications 1 to 3 of Example 2 of the second embodiment.

FIG. 20 is a detailed top view of a pixel included in a solid-state imaging device according to Modifications 4 to 6 of Example 2 of the second embodiment.

FIG. 21 is a detailed top view of a pixel included in a solid-state imaging device according to Modifications 7 and 8 of Example 2 of the second embodiment.

FIG. 22 is a graph showing the shape dependence of the convex portion of the gate electrode on the number of pixels in which white defects are observed in the solid-state imaging device according to Example 2 of the second embodiment.

FIG. 23 is a detailed top view, cross-sectional view, and impurity concentration distribution diagram of a pixel included in the solid-state imaging device according to Example 3 of the second embodiment.

FIG. 24 is a cross-sectional view of a pixel included in a solid-state imaging device of a comparative example of the third embodiment.

25A and 25B are a top view and a cross-sectional view of a pixel included in the solid-state imaging device according to the third embodiment.

FIG. 26 is a top view and a cross-sectional view (No. 1) for explaining the method of manufacturing the pixel included in the solid-state imaging device according to the third embodiment.

FIG. 27 is a top view and a cross-sectional view (No. 2) for explaining the method of manufacturing the pixel included in the solid-state imaging device according to the third embodiment.

28A and 28B are a top view and a cross-sectional view of a pixel included in the solid-state imaging device according to Example 1 of the fourth embodiment.

29A and 29B are a top view and a cross-sectional view of a pixel included in the solid-state imaging device according to Example 2 of the fourth embodiment.

FIG. 30 is a cross-sectional view illustrating the method for manufacturing the pixel included in the solid-state imaging device according to Example 2 of the fourth embodiment.

31A and 31B are a top view and a cross-sectional view of a pixel included in a solid-state imaging device according to Example 3 of the fourth embodiment.

32A and 32B are a top view and a cross-sectional view of a pixel included in a solid-state imaging device according to Example 4 of the fourth embodiment.

33A and 33B are a top view and a cross-sectional view of a pixel included in a solid-state imaging device according to Example 5 of the fourth embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 2 Pixel array 3 Signal scanning circuit 4 Signal reading circuit 5 Pixel 11 p-type semiconductor substrate 12 Element isolation area 13 Photodiode (PD) signal storage section 14 Detection section (detect node, drain area of FET1) 15 FET1 Gate insulating film 16 FET1 gate electrode 17 active region 18 channel stopper and dark current suppressing region 19 FET4 gate electrode 20 FET3 gate electrode 21 FET2 gate electrode 22 n-type semiconductor region 23 conduction band 24 accumulated signal electrons 25 Moved Signal Electrons 26 p-Type Semiconductor Region 27 Distribution of Electrons Generated as Dark Current at Gate Electrode 28 Projection (Protrusion) 29 Punch Through Prevention Region 30 Interlayer Insulation Film 31 Electron 32 Element Separation Region 33 Channel Stopper Area 34 Dark current suppression area 35 Chrolenses 36, 37 Electron moving direction 38 Convex portion 39 Impurity region 40 PDp impurity concentration distribution 41 PDn (13) impurity concentration distribution 42 PDn (13 and 38) impurity concentration distribution 43 PDn (38) impurity concentration distribution 44 resist 45 impurity diffusion layers 46, 53 ion beam 47 polysilicon films 48, 49, 50, 52 resist 51 resist openings 52 to 54 silicon oxide films 55 to 60 silicon nitride films 61 to 63 resists 64, 65 metal wiring 66, 69, 71, 72 Silicon oxide film 67, 68, 70 Silicon nitride film FET1 Read transistor (transfer transistor) FET2 Reset transistor FET3 Amplification transistor FET4 Row selection transistor

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Yamashita             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Tetsuya Yamaguchi             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Hidetoshi Nozaki             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Hisanori Ihara             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Nagataka Tanaka             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Yuichiro Eki             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Masayuki Ayabe             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Yukio Endo             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Manabe Sohei             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F-term (reference) 4M118 AA02 AA05 AB01 BA14 CA03                       CA32 FA06 FA26 GD04                 5C024 CX32 CY47 EX43 GX03 GY31                 5F049 MA02 MB03 NA04 NA05 NB05                       RA02 SS03 SZ20 UA13 UA20

Claims (24)

[Claims] 1. A semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type provided inside the substrate away from a surface of the substrate, and the substrate including the surface of the substrate. A second semiconductor region of the second conductivity type that is provided apart from above the first semiconductor region, an insulating film provided on the second semiconductor region, and an insulating film provided on the insulating film. A conductor provided, and a bottom surface provided on the substrate including the surface of the substrate, the bottom surface of which contacts the top surface of the first semiconductor region, the side surface of which contacts the side surface of the second semiconductor region, and the distance from the conductor Is provided on the substrate including the third semiconductor region of the first conductivity type having a thickness equal to or larger than the thickness of the insulating film and the substrate including the surface of the substrate, and a side surface of the third semiconductor region is in contact with a side surface of the second semiconductor region. And the distance between the second conductive type A solid-state imaging device having four semiconductor regions. 2. The solid-state imaging device according to claim 1, wherein the distance between the conductor and the third semiconductor region is larger than the film thickness of the insulating film. 3. The semiconductor device according to claim 1, further comprising a fifth semiconductor region of the first conductivity type above the first semiconductor region and below the second semiconductor region. Solid-state imaging device. 4. The lower surface is provided below the surface of the substrate, and the side surface and the lower surface further include an insulator in contact with the third semiconductor region. The solid-state imaging device according to. 5. The depth from the surface of the substrate to the upper surface of the first semiconductor region is deeper than the depth from the surface of the substrate to the lower surface of the insulator. The solid-state imaging device described. 6. The solid-state imaging device according to claim 5, wherein the first semiconductor region is provided below the insulator. 7. The first semiconductor region is a signal storage unit that stores signal charges obtained by photoelectric conversion, and the conductor is a gate of a field effect transistor that discharges the signal charges from the signal storage unit. 7. The electrode according to claim 1, wherein the second semiconductor region is a channel region of the transistor.
Item 10. The solid-state imaging device according to item. 8. A first-conductivity-type semiconductor substrate, a second-conductivity-type first semiconductor region provided inside the substrate away from the surface of the substrate, and provided on the surface of the substrate. An insulating film formed on the insulating film, a conductor provided on the insulating film and having a convex portion provided above the first semiconductor region, and provided on the substrate including the surface of the substrate, the first semiconductor A third semiconductor region of the first conductivity type, which is provided above the region, is in contact with a side surface of the first semiconductor region, and is provided below the conductor, and is provided on the substrate including the surface of the substrate. , The second conductive type fourth semiconductor region having a distance from the conductor equal to the film thickness of the insulating film. 9. The fourth semiconductor region is provided on the substrate including the surface of the substrate, below the conductor, below the protrusion, and in contact with a side surface of the third semiconductor region. 9. The solid-state imaging device according to claim 8, further comprising a second semiconductor region of the second conductivity type that is in contact with a side surface of the solid-state imaging device. 10. The lower surface is provided below the surface of the substrate, and the side surface and the lower surface further include an insulator in contact with the third semiconductor region. Solid-state imaging device. 11. The first semiconductor region is a signal storage unit that stores signal charges obtained by photoelectric conversion, and the conductor is a gate of a field effect transistor that discharges the signal charges from the signal storage unit. It is an electrode, The solid-state imaging device of any one of Claims 8 thru | or 10 characterized by the above-mentioned. 12. The solid-state imaging device according to claim 11, wherein in the gate electrode, the gate length is maximum in the convex portion of the conductor. 13. The solid-state imaging device according to claim 8, wherein the convex portion is a protrusion. 14. The solid-state imaging device according to claim 11, wherein the convex portion of the conductor is provided at the center of a section that defines the gate width in the gate electrode. 15. The solid-state imaging device according to claim 8, wherein a distance between the convex portion and the third semiconductor region is larger than a film thickness of the insulating film. 16. The solid-state imaging device according to claim 8, wherein a side surface of the third semiconductor region is arranged below a side surface of the convex portion. 17. The solid-state imaging device according to claim 8, wherein the third semiconductor region is provided below the convex portion. 18. The solid-state imaging device according to claim 9, wherein the second semiconductor region is a channel region of the transistor. 19. An optical axis coincides with a perpendicular to the surface of the substrate passing through the center of the region excluding the region below the convex portion from the first semiconductor region, and is provided above the third semiconductor region. The solid-state imaging device according to any one of claims 8 to 18, further comprising a lens. 20. A semiconductor substrate of the first conductivity type, a lower surface of which is provided below the surface of the substrate, and a side surface of which is provided inside the substrate, away from an insulator contacting the substrate and the surface of the substrate. A second conductive type first semiconductor region whose side surface faces the side surface of the insulator through the substrate; a silicon oxide film provided on the substrate above the first semiconductor region; A solid-state imaging device comprising a silicon nitride film which is provided on a silicon oxide film and has a total film thickness above the first semiconductor region and a film thickness of the silicon oxide film of more than 600 Å. 21. The width of the silicon nitride film is narrower than the distance between the side surfaces of the insulator.
The solid-state imaging device according to 0. 22. The width of the silicon nitride film is the first
The solid-state imaging device according to claim 21, wherein the solid-state imaging device is wider than the width of the semiconductor region. 23. A semiconductor substrate of the first conductivity type, a lower surface of which is provided below the surface of the substrate, and a side surface of which is provided inside the substrate apart from an insulator contacting the substrate and the surface of the substrate. A second conductive type first semiconductor region having a side surface facing the side surface of the insulator through the substrate; And a second semiconductor region of the second conductivity type that faces the side surface of the insulator, and is provided inside the substrate away from the surface of the substrate, and the side surface is on the side surface of the insulator through the substrate. A second semiconductor region of the second conductivity type that opposes, a silicon oxide film provided on the substrate above the first to third semiconductor regions, and provided on the first silicon oxide film, The film thickness above the first semiconductor region and The total thickness of the silicon oxide film is provided on the first silicon nitride film and the second silicon oxide film having a total thickness of more than 600Å, and the film thickness above the second semiconductor region and the film thickness of the silicon oxide film. The total thickness of the silicon oxide film and the film thickness above the third semiconductor region is 70, which is provided on the second silicon nitride film and the third silicon oxide film whose total thickness is more than 650Å.
A solid-state imaging device having a third silicon nitride film thicker than 0Å. 24. A semiconductor substrate of a first conductivity type, a lower surface of which is provided below the surface of the substrate, and a side surface of which is provided inside the substrate away from an insulator contacting the substrate and the surface of the substrate. A second conductive type first semiconductor region whose side surface faces the side surface of the insulator via the substrate; and a concave surface provided above the first semiconductor region and above the first semiconductor region. A silicon oxide region, a silicon nitride region provided above the first semiconductor region and having a convex surface above the first semiconductor region, the convex surface corresponding to the concave surface, and laterally of the silicon oxide region and the silicon nitride region. A solid-state imaging device, comprising: a conductor provided.