JPH11284166A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow perfect transfer of the signal electric charge of a photo diode(PD) at a low voltage, even with a PD of entire depletion while the PD has surface shield structure. SOLUTION: A first conductive type well region 2 formed on a semiconductor substrate 1, a photo diode(PD) 3 comprising the well region 2 and a second conductive type surface shield region 6 formed on the well region 2, a read-out gate (TG) 4 part formed close to a first conductive type surface layer 6 formed at the upper part of a second conductive type region 7 of the PD 3, the second conductive type region 7 at the PD 3, and the PD 3 part, and a second conductive type drain region 5 (detection node part 10) formed close to the other of the TG 4 are provided to a unit cell part of a solid-state imaging device. Here, a first conductive type barrier layer 8 whose concentration is higher than the well region 2 is formed inside the substrate 1 under the TG 4, comprising the second conductive type region 7 of the PD 3 and a second conductive type through channel layer 9 formed under the TG 4 while adjoining the second conductive type region 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type solid-state imaging device, and more particularly to an improvement in the structure of a read transistor in a unit cell.

[0002]

2. Description of the Related Art A MOS solid-state imaging device (MOS image sensor) can be miniaturized, can be driven by a single power supply, and can be manufactured entirely by a MOS process including an imaging unit and peripheral circuits. In recent years, attention has been paid to the advantages of being able to configure a chip as one integrated circuit.

[0003] A number of techniques have been proposed for an amplifying MOS solid-state image pickup device (amplifying MOS image sensor) having an amplifying function inside a pixel. It is expected to be suitable for reducing the pixel size by increasing the number of pixels to respond and reducing the image size.

Further, the amplification type MOS image sensor consumes less power than the CCD image sensor, and can be easily integrated with other peripheral circuits using the same CMOS process as that of the sensor part, thereby reducing the cost. There is also a decisive advantage.

Here, an outline of the amplification type MOS image sensor will be described. That is, in the amplification type MOS image sensor, the cells constituting each pixel are formed on the same semiconductor substrate Su.
A configuration in which a photodiode as a photoelectric conversion element and a plurality of MOS transistors are arranged in parallel on b. Then, a potential is applied to a MOS transistor constituting the signal charge storage / readout unit with the signal charge generated by the photoelectric conversion by the photodiode, the MOS transistor is turned on, and the potential is provided for signal amplification inside the pixel. By providing a MOS transistor (amplifying transistor) to modulate the amplifying transistor, an amplifying function is provided inside the pixel.

The signal amplified by the amplifying transistor is read out via a horizontal address line to become an image signal at the pixel. A plurality of such unit cells are arranged in a matrix (two-dimensional matrix).

The MOS type solid-state imaging device is driven by a single power supply and consumes low power.
When a fully depleted photodiode is used as the photoelectric conversion unit because of low voltage driving such as 5 [V] or 3.3 [V], it is difficult to read out signal charges from the photodiode. However, it is difficult to perform full transfer reading.

In the MOS type solid-state imaging device, a photodiode portion forming a unit cell has a first conductivity type well and a second conductivity type well.
It is formed by forming a conductive type impurity region. A surface shield region of the first conductivity type impurity is formed on the second conductivity type impurity region. The impurity concentration of the second conductivity type region of the photodiode portion is determined by the impurity concentration of the well region and the surface shield region. It is at an intermediate level of impurity concentration in the area. In addition, since the second-conductivity-type impurity region of the photodiode needs to accumulate the electron charge generated corresponding to the amount of light received by the photodiode, the potential of the photodiode is 3.3 [V] or 5 [V].
It is necessary to set to a positive voltage such as.

However, in this case, the depletion layer always extends to the surface of the impurity region of the second conductivity type. However, when the depletion layer reaches the surface of the impurity region of the second conductivity type, the leak current increases and the darkness increases. Since the time unevenness is increased, it is necessary to design the highest impurity concentration in the surface shield region formed on the upper surface of the second conductivity type impurity region.

Therefore, such a structure of the surface shield is formed by completely depleting the impurity region of the second conductivity type of the photodiode, so that the impurity region of the second conductivity type of the photodiode corresponds to the amount of received light. The signal charges generated by the photoelectric conversion are accumulated in the semiconductor substrate 1 without being leaked. Then, the stored signal charges are read by a MOS read transistor that shares the second conductivity type impurity region of the photodiode as a source region.

A MOS-type read transistor sharing the second conductivity type impurity region of the photodiode as a source region has a gate electrode over the second conductivity type impurity region and the drain region. The signal charge stored in the second conductivity type impurity region of the photodiode is read by applying a signal to turn on the reading transistor.

However, in the case of the MOS-type solid-state imaging device having the above structure, the high-concentration surface shield region always extends below the gate of the readout transistor due to the heat treatment after the ion implantation in the semiconductor manufacturing process. Once in such a state, even if the gate of the read transistor is turned on, the potential under the gate cannot be made high due to the high-concentration first conductivity type surface shield layer.

Therefore, the signal charge generated in the second conductivity type impurity region of the photodiode cannot be read out by the readout transistor. With an np type photodiode which is not a complete readout, signal readout can be easily performed. Therefore, it is conceivable to use such a photodiode as the photoelectric conversion element of the unit cell, but this time, since the photodiode does not transfer completely, the dark current increases due to the residual charge. Problems arise.

Further, if the signal of the photodiode cannot be completely transferred and read, a capacitive image lag occurs in each pixel, which causes deterioration of image quality. Therefore, MOS
The solid-state imaging device has to adopt a structure in which the photodiode is completely depleted in the unit cell.

Therefore, development of a technique for completely reading out all generated signal charges from a completely depleted photodiode is desired in a MOS solid-state imaging device.

Further, not only in the MOS type but also in the CCD type solid-state imaging device, the current read voltage of 15 [V] is used.
However, there is a problem that it is difficult to perform complete transfer readout due to lower voltage and smaller cell size.

Therefore, the subject of the present invention is a technique relating to a CCD solid-state imaging device.
h, et al., “A 1 / 4-inch 38OkPixel IT ・ CCD Image S
ensorEmploying Gate -Assisted Punchthrough Read-
out Mode ”, IEEE TRANSACTIONS ON ELECTRON DEVICES, V
OL.42, NO.10, OCTOBER 1995.]
In the CD-type solid-state imaging device, there has been proposed a technique in which a signal of a photodiode formed in a deep portion of a semiconductor substrate is improved by devising a reading method.

In this example, the reduction of the saturation signal of the photodiode is improved by forming the photodiode deep in the semiconductor substrate, and the photodiode is formed deep in the semiconductor substrate. Thus, the saturation signal of the photodiode is increased, and the signal charge in the deep part of the substrate is improved by improving the readout gate.

In this example, the structure beneath the read gate adjacent to the photodiode is formed in the order of “p layer” / “p− layer” / “p layer” from the silicon oxide film interface side. In this mode, the readout is performed by punch-through with the voltage applied to the readout gate unit.

As described above, the decrease in the saturation signal of the photodiode is increased by forming the photodiode in the deep portion of the semiconductor substrate, thereby increasing the saturation signal of the photodiode, and reading the signal charge in the deep portion of the substrate via the read gate. In such a structure in which the surface of the photodiode is covered with a p-type shield layer, the reading of the signal charges of the photodiode formed inside the substrate is actually performed. Would be extremely difficult.

The reason is that, even if a voltage is applied to the gate, the fluctuation of the channel on the photodiode side is suppressed, and the signal of the photodiode is suppressed due to the surface shield layer formed in a self-aligned manner at the read gate end. This is because it becomes a barrier to electric charges.

The problem with the above surface shield is as follows.
In MOS-type solid-state imaging devices and CCD-type solid-state imaging devices, there is a problem that reading cannot be performed.
This is a major obstacle in promoting the reduction of the read voltage.

[0023]

The MOS type solid-state image pickup device can be driven by a single power supply and can operate with low power consumption, and is an element which is very economically advantageous as compared with the CCD type. However, when a part of the photodiode is used also as the source of the MOS transistor for reading, the impurity concentration in the second conductivity type impurity region of the photodiode is reduced due to the surface shield layer formed on the photodiode portion. And the impurity concentration of the surface shield region is at an intermediate level between the impurity concentration and the second conductivity type impurity region of the photodiode. , The potential of the photodiode is 3.3 [V] or
It must be set to a positive voltage such as 5 [V].

However, in this case, the depletion layer always extends to the surface of the impurity region of the second conductivity type. However, when the depletion layer reaches the surface of the impurity region of the second conductivity type, the leak current increases and the darkness increases. Since the time unevenness is increased, it is necessary to design the highest impurity concentration in the surface shield region formed on the upper surface of the second conductivity type impurity region.

Since such a structure of the surface shield is formed by completely depleting the second conductivity type impurity region of the photodiode, the second conductivity type impurity region of the photodiode is photoelectrically changed according to the amount of light received. The converted signal charges are accumulated in the semiconductor substrate 1 without being leaked.

The MOS-type read transistor sharing the second conductivity type impurity region of the photodiode as a source region has a gate electrode over the second conductivity type impurity region and the drain region. By applying a signal to the electrode to turn on the reading transistor, signal charges accumulated in the second conductivity type impurity region of the photodiode are read.

However, in the case of the MOS-type solid-state imaging device having the above structure, the high-concentration surface shield region always extends below the gate of the readout transistor due to the heat treatment after the ion implantation in the semiconductor manufacturing process. Once in such a state, even if the gate of the read transistor is turned on, the potential under the gate cannot be made high due to the high-concentration first conductivity type surface shield layer.

Therefore, the read transistor cannot read the signal charge generated in the second conductivity type impurity region of the photodiode. Therefore, an object of the present invention is to improve this point, and to improve 3.3 [V] or 5.0 even in a surface shield structure.
An object of the present invention is to provide a solid-state imaging device having a read-out transistor structure capable of completely transferring signal charges of a photodiode with a low power supply voltage such as [V].

[0029]

In order to achieve the above object, the present invention is configured as follows. That is, a photodiode portion including a first conductivity type well region formed on a semiconductor substrate, a second conductivity type region formed on the well region, and an upper portion of the photodiode portion over the second conductivity type region. A surface layer of the first conductivity type formed, and a second layer of the photodiode portion in the well region of the first conductivity type.
A second conductivity type drain region formed in the vicinity of the conductivity type region;
In a solid-state imaging device having a gate portion of a read transistor provided above the well region between the second conductivity type region and a second conductivity type drain region of the photodiode portion, Forming a first conductivity type barrier layer connecting the region with the deep portion, and protruding from the second conductivity type region of the photodiode portion between the first conductivity type barrier layer and the lower portion of the gate portion; A high-concentration second conductivity type channel configuration layer is provided.

Alternatively, the second part of the photodiode unit
Forming a first conductivity type barrier layer that connects the conductivity type region and the drain region of the second conductivity type in a deep portion, and further comprising the photodiode between the first conductivity type barrier layer and the lower portion of the gate portion; A channel configuration layer of the second conductivity type from the second conductivity type region of the portion to the drain region is provided.

Alternatively, a first conductivity type barrier layer formed adjacent to both the second conductivity type photodiode portion and the second conductivity type drain region is provided below a gate portion of the read transistor. A second conductive type through channel layer formed adjacent to both the second conductive type photodiode portion and the second conductive type drain region above the conductive type barrier layer, or 1
Instead of the conductivity type barrier layer, a structure was provided in which a second conductivity type barrier well having a higher concentration than the first conductivity type well layer was provided.

Alternatively, the first substrate formed on the semiconductor substrate
A photodiode portion including a conductivity type well region, a second conductivity type region formed on the well region, and a first portion formed above the second conductivity type region of the photodiode portion.
A conductive type surface layer, a second conductive type drain region formed near the second conductive type region of the photodiode portion in the first conductive type well region, and a second conductive type drain region formed between the drain region and the photodiode portion. In a solid-state imaging device having a gate portion of a read transistor provided above the well region between the two conductivity type regions, a part of the second conductivity type region of the photodiode is located below the gate portion of the read transistor. The structure reaches the interface with the oxide film.

By adopting such a structure, even if the photodiode portion has a surface shield structure, the readout transistor can operate normally and the signal of the photodiode can be completely read, and the surface shielded photodiode can be read. Signal charge of
A reading transistor structure which can be read with a low power supply voltage of 5 [V] or 3.3 [V] is obtained.

Therefore, according to the present invention, in a structure having a photodiode part in which a unit cell part is completely depleted and a transistor for reading out signal charges of the photodiode, a signal of the photodiode part which is completely depleted is completely read. And a solid-state imaging device having a readout transistor.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 shows a first embodiment of the present invention.

In this structure, for example, a first conductivity type well region 2 in which a p-type impurity is diffused is formed on a Si (silicon) semiconductor substrate 1. The impurity concentration of the well region 2 is as low as several E15 (E15 is 10 to the 15th power).

In a part of the well region 2, a region (PD-n) 7 for forming the photodiode 3 is formed in the well region 2 by implanting impurities of the second conductivity type. is there.

In the well region 2, a detection node portion made of impurities of the second conductivity type is located at a predetermined distance near the second conductivity type region (PD-n) 7 for forming the photodiode 3. (SD-n) 10 is formed, and a signal is stored on the semiconductor substrate 1 between the detection node (SD-n) 10 and the second conductivity type region (PD-n) 7 of the photodiode 3. A gate electrode 4 for forming a read transistor for reading is formed. Since the gate electrode 4 is arranged so as to extend between the detection node (SD-n) 10 and the second conductivity type region (PD-n) 7 constituting the photodiode 3, the detection node (SD-n)
A MOS transistor having a drain region 5 as a drain region 5 and a second conductivity type region (PD-n) 7 constituting a photodiode 3 as a source region is formed, and the second conductivity type region (PD -N) The signal charge 16 generated in 7 can be caused to flow to the SD-n 10 on the drain region 5 side by controlling the voltage of the gate electrode 4, and S
If, for example, the configuration is such that the gate electrode of the amplification MOS transistor is connected to Dn 10, the charge of the photodiode 3 can be given by controlling the gate electrode 4. Therefore, SD-n 10 has a meaning such as a detection node of the photodiode 3 with respect to the amplification MOS transistor. Therefore, the SD-n 10 forming the drain region 5 is referred to herein as a detection node. In the same sense, the gate electrode 4 is a transfer gate for a signal generated by the photodiode 3.
Is referred to as a transfer gate (TG) 4.

A channel stop region 11 for element isolation is formed on the semiconductor substrate 1 so as to surround the photodiode 3 and the readout transistor.
A surface shield region (PD-p +) 6 for protecting the surface is formed on the upper surface of the conductivity type region (PD-n) 7, and a detection node portion (below the transfer gate (TG) 4) and a read destination ( On the upper surface of the SD-n) 10, a channel implant (CH-) for setting threshold values of the detection node (SD-n) 10 and the transfer gate (TG) 4 is provided.
(I / I) 9 is formed.

The element isolation region 11 is a channel stop (high-concentration first conductivity type layer). This element isolation region is a thick oxide film LOCOS (Local Oxidation of S).
(ilicon) region or both. It is represented by a channel stop in the drawing.

The impurity concentration of the second conductivity type region (PD-n) 7 in the photodiode portion 3 is at an intermediate level between the impurity concentration of the well region 2 and the impurity concentration of the surface shield region (PD-p +) 6. is there. Also, since it is necessary to accumulate the electron charges generated corresponding to the amount of light received by the photodiode in the second conductivity type region (PD-n) 7 of the photodiode 3, it is necessary to set the potential to a positive potential.

However, in this case, the depletion layer always extends to the surface (upper surface) of the second conductivity type region (PD-n) 7. 7
When it reaches the surface (upper surface) of the second conductive type region (PD-n) 7, the leakage current increases, leading to an increase in unevenness in darkness. It is necessary to design the highest impurity concentration in the portion of (p +) 6.

In such a structure of the surface shield, the second conductivity type region (PD-n) of the photodiode 3
7 is completely depleted, so that the signal charge 16 generated by photoelectric conversion in the second conductivity type region (PD-n) 7 of the photodiode 3 corresponding to the amount of light received does not leak to the semiconductor. It is stored inside the substrate 1.

However, the high-concentration surface shield region (PD-p +) 6 always extends below the transfer gate (TG) 4 by heat treatment after ion implantation in the semiconductor manufacturing process. When the transfer gate (TG) 4 is turned on by the high-concentration p region, the potential under the transfer gate 4 cannot be set to a high voltage.

Therefore, the photodiode (PD-n)
7 cannot be read out. Further, when the channel length L of the transfer gate (TG) 4 is reduced by the low-concentration p-well region 2, the second conductivity type region (P) of the photodiode 3 corresponding to the source region is reduced.
Dn) 7 and a detection node portion S corresponding to a drain region.
A depletion layer extends from Dn 10, causing punch-through.

When punch-through occurs at the gate (TG) 4 of the transfer transistor, the potential of the drain region modulates the channel potential.
(Drain modulation effect) ", which causes problems such as deterioration of the linearity of the signal light amount-output charge characteristic.

Therefore, in the first embodiment, the first conductivity type well region 2 formed on the semiconductor substrate 1 and the first conductivity type well region and the first conductivity type well region 2 formed on the well region 2 are formed. One conductivity type surface shield area (PD-p +
6), and a first conductive type surface layer (surface shield region (PD-p +) 6) formed on the second conductive type region (PD-n) 7 of the photodiode 3. ) And the second in the photodiode 3
A conductivity type region (PD-n) 7 and a read gate (TG) 4 formed near the photodiode 3
And a unit cell section of a solid-state imaging device including a second conductive type drain region 5 (detection node section (SD-n) 10) formed near the other of the read gate (TG) 4 section, A first conductivity type barrier layer (BA-P) 8 having a higher concentration than the first conductivity type well region 2 is formed inside the semiconductor substrate 1 below the read gate (TG) 4, and further, the photodiode is formed. 3, the second conductivity type region 7;
The read gate (T) adjacent to the second conductivity type region 7
G) A structure having a second conductivity type through channel layer 9 formed under 4.

That is, in order to prevent problems such as channel length modulation effect (drain modulation effect) and punch-through from occurring, in the first embodiment, the transfer gate (T
G) A barrier layer (BA-P layer) 8 having the same type as the p-well layer 2 and a higher concentration (p-type and higher concentration) than the p-well layer 2 is provided under the barrier layer 4 and the barrier layer (BA-P layer) 8 is provided so as to be connected to both the second conductivity type region (PD-n) 7 of the photodiode 3 and the detection node (SD-n) 10.

Thus, a depletion layer extending from both the second conductivity type region (PD-n) 7 constituting the photodiode 3 and the detection node (SD-n) 10 on the drain side of the transistor can be suppressed.

Further, a high concentration barrier layer (BA-P layer)
8, there is a possibility that the signal charges of the second conductivity type region (PD-n) 7 in the photodiode 3 cannot be read, and as a countermeasure, the barrier layer (BA-P
A channel forming layer (TG-N) 15 is provided above the layer 8. The channel forming layer (TG-N) 15 is located above the barrier layer (BA-P layer) 8, and is transferred from the second conductivity type region (PD-n) 7 of the photodiode 3 to the transfer gate of the transistor. (TG) 4 is formed so as to partially protrude downward.

The formation range of the channel formation layer (TG-N) 15 is narrow, and the second conductivity type region (PD
-N) Transfer gate (TG) 4 of transistor in 7
It occupies the vicinity and a part of the area under the transfer gate 4.

With such a configuration, the channel forming layer (TG-N) 15 plays a part of the signal readout path 13, and the signal readout path can be secured.

(Second Embodiment) FIG. 2 shows a second embodiment as another example. FIG. 2 also has substantially the same structure as that of FIG. 1 except that the barrier region (BA-P) 8 is not connected to the second conductivity type region (PD-n) 7 of the photodiode 3. I have.

However, since the extension of the depletion layer from the detection node (SD-n) 10 forming the drain region 5 needs to be suppressed, the barrier region (BA-P) 8 is connected to the detection node (SD-n) forming the drain region 5. Section (SD-n) 10 is connected to the lower part.

Further, for the same reason as in the first embodiment, a channel forming layer (TG-P layer) is formed on the upper side of the barrier layer (BA-P layer) 8.
N) 15 is provided. This channel forming layer (TG-N) 1
5 is located above the barrier layer (BA-P layer) 8 except that the second conductive type region (PD-n) 7 of the photodiode 3 is similar to the first embodiment. The transistor is not formed so as to partially protrude below the transfer gate (TG) 4 of the transistor, but is kept in the second conductivity type region (PD-n) 7.

The formation range of the channel formation layer (TG-N) 15 is narrow, and the second conductivity type region (PD
-N) Transfer gate (TG) 4 of transistor in 7
It occupies a partial area in the vicinity.

With such a configuration, the channel forming layer (TG-N) 15 plays a part of the signal readout path 13, and the signal readout path can be secured.

Since the n-type ion implantation region (channel formation layer (TG-N) 15) for reading is formed by a self-alignment process after the formation of the transfer gate (TG) 4, the MOS transistor having this configuration is used. In the solid-state imaging device, it is possible to suppress variations in the manufacturing process.

(Third Embodiment) FIG. 3 shows a third embodiment. This example basically follows the structure of the first embodiment. However, the channel forming layer (TG-N) 15 is removed from the structure of the first embodiment, and the transfer gate (T
G) A channel forming layer (4) extending between the second conductivity type region (PD-n) 7 and the detection node unit (SD-n) 10 below the 4 and above the barrier layer (BA-P) 8. CH-A)
12 were provided.

That is, as shown in FIG. 3, in this example, a low-concentration well region (P-well region) 2 is formed on a semiconductor substrate 1. In this case, too, reading is very problematic, so that the second conductivity type region (PD-n) 7 of the photodiode 3 and the drain portion 5 of the transistor are formed below the reading gate (TG) 4 (SD-n). ) 10
To form a barrier layer (BA-P) 8;
The channel length modulation effect (drain modulation effect)
And the occurrence of punch-through, and by applying a low voltage, the second conductivity type region (PD-n) from the completely depleted second conductivity type region (PD-n) 7 of the photodiode 3 In order to be able to read out the signal charges 16 generated at 7 to the detection node unit (SD-n) 10, the barrier layer (BA-P) in the channel region
8 By ion-implanting into the upper region, the channel forming layer (CH-
A) Form 12.

The ion implantation is performed in the second conductivity type region (PD-
n) and a part of the detection node (SD-n) 10 so as to extend over the second conductivity type region (PD).
-N) 7 and a channel forming layer (CH-A) 12 can be formed in a region above the barrier layer (BA-P) 8 in the channel region so as to connect the detection node portion (SD-n) 10.

Such a channel forming layer (CH-A) 1
2, the signal charges 16 generated in the second conductivity type region (PD-n) 7 of the photodiode 3 are transferred along the channel forming layer (CH-A) 12 as a current path 13. The data is read to (SD-n) 10 in the drain region 5.

In the case of the third embodiment, the barrier layer (B
The (AP) 8 and the channel forming layer (CH-A) 12 can be formed using the same mask, and the process can be simplified. However, it is not always necessary to form the barrier layer (BA-P) 8 below the channel forming layer (CH-A) 12 in the invention disclosed herein. Has a characteristic.

(Fourth Embodiment) FIG. 4 shows a fourth embodiment. This example corresponds to a modification of the third embodiment shown in FIG. In the configuration of FIG. 4, a barrier well (BA-we) is used instead of the barrier layer (BA-P) 8 in FIG.
11) is formed.

This barrier well (BA-well) 14
Are formed over the region including the region under and around the transfer gate (TG) 4, the region (PD-n) 7 of the second conductivity type of the photodiode 3 and the region (SD-n) for the drain region 5 of the transistor. And 10). Then, in the barrier well (BA-well) 14 region, the channel ion implantation region (CH-A) is formed so as to extend between the second conductivity type region (PD-n) 7 and the detection node unit (SD-n) 10. 12 is formed.

According to this structure, the same effect as in the third embodiment can be expected. (Fifth Embodiment) FIG. 5 shows a fifth embodiment.

In this embodiment, as shown in FIG. 5, a low-concentration p-well (p-well) layer 2 is formed on a semiconductor substrate 1, and a second photodiode 3 is formed on the p-well layer 2. A detection node (SD-n) 10 for forming the conductivity type region (PD-n) 7 and the drain region 5 is formed.

On the p-well layer 2, a region between the formation region of the detection node portion (SD-n) 10 for forming the second conductivity type region (PD-n) 7 and the drain region 5 of the photodiode 3 is further formed. A transfer gate (TG) 4 is formed so as to cover the second conductive type region (PD-n) 7, and a detection node for forming the drain region 5 is formed. The part (SD-n) 10 is formed so as not to enter the area.

Then, a p-type surface shield portion (PD-p +) region 6 is formed above the second conductivity type region (PD-n) 7 of the photodiode 3, and this surface shield portion (PD-n) is formed. p +) region 6 is a transfer gate (T
G) 4 to be formed in a self-aligned manner, while the second conductivity type region (P
Dn) 7 is prevented from being formed in a self-aligned manner by the transfer gate (TG) 4. Therefore, the second conductivity type region (PD-n) 7 of the photodiode 3 has a configuration extending to below the transfer gate (TG) 4.

As described above, by adopting a structure in which the portion of the second conductivity type region (PD-n) 7 of the photodiode 3 extends below the transfer gate (TG) 4, the second conductivity type region of the photodiode 3 is The signal charges 16 generated in the region (PD-n) 7 can be read out to the (SD-n) 10 in the drain region 5.

That is, in the configuration of the fifth embodiment, the second conductivity type region (PD-
Since n) 7 enters under the transfer gate (TG) 4 of the transistor, the potential of the read channel can be modulated by the transfer gate (TG) 4.

In this case, the barrier layer (BA-P) 8
It is not a mandatory configuration requirement. Therefore, the configuration shown in FIG. 6 may be used. FIG. 6 shows an LD of a MOS transistor.
The structure adopts the D structure. Reference numeral 17 denotes a sidewall spacer having an LDD structure. This sidewall spacer 1
7, the second conductivity type region (PD-n) 7 is offset, and the second conductivity type region (P
Dn) 7 to the signal charge 16 in the drain region 5 (SD
-N) read out to 10;

(Sixth Embodiment) FIG. 7 shows a sixth embodiment. As shown in FIG. 7, in this example, on a semiconductor substrate 1,
A low concentration well layer 2 is formed. Then, a second conductivity type region (PD-n) 7 constituting the photodiode 3 and a drain region 5 of the transistor are formed above the low concentration well layer 2.
Is formed as the detection node unit (SD-n) 10.

A transfer gate (TG) 4 is formed in the low-concentration well layer 2 in a region between the second conductivity type region (PD-n) 7 and the detection node (SD-n) 10 via an insulating layer. You.

Under the transfer gate (TG) 4, a channel forming layer (TG-N) of the same impurity type as the second conductivity type region (PD-n) 7 of the photodiode 3 is provided to improve reading. 15 is the second conductivity type region (PD-n)
7 to a part of the region below the transfer gate (TG).

In this embodiment, the channel formation layer (TG-N) 15 is not formed in a self-aligned manner with respect to the transfer gate (TG) 4. Then, the channel forming layer (TG-N) 15 is a transfer gate (TG) 4
Lower part area and surface shield layer (PD-P +) 6
It is characterized in that it is formed so as to be connected to a part of.

Although various embodiments have been described above, the present invention is, in short, a unit cell comprising a photodiode for photoelectric conversion and an MO for reading signal charges from the photodiode.
In a MOS-type solid-state imaging device designed to take out via an S-transistor, the driving voltage can be 3.3 [V] or 5.0 [V] even in the surface shield structure by devising the structure of the gate of the reading MOS transistor. ], Which provides a structure of a read transistor capable of performing a complete transfer even at a low voltage of a first conductivity type formed on a semiconductor substrate and a well region formed on the well region. A second conductivity type photodiode portion,
A first conductivity type surface layer formed above the second conductivity type photodiode portion; a readout gate portion formed adjacent to the second conductivity type photodiode portion; Forming a conductive type barrier layer, further forming the second conductive type photodiode portion, and a second conductive type through channel layer formed adjacent to the second conductive type photodiode layer and below the readout gate portion; It is a structure provided with.

By adopting such a structure, even if the photodiode portion has a surface shield structure, the signal of the photodiode can be completely read out. 3.
Even with a low power supply voltage of 3 [V], it is possible to provide a read transistor structure capable of reading signal charges of a surface-shielded photodiode.

Although the power supply voltage of the MOS type solid-state imaging device of the present invention is small with one power supply, the readout gate (TG)
The voltage applied to 4 may be increased by a circuit technique such as a booster circuit.

The present invention relates to a MOS-type solid-state imaging device, and more particularly to an improvement in the structure of a read transistor portion in a unit cell portion. However, the present invention relates to a readout device capable of reading out a signal of a fully depleted photodiode portion. 2. Even with a surface shield structure having a transistor structure, by devising the structure of the read gate,
With a low power supply voltage of 3 [V] or 5.0 [V], a read transistor capable of performing complete transfer can be realized.

[0081]

As described above in detail, according to the present invention, even if the photodiode has a surface shield structure and the photodiode is completely depleted, the structure of the read gate can be improved. It is possible to provide a MOS solid-state imaging device having a read transistor structure capable of completely transferring signal charges of a photodiode with a low power supply voltage of 0.3 [V] or 5.0 [V].

[Brief description of the drawings]

FIG. 1 is a view for explaining the present invention, and is a sectional view of an element showing a first embodiment of the present invention.

FIG. 2 is a view for explaining the present invention, and is a sectional view of an element showing a second embodiment of the present invention.

FIG. 3 is a view for explaining the present invention and is a sectional view of an element showing a third embodiment of the present invention.

FIG. 4 is a view for explaining the present invention, and is a sectional view of an element showing a fourth embodiment of the present invention.

FIG. 5 is a view for explaining the present invention, and is a sectional view of an element showing a fifth embodiment of the present invention.

FIG. 6 is a view for explaining the present invention, and is a sectional view of an element showing a sixth embodiment of the present invention.

FIG. 7 is a view for explaining the present invention, and is a sectional view of an element showing a seventh embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 low-concentration well layer 3 photodiode 5 transistor drain region 4 transfer gate (TG) 6 surface shield layer (PD-P +) 7 second conductive element forming photodiode 3 Mold area (P
Dn) 8 ... Barrier layer (BA-P) 9 ... Second conductivity type through channel layer 10 ... Construct drain region 5 of transistor (SD
-N) 11: channel stop region for element isolation 12: channel forming layer (CH-A) 13: current path 14: barrier well (BA-well) 15: channel forming layer (channel implant layer (PD)
-N)) 16 ... signal charge

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hidetoshi Nozaki 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Inside the Toshiba R & D Center Co., Ltd. (72) Inventor Hiroshi Yamashita Toshiba Komukai, Saiwai-ku, Kawasaki City, Kanagawa Prefecture No. 1 Town, Toshiba R & D Center (72) Inventor Ikuko Inoue No. 1, Komukai Toshiba Town, Kawasaki City, Kanagawa Prefecture, Japan Toshiba R & D Center

Claims (5)

[Claims] A photodiode portion including a first conductivity type well region formed on a semiconductor substrate, a second conductivity type region formed on the well region, and a second conductivity type of the photodiode portion. A first conductivity type surface layer formed above the region, and a second conductivity type surface region formed in the first conductivity type well region near the second conductivity type region of the photodiode portion.
A solid-state imaging device comprising: a drain region of a conductivity type; and a gate portion of a read transistor provided above the well region between the drain region and a second conductivity type region of the photodiode portion. Forming a first-conductivity-type barrier layer that connects the second-conductivity-type region and the second-conductivity-type drain region in a deep portion, and between the first-conductivity-type barrier layer and the lower part of the gate portion. A solid-state imaging device comprising: a high-concentration second-conductivity-type channel configuration layer protruding from a second-conductivity-type region of the photodiode unit. 2. A photodiode portion comprising a first conductivity type well region formed on a semiconductor substrate, a second conductivity type region formed on the first conductivity type well region, and a second conductivity type of the photodiode portion. A first conductivity type surface layer formed above the region, and a second conductivity type surface region formed in the first conductivity type well region near the second conductivity type region of the photodiode portion.
A solid-state imaging device, comprising: a drain region of a conductivity type; and a gate portion of a read transistor provided above the well region between the drain region and the second conductivity type region of the photodiode portion. A first conductivity type barrier layer formed with an offset approaching the second conductivity type region side of the photodiode portion from a deep portion in the drain region, and a second conductivity type region of the photodiode portion A solid-state imaging device, wherein a channel-constituting layer of a high-concentration second conductivity type is provided on the surface layer side of the barrier layer position and toward the end of the gate portion. A first conductivity type well region formed on the semiconductor substrate, a second conductivity type photodiode portion formed on the well region, and an upper portion of the second conductivity type photodiode portion. A surface layer of the first conductivity type formed, a read gate portion formed adjacent to the photodiode portion of the second conductivity type, and a drain of the second conductivity type formed adjacent to the other of the read gate portion A unit cell portion of the solid-state imaging device having a region, a first portion formed below the gate portion of the readout transistor and adjacent to both the second conductivity type photodiode portion and the second conductivity type drain region. A second conductive type through-hole formed adjacent to both the second conductive type photodiode section and the second conductive type drain region, above the first conductive type barrier layer; A solid-state imaging apparatus characterized by having Le layer. 4. The solid-state imaging device according to claim 3, wherein a second conductive type barrier well having a higher concentration than the first conductive type well layer is provided instead of the first conductive type barrier layer. A solid-state imaging device characterized by the above-mentioned. 5. A photodiode portion comprising a first conductivity type well region formed on a semiconductor substrate, a second conductivity type region formed on the well region, and a second conductivity type of the photodiode portion. A first conductivity type surface layer formed above the region, and a second conductivity type surface region formed in the first conductivity type well region near the second conductivity type region of the photodiode portion.
A solid-state imaging device comprising: a drain region of a conductivity type; and a gate portion of a read transistor provided above the well region between the drain region and a second conductivity type region of the photodiode portion. A solid-state imaging device having a structure in which a part of the second conductivity type region reaches an interface with an oxide film below a gate portion of the read transistor.