JP6897740B2 - Pixel unit and image sensor - Google Patents

Description

The present invention relates to a pixel unit and an image sensor.

Solid-state image sensors such as CMOS (Complementary Metal Oxide Semiconductor) image sensors can be manufactured using a general semiconductor manufacturing process, and analog and digital circuits can be mixed in the same chip. Therefore, it has a great advantage that the number of peripheral ICs can be reduced.

The solid-state image sensor is composed of a pixel portion in which a plurality of pixels are arranged and a peripheral circuit arranged around the pixel portion. Each pixel comprises a photoelectric conversion element (PD) such as a photodiode, a pixel transistor including various transistors, and a floating diffusion (FD) region for voltage-converting the photoelectrically converted charge.

In the solid-state image sensor, the gate size of the pixel transistor is also reduced as the size of each pixel in the pixel portion is reduced due to miniaturization, so that the characteristics of the pixel transistor may not be maintained. For example, the transfer transistor (TX) included in the pixel transistor has a transfer gate (TG) for transferring and reading charges from the PD region to the FD region. It is becoming difficult to achieve both.

In particular, as the gate size of the transfer transistor becomes smaller, the voltage modulation in the channel of the transfer gate becomes smaller during charge transfer. As a result, the potential potential of the transfer gate does not rise (the potential barrier does not fall), which affects transfer characteristics such as afterimage, photoresponsiveness, and black spot defects. On the other hand, increasing the gate size of the transfer transistor narrows the area of the PD region, and the light incident on the PD region becomes insufficient due to the presence of the transfer gate of the transfer transistor.

Therefore, in the conventional solid-state image sensor, a part of the gate of the transfer transistor is projected from the main body of the gate to the PD region side for the purpose of controlling the potential potential of the gate of the transfer transistor to reduce the transfer residue. A structure including an extension portion is known (for example, Patent Document 1).

However, in the conventional image sensor, since the area of the PD region is reduced due to the presence of the extension portion with respect to the main body portion of the transfer gate, the number of saturated electrons is reduced in the PD region, and light incident is not sufficiently secured. Further, since there are parts having different gate sizes (particularly gate lengths) in the transfer gate and the distance from the PD area to the FD area (TX gate length) is not uniform, the FD area adjacent to the TX (particularly, the gate length) is not uniform. The potential in the neighboring region) varies.

Due to such a variation in potential, it takes time to move the charge from the region distant from the TX in the PD region to the region adjacent to the TX, so that the transfer characteristic may be deteriorated. As described above, the structure of the conventional solid-state image sensor has a structure that adversely affects the transfer characteristics. Therefore, there is a demand for an image sensor with improved transfer characteristics while sufficiently ensuring light incident.

The imaging element according to one aspect of the present invention is a pixel unit including a photoelectric conversion element, a transfer transistor including a transfer gate connected to the photoelectric conversion element, and a floating diffusion region connected to the transfer gate. The transfer gate has a first gate width in the gate width direction, a first gate region connected to the floating diffusion region and extending in the gate length direction away from the floating diffusion region, and the first gate region in the gate width direction. The second gate region has a second gate width smaller than the gate width of 1, includes a second gate region continuously extending from the first gate region in the gate length direction, and the second gate region is the second gate region. wherein in a direction away from the first gate region first Ri from the gate width of such gradually becomes smaller in the second gate width, the planar shape of the transfer gate, the side away from the floating diffusion region of the square wherein the shape der Rukoto obtained by cutting two corners.

According to the present invention, it is possible to improve the transfer characteristics of the image pickup device while sufficiently ensuring the light incident.

It is a figure which shows an example (1st Example) of the pixel unit which concerns on this invention. It is a figure which shows the electric field state of an example of the pixel unit which concerns on this invention. It is a figure which shows an example (2nd Example) of the pixel unit which concerns on this invention. It is a figure which shows an example (third embodiment) of the pixel unit which concerns on this invention. It is a figure which shows an example (4th Example) of the pixel unit which concerns on this invention. It is a figure which shows an example (fifth embodiment) of the pixel unit which concerns on this invention. It is a figure which shows an example (sixth Example) of the pixel unit which concerns on this invention. It is a figure which omits a part of an example of the image pickup element (pixel part) using the pixel unit (fifth embodiment) of FIG. It is a schematic block diagram which shows an example of the image pickup device which concerns on this invention. It is a figure which shows the circuit structure of the pixel which constitutes the pixel part of the image pickup device of FIG. It is a figure explaining the operation timing of the pixel unit constituting the image pickup device of FIG. It is a figure which shows an example of the camera system which used the image sensor provided with the pixel unit which concerns on this invention.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In each drawing, the same or corresponding configurations are designated by the same reference numerals and the description thereof will be omitted. FIG. 1 shows a pixel structure which is an example (first embodiment) of a pixel unit according to the present invention. The pixel 1 includes a photodiode 3, a transistor 5, and a diffusion region 7.

The photodiode 3 has a function of being electrically connected to the transistor 5 and converting the incident light into an electric charge. Although not shown, in the photodiode 3, an n-type semiconductor region (n +) serving as a charge storage region is formed in the p-type semiconductor well region, and a p-type semiconductor region (p +) is formed on the surface side of the n-type semiconductor region. It is configured as an embedded type photoelectric conversion element.

The photodiode 3 is an example of a photoelectric conversion element constituting the pixel unit of the present invention.

The transistor 5 is provided adjacent to the photodiode 3 with a gate 51 that is electrically connected to the photodiode 3. That is, the transistor 5 is connected to the photodiode 3 via the gate 51. The transistor 5 has a function of transferring the electric charge converted by the photodiode 3 to the diffusion region 7.

The transistor 5 is an example of a transfer transistor constituting the pixel unit of the present invention. Further, the gate 51 of the transistor 5 is an example of a transfer gate constituting the transfer transistor in the present invention.

The diffusion region 7 is adjacent to the transistor 5 so as to sandwich the transistor 5 with the photodiode 3, and is electrically connected to the gate 51 of the transistor 5. The planar shape of the diffusion region 7 is a quadrangle such as a rectangle or a square. The diffusion region 7 contains diffused impurities and is formed in the n-type semiconductor region (n +). The diffusion region 7 corresponds to the drain of the transistor 5, and the electric charge transferred from the transistor 5 is accumulated.

The diffusion region 7 is an example of a floating diffusion region constituting the pixel unit of the present invention.

In the pixel unit of FIG. 1, an element separation region 9 is further formed so as to surround the photodiode 3, the transistor 5, and the diffusion region 7. The element separation region 9 constitutes a p-type semiconductor region (p + region), and a part of the element separation region 9 is formed by entering the channel portion of the gate 51 of the transistor 5 (below the gate 51 of the transistor 5). May be good.

Due to the existence of such an element separation region 9, the photodiode 3, the transistor 5, and the diffusion region 7 provided in the pixel 1 are electrically separated from the other pixels 1.

Further, the gate 51 of the transistor 5 is configured to include a first gate region 52 and a second gate region 53 having different gate widths. The first gate region 52 has a first gate width GW1 in the gate width direction WD, and extends toward the gate length direction LD connected to the diffusion region 7 and away from the diffusion region 7.

Here, the gate length direction LD means a direction in which the carrier moves in the channel during the operation of the transistor 5, and corresponds to the vertical direction in FIG. Further, the gate width direction WD means a direction orthogonal to the gate length direction LD, and corresponds to the left-right direction in FIG. Therefore, the direction in which the first gate region 52 extends (gate length direction LD away from the diffusion region 7) indicates a direction from top to bottom in FIG.

Further, the second gate area 53 has a second gate width GW2 smaller than the first gate width GW1 in the gate width direction WD, and continuously extends from the first gate area 52 in the gate length direction LD. There is. The second gate region 53 continuous from the first gate region 52 may be formed integrally with the first gate region 52, or may be formed as a separate member from the first gate region 52. May be good.

The second gate region 53 is formed so as to gradually decrease from the first gate width GW1 to the second gate width GW2 in the direction away from the first gate region 52. The direction away from the first gate region 52 indicates a direction from top to bottom on the paper of FIG. 1 in the same direction as the direction in which the first gate region 52 extends (gate length direction LD away from the diffusion region 7).

That is, the gate width of the gate 51 is constant in the first gate area 52 (first gate width GW1), and in the second gate area 53, the neighborhood 53a to the second gate area of the first gate area 52 It becomes smaller toward the tip of 53 (side 51f described later).

In other words, in the second gate region 53, the first gate width GW1 to the second gate are directed from the vicinity 53a of the first gate region 52 toward the tip of the second gate region 53 (side 51f described later). The width changes to GW2 so that the gate width becomes smaller.

In FIG. 1, the gate 51 is arranged between the photodiode 3 and the diffusion region 7. The diffusion region 7 is connected to the end portion 51a of the gate 51 (first gate region 52) on the diffusion region 7 side with a width dimension shorter than that of the first gate width GW1.

In FIG. 1, the gate 51 is arranged between the photodiode 3 and the diffusion region 7. The diffusion region 7 is connected to the end portion 51a of the gate 51 (first gate region 52) on the diffusion region 7 side with a width dimension shorter than that of the first gate width GW1.

When the gate 51 of the transistor 5 having such a shape is arranged so as to be surrounded by the photodiode 3 except for the end portion 51a connected to the diffusion region 7, the area of the photodiode 3 is maintained while maintaining the area of the entire pixel 1. Can be widened. As a result, even if the gate 51 of the transistor 5 is arranged, the light incident can be sufficiently secured in the photodiode 3 and the number of saturated electrons can be sufficiently secured.

Further, by the gate 51 of the transistor 5 in this shape, it can be made substantially uniform length from the photodiode 3 to the diffusion region 7. Therefore, in the region where the photodiode 3 is provided, the potential can be increased from the remote region 3a away from the transistor 5 toward the near region 3b adjacent to the transfer transistor.

As a result, the transfer electric field is improved (no reverse electric field is generated) between the remote region 3a away from the transistor 5 in the region of the photodiode 3 and the neighboring region 3b adjacent to the transfer transistor, so that the transfer characteristics of the image sensor Can be improved.

As shown in FIG. 1, the gate 51 of the transistor 5 is preferably formed so that the second gate region 53 has a tapered shape. By arranging such a tapered gate 51 between the photodiode 3 and the diffusion region 7, the length from the photodiode 3 to the diffusion region 7 can be made substantially uniform.

Therefore, by arranging such a tapered gate 51, the potential is made positive from the photodiode 3 toward the gate 51 of the transistor 5 (from the remote region 3a of the photodiode 3 toward the nearby region 3b). Can be done. That is, since the transfer electric field can be improved in the region of the photodiode 3, the transfer characteristics of the image sensor can be improved by arranging such a tapered gate 51.

Further, as shown in FIG. 1, the planar shape of the gate 51 is preferably a shape in which two corners of the four corners of the quadrangle on the side away from the diffusion region 7 are cut out. Specifically, the planar shape of the gate 51 is composed of the six sides and the six corners shown in FIG. Of the six sides, the side located on the diffusion region 7 side corresponds to the end portion 51a connected to the diffusion region 7 of the gate 51 (first gate region 52).

Of the remaining five sides, two sides constitute the two sides 51b and the side 51c included in the first gate area 52. The side 51b and the side 51c are continuous with the side (end) 51a and face the WD in the width direction. The remaining three sides constitute the three sides 51d, 51e, and 51f included in the second gate area 53. Of the three sides, the side 51d and the side 51e face the gate width direction WD while being continuously inclined toward the gate length direction LD on the side 51b and the side 51c, respectively.

Further, the side 51f is continuous with the sides 51d and 51e and faces the side 51a in the gate length direction LD. These three sides (side 51d, side 51e, and side 51f) have a shape of the second gate region 53 (a shape that gradually decreases from the first gate width GW1 to the second gate width GW2). Configure. In other words, these three sides (side 51d, side 51e, and side 51f) form a tapered second gate region 53.

In FIG. 1, the gate 51 is arranged between the photodiode 3 and the diffusion region 7 so that five sides (sides 51b to 51f) excluding the side 51a are adjacent to the photodiode 3. That is, the gate 51 is arranged so that the photodiode 3 surrounds five sides (sides 51b to 51f) excluding the side 51a.

By arranging the gate 51 having such a shape between the photodiode 3 and the diffusion region 7, the length from the photodiode 3 to the diffusion region 7 can be made substantially uniform with high accuracy.

Therefore, the potential can always be positive from the photodiode 3 toward the gate 51 of the transistor 5 (from the remote region 3a of the photodiode 3 toward the near region 3b). That is, since the transfer electric field can be reliably improved within the region of the photodiode 3, the transfer characteristics of the image pickup device can be reliably improved by arranging such a gate 51.

In the example shown in FIG. 1, the planar shape of the gate 51 is a hexagon in which all six sides are straight lines. However, the six sides constituting the gate 51 are not limited to straight lines. For example, of the six sides, at least one of the two sides (sides 51d and 51e) constituting the tapered second gate region 53 may be curved.

Further, the photodiode 3, the gate 51 of the transistor 5, and the diffusion region 7 are preferably arranged on a straight line. With such an arrangement, the length from the photodiode 3 to the diffusion region 7 can be made substantially uniform with higher accuracy via the gate 51 of the transistor 5.

FIG. 2 shows the electric field state of the photoelectric conversion element in an example of the pixel unit constituting the image pickup element of the present invention. FIG. 2 shows the potential potential at the time of charge transfer in the photoelectric conversion element provided in the pixel unit.

From this figure, the potential potential extends from the vicinity region 3b of the region of the photodiode 3 adjacent to the transistor 5 toward the remote region 3a of the region of the photodiode 3 away from the transistor 5 so that the maximum potential potential expands. You can see that.

From a different point of view, in the region of the photodiode 3, the electric field is always positive from the remote region 3a to the near region 3b. That is, it can be seen that in the region of the photodiode 3, there is no reverse electric field from the remote region 3a to the near region 3b. As described above, FIG. 2 shows that by arranging the gate 51, so-called transfer residue in which electric charges remain in the region of the photodiode 3 is less likely to occur, and the transfer characteristics are improved.

FIG. 3 shows an example (second embodiment) of a pixel unit constituting the image pickup device of the present invention. In pixel 1 of FIG. 3, the diffusion region 7 is composed of two regions having different concentrations of diffused impurities. Of these, the region having a high impurity concentration constitutes a high concentration region 7a, and the region having a low impurity concentration constitutes a low concentration region 7b.

The impurity concentration in this high concentration region 7a ^{can be 1 × 1019 cm -3} or more. Further, the impurity concentration in the low concentration region 7b can be less than ^{1 × 1019 cm -3.}

The high concentration region 7a is composed of a region (N +) having a high impurity concentration and is connected to the bottom of the gate 51 of the transistor 5. Further, the low concentration region 7b is adjacent to the high concentration region (N +) and is connected to the gate 51 of the transistor 5. The low concentration region 7b constitutes a region (N−) having a lower impurity concentration than the high concentration region (N +).

The high density region 7a is an example of the first diffusion region of the diffusion region of the pixel unit constituting the image pickup device of the present invention, and the low density region 7b is the second diffusion region of the diffusion region. It is an example of the area.

By providing such a high-concentration region and a low-concentration region, the electric charge transferred by the transistor 5 can easily move to the low-concentration region where the potential is shallow. Then, the charges collected in the low concentration region where the potential is shallow are collected in the high concentration region where the potential is deep, so that the decrease in transfer efficiency can be suppressed. Therefore, the junction capacitance (diffusion capacitance) of the diffusion region 7 can be reduced, and the conversion efficiency of the image sensor can be improved.

Further, in the element separation region 9, crystal defects (or lattice defects) are likely to occur inside in the manufacturing of CMOS. Therefore, if the element separation region 9 is adjacent to the high concentration region 7a of the diffusion region, a dark current is likely to be generated, which may reduce the conversion efficiency.

Therefore, as shown in FIG. 3, the low-concentration region 7b is preferably provided at a position separating the high-concentration region 7a and the element separation region 9, that is, between the high-concentration region 7a and the element separation region 9. When the low concentration region 7b is provided at such a position, it is possible to suppress the generation of dark current and reduce the decrease in conversion efficiency.

Further, in the plan view of FIG. 3, the low-concentration region 7b is adjacent to the high-concentration region 7a so as to sandwich the high-concentration region 7a. When the low-concentration region 7b is arranged in this way with respect to the high-concentration region 7a, the low-concentration region 7b can be arranged in the vicinity of the portion where the diffusion region 7 is connected to the transfer transistor (the portion where a dark current is likely to occur). Therefore, it is possible to suppress the generation of dark current while reducing the diffusion capacity of the diffusion region 7, so that the conversion efficiency can be reliably improved.

Further, since the portion of the diffusion region 7 connected to the transistor 5 is composed of the high concentration region 7a and the low concentration region 7b, the source of the diffusion region 7 can be increased. As a result, the charge transfer characteristics can also be improved.

The impurity concentration of the low concentration region 7b in the diffusion region 7 is lower than that of the low concentration region of a normal LDD (lightly doped drain) structure. Further, the low concentration region 7b has an area wider than the region where the impurity concentration naturally formed in the vicinity of the junction is wider than the region where the impurity concentration is naturally formed in the formation of a normal PN junction.

On the other hand, a part of the high concentration region 7a in the diffusion region 7 constitutes a contact region that becomes a part of the transistor 5 in a state of being connected to the transistor 5. In other words, a part of the transistor 5 also serves as a part of the high concentration region 7a in the diffusion region 7.

The high concentration region 7a is not necessary except for the position where the contact region is substantially placed. In the case of manufacturing by a general CMOS process, the high concentration region 7a is formed by impurity injection using a resist mask, so that it is sufficiently larger than the contact area of the contact region. On the other hand, an increase in the area of the diffusion region 7 increases the diffusion capacitance (so-called junction capacitance) in the floating diffusion, which may lead to a decrease in conversion efficiency.

Therefore, in this example, as shown in FIG. 3, of the diffusion region 7, the contact region (region in which electric charge is substantially easily accumulated) connected to the gate 51 of the transistor 5 is shared with the transistor 5. It forms a high concentration region 7a of the mold. The concentration distribution of impurities is set so that the other regions are n-type low concentration regions 7b.

The bonding capacitance in the low concentration region 7b is much smaller than that in the high concentration region 7a. Therefore, the total bonding capacitance in the diffusion region 7 is reduced, and the conversion efficiency is improved. Further, since the electric charge transferred from the photodiode 3 to the low concentration region 7b having a shallow potential in the diffusion region 7 is collected in the high concentration region 7a having a deep potential, the transfer efficiency can be maintained.

FIG. 4 shows the configuration of another example (third embodiment) of the pixel unit constituting the image pickup device of the present invention. In the pixel 1 shown in FIG. 2, the low density region 7b is composed of a part of the semiconductor substrate (Sub). That is, the area of a part of the semiconductor substrate (Sub) is substantially the same as the area of the low concentration region (N−) shown in FIG.

The semiconductor substrate (Sub) has a sufficiently lower impurity concentration than the high concentration region. Therefore, by forming the low concentration region 7b of the diffusion region 7 with a part of the semiconductor substrate Sub, the diffusion capacitance component of the diffusion region 7 can be reduced. Therefore, the total bonding capacitance in the diffusion region 7 is reduced, and the conversion efficiency is improved.

Further, by forming the low concentration region 7b with a part of such a semiconductor substrate (Sub), it is not necessary to use another member for forming the low concentration region of the floating diffusion. That is, since the low concentration region can be provided by using a conventional CMOS manufacturing process (etching or the like), the manufacturing cost can be suppressed.

FIG. 5 describes the configuration of still another example (fourth embodiment) of the pixel unit constituting the image pickup device of the present invention. Pixel 1 in FIG. 5 is further provided with a transistor 11. The transistor 11 is electrically connected to the diffusion region 7. The transistor 11 has a function of resetting (voltage conversion) the potential of the electric charge accumulated in the diffusion region 7 to the reset potential.

The transistor 11 includes a reset gate 11a forming a contact portion connected to the diffusion region 7, and the reset gate 11a is arranged so as to sandwich the diffusion region 7 with the gate 51 of the transistor 5. The transistor 11 is an example of a reset transistor in the present invention.

By providing such a transistor 11, the diffusion region 7 functions as a source of the transistor 11. On the other hand, since the diffusion region 7 also functions as the drain of the transistor 5, the source of the transistor 11 and the drain of the transistor 5 can be shared via the FD region. Therefore, the diffusion capacity component of the diffusion region 7 can be reduced. As a result, the total bonding capacitance in the diffusion region 7 is reduced, and the conversion efficiency is improved.

FIG. 6 shows the configuration of another example (fifth embodiment) of the pixel unit constituting the image pickup device of the present invention. The pixel 1 shown in FIG. 6 is further provided with a transistor 13.

The transistor 13 is connected to the diffusion region 7 and amplifies the signal voltage converted in the diffusion region 7. The transistor 13 is an example of an amplification transistor in the present invention.

The transistor 13 is composed of an amplification gate 13a and a drain / source diffusion region 13b. Of these, the amplification gate 13a is the gate capacitance of the capacitance of the diffusion region 7. Of the diffusion region 7, the high concentration region 7a is connected to the amplification gate 13a via the metal wiring 15.

By providing such a transistor 13, the transfer characteristics of the pixels can be further improved, and the capacitance of the diffusion region can be suppressed, so that the conversion efficiency can be improved. Further, since the presence of such a transistor 13 can output the amplified electric signal to the outside, it becomes easy to assemble an image sensor in combination with other pixels.

FIG. 7 shows the configuration of another example (sixth embodiment) of the pixel unit constituting the image pickup device of the present invention. In the pixel 1 of FIG. 7, an extension portion 54 in which a part of the transistor 5 extends toward the diffusion region 7 is provided with respect to FIG. As shown in FIG. 7, the extension portion 54 is formed so that the end portion of the transistor 5 on the diffusion region 7 side protrudes toward the diffusion region 7 side and overlaps a part of the diffusion region 7. With such an extension portion 54, the diffusion region 7 can be narrowed.

That is, the extension portion 54 constitutes a region (contact region) in which a part of the diffusion region 7 is connected to the transistor 5, and a part of the transistor 5 becomes a part of the diffusion region 7, so that the area of the diffusion region 7 is increased. It can be made smaller.

FIG. 8 shows an example of a pixel portion in which the pixels of the fifth embodiment shown in FIG. 6 are arranged. In the pixel portion 14 of FIG. 8, among the plurality of pixels 1, some of the plurality of pixels (pixels 1a and 1b) are arranged in a row in the vertical direction (vertical direction) in a plan view. Consists of. Further, the pixel groups 17 are arranged side by side in a plurality of rows in the horizontal direction (horizontal direction) in the plan view of FIG.

Both the pixels 1a and 1b constituting the pixel group 17 are connected to one vertical signal line 19 to one pixel group 17 via the metal wiring 21. The vertical signal line 19 has a function of transmitting an electric signal output from each pixel 1 to a read-out signal processing unit (read-out signal processing unit 27 of FIG. 9 to be described later).

The pixel group 17 is an example of a pixel unit sequence in the present invention. The vertical direction is an example of the first direction of the present invention, and the horizontal direction is an example of a second direction orthogonal to the first direction. Further, the vertical signal line 19 is an example of a signal line in the present invention.

The arrangement direction of the pixels constituting the pixel group 17 and the arrangement direction of the pixel group 17 are not limited, but as in this example, the pixel group 17 in which the pixels 1 are arranged vertically is further arranged in the horizontal direction. If they are arranged side by side, a plurality of pixels can be arranged in the pixel unit 14 at a high density. Moreover, the length of each vertical signal line can be shortened. As a result, it is possible to provide a high-resolution solid-state image sensor in which the transfer characteristics are improved and the light incident and saturation are sufficiently ensured.

Further, although not particularly shown, in the pixel unit 14, each pixel constituting the pixel group 17 may be connected to one vertical signal line for one pixel. For example, using two pixels and two vertical signal lines constituting the pixel group 17, one pixel is connected to one vertical signal line via a metal wiring, and the other pixel is connected to another vertical signal line via another metal wiring. Connect to the other vertical signal line.

By connecting such a pixel and a vertical signal line, the signal of the pixel can be read out at the same time. Therefore, the image sensor can be operated at high speed, and the transfer characteristics can be further improved.

Here, an example of the operation of the image pickup device (solid-state image pickup device) of the present invention will be described. FIG. 9 shows a schematic configuration of an example of the image pickup device (solid-state image pickup device) of the present invention. The main part of the solid-state image sensor 23 of this example is composed of a control circuit unit 25, a pixel unit 14, and a readout signal processing unit 27.

The control circuit unit 25 is connected to the pixel unit 14 and transmits a drive signal for driving the pixel unit 14 to the pixel unit 14.

The pixel unit 14 is configured by arranging a plurality of pixels 1 showing an example of a pixel unit constituting the image pickup device of the present invention. The pixel unit 14 is further connected to the read signal processing unit 27 via a vertical signal line 19 to which each pixel 1 is connected. The pixel unit 14 is driven by a drive signal from the control circuit unit 25, whereby the output signal output from each pixel 1 is read out and transmitted to the signal processing unit 27.

The read signal processing unit 27 includes a read circuit 29 that reads the output signal of the pixel 1 and a data transfer unit 31 that outputs the output signal read by the read circuit to the outside as signal data.

As the read circuit 29, an analog amplifier can be used when the output signal is read as an analog signal, and an AD conversion circuit can be used when the output signal is read as a digital signal. In this example, as the read circuit 29, an AD conversion circuit is provided as shown in FIG.

When the signal processed by the read signal processing unit 27 is an analog signal, the data transfer unit 31 can use an output amplifier for analog output. Further, in the case of a digital signal digitized by an AD conversion circuit or the like, a differential amplifier circuit for digital data or the like can be used. In this example, a differential amplifier circuit is provided as the data transfer unit 31.

FIG. 10 shows the circuit configuration of the pixel 1 constituting the pixel portion 14 of the image pickup device of FIG. A photodiode PD, a transfer transistor TX, a reset transistor RT, an amplification transistor SF, and a floating diffusion FD are arranged on the pixel 1.

Further, the power supply VDD, the control line (transfer control line) LTX of the transfer transistor TX, the control line (reset control line) LRT of the reset transistor RT, and the power supply control line L VDDRT of the reset transistor RT are arranged on the pixel 1. ..

The transfer transistor TX is connected between the photodiode PD and the floating diffusion FD as an output node. When a drive signal is given from the control circuit unit 25 to the transfer control line LTX, the transfer transistor TX transfers the electric charge (or electron) photoelectrically converted by the photodiode PD to the floating diffusion FD.

The reset transistor RT is connected between the reset power control line L VDDRT and the floating diffusion FD. In this reset transistor RT, a reset drive signal is given from the control circuit unit 25 to the gate of the reset transistor RT through the reset control line LRT. As a result, the potential of the floating diffusion FD is reset by the potential of the reset power supply L VDDRT.

The floating diffusion FD is connected to the gate of the amplification transistor SF in a state of being connected between the transfer transistor TX and the reset transistor RT.

The amplification transistor SF is connected to the vertical signal line 19 and constitutes a constant current source and a source follower outside the pixel unit 14. The amplification transistor SF amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the vertical signal line 19. The voltage output from each pixel 1 through the vertical signal line 19 is output to the read signal processing unit 27.

As shown in FIG. 9, the reset control line LRT, the transfer control line LTX, and the reset power supply control line L VDDRT, which are wired to the pixel unit 14, are wired in units of rows in which a plurality of pixels are arranged as a set. To. The reset control line LRT, the transfer control line LTX, and the reset power supply control line L VDDRT are driven by the control circuit unit 25.

Next, with reference to FIG. 11, the operation timing of the pixels constituting the pixel portion of the image pickup device, which is an example of the present invention, will be described. Each operation shown in FIG. 11 corresponds to each node in the circuit diagram of FIG. Further, each operation represents an operation of a time including between _{the read time t dark} of the reset signal of the pixel 1 and the read time t _{sig of the signal level of the pixel 1.}

The reset power control line L VDDRT constitutes the power supply VDD. This enables the pixel reading operation of the pixel unit 14. Next, the test signal input gate TFD (not shown) is grounded. As a result, the amplification transistor TSF of the test output signal unit (not shown) and the vertical signal line are cut off, and the output signal from each pixel 1 of the pixel unit 14 is read out.

The operation of reading the output signal of pixel 1 will be described in chronological order as follows. First, before the reset signal read time t _dark , the reset transistor RT is set to the reset control line LRT to the H level voltage VDD. As a result, the floating diffusion FD is reset to the reset potential VFD _dark .

At the reset signal read time t _{dark , the read signal processing unit 27 reads the potential level VFD dark} of the floating diffusion FD reset by the reset voltage as an output signal output from the amplification transistor SF to the vertical signal line 19.

After that, before the signal level read time t _sig , the transfer transistor TX is set to the H level voltage VDD on the transfer control line LTX, and the electrons (charges) accumulated in the photodiode PD are transferred to the floating diffusion FD (charge transfer). I do).

At the signal level read time t _sig , the read signal processing is performed as an output signal output from the amplification transistor SF to the vertical signal line 19 with _{the voltage VFD sig} of the signal level that fluctuates according to the number of electrons transferred by the charge transfer and the FD capacitance. The unit 27 reads out.

FIG. 12 is a diagram showing an example of a camera system to which the image sensor of the present invention is applied. The camera system 33 of FIG. 12 is mainly composed of a solid-state image sensor 23, a lens 35, a drive circuit 37, and a signal processing circuit 39. The image sensor shown in FIGS. 8 and 9 can be used as the solid-state image sensor 23.

The lens 35 can form an image of incident light on the imaging surface in the pixel region of the solid-state image sensor 23, and constitutes the optical system of the camera lens. The drive circuit 37 can drive the solid-state image sensor 23 and constitutes a drive unit of the camera system. The signal processing circuit 39 can perform predetermined signal processing on the output signal output from the solid-state image sensor 23, and constitutes a signal processing unit of the camera system.

The image signal processed by the signal processing circuit 39 is recorded in a recording medium such as a memory through an analog-to-digital conversion circuit (AFE) for analog output and through digital signal processing (DFE) for digital output. To. The image information recorded on the recording medium is hard-copied by a printer or the like. Further, the image signal processed by the signal processing unit is displayed as a moving image on a monitor such as a liquid crystal display.

As described above, by mounting the above-mentioned solid-state image pickup device on the image pickup apparatus, the above-mentioned effect of the present invention (the effect of improving the transfer characteristics while sufficiently securing the incident light of the photoelectric conversion element) can be obtained. A high-precision camera can be realized as a device.

Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes can be made within the scope of the invention described in the claims. It is possible.

1 pixel 3 photodiode 5 transistor 51 gate 52 first gate area 53 second gate area GW1 first gate width GW2 second gate width LD gate length direction WD gate width direction 54 extension 7 diffusion area 7a high concentration Region 7b Low concentration region (semiconductor substrate)
11 Transistor 13 Transistor 17 Pixel group 19 Vertical signal line 23 Solid-state image sensor

Japanese Unexamined Patent Publication No. 2003-258231

Claims (9)

Photoelectric conversion element and
A transfer transistor having a transfer gate connected to the photoelectric conversion element, and
A pixel unit including a floating diffusion region connected to the transfer gate.
The transfer gate
A first gate region having a first gate width in the gate width direction, connecting to the floating diffusion region and extending in the gate length direction away from the floating diffusion region,
A second gate region having a second gate width smaller than the first gate width in the gate width direction and continuously extending from the first gate region in the gate length direction is included.
It said second gate region, the first Ri from said first gate width in the direction away from the gate area of reduced gradually so that the second gate width,
The planar shape of the transfer gate, the pixel unit, wherein the shape der Rukoto obtained by cutting two corners of distant from the floating diffusion region of the square side. The pixel unit according to claim 1, wherein the second gate region is formed in a tapered shape . The pixel unit according to claim 1 or 2 , wherein the photoelectric conversion element, the transfer gate, and the floating diffusion region are arranged on a straight line. The floating diffusion region includes a first diffusion region and a second diffusion region having different diffusion impurity concentrations.
The first diffusion region has a higher impurity concentration than the second diffusion region.
The pixel unit according to any one of claims 1 to 3 , wherein the second diffusion region is adjacent to the first diffusion region so as to sandwich the first diffusion region. The pixel unit according to any one of claims 1 to 4 , further comprising a reset transistor connected to the floating diffusion region and resetting the electric charge accumulated in the floating diffusion region. The pixel unit according to any one of claims 1 to 5 , further comprising an amplification transistor that is connected to the floating diffusion region and amplifies the voltage converted in the floating diffusion region. The pixel unit according to any one of claims 1 to 6 , wherein the transfer gate further includes an extension portion extending from the transfer transistor toward the floating diffusion region. An image pickup device in which a plurality of pixel units according to any one of claims 1 to 7 are arranged.
Among the pixel units, some of the pixel units form a pixel unit row arranged side by side in the first direction.
An image pickup device in which a plurality of pixel unit rows are further arranged side by side in a second direction orthogonal to the first direction. The image pickup device according to claim 8 , wherein some of the pixel units constituting the pixel unit row are connected to one signal line for reading an electric signal of the pixel unit.

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