JP5725232B2 - Solid-state imaging device and camera - Google Patents

Solid-state imaging device and camera Download PDF

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JP5725232B2
JP5725232B2 JP2014087272A JP2014087272A JP5725232B2 JP 5725232 B2 JP5725232 B2 JP 5725232B2 JP 2014087272 A JP2014087272 A JP 2014087272A JP 2014087272 A JP2014087272 A JP 2014087272A JP 5725232 B2 JP5725232 B2 JP 5725232B2
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floating diffusion
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state imaging
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義治 工藤
義治 工藤
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ソニー株式会社
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  The present invention relates to a solid-state imaging device and a camera including the solid-state imaging device.

  Solid-state imaging devices are roughly classified into amplification-type solid-state imaging devices represented by CMOS (Complementary Metal Oxide Semiconductor) image sensors and charge transfer-type solid-state imaging devices represented by CCD (Charge Coupled Device) image sensors.

  Since CMOS image sensors have high functionality and low power consumption, replacement of conventional CCD image sensors is rapidly progressing particularly in image sensors for portable devices. The CMOS image sensor includes an imaging unit in which a plurality of pixels each including a photodiode (PD), which is a photoelectric conversion element, and a plurality of pixel transistors are regularly arranged, and a peripheral circuit arranged around the imaging unit. It is configured.

  Peripheral circuits include a column circuit (so-called vertical drive unit) that propagates signals in the column direction, a horizontal circuit (so-called horizontal transfer unit) that sequentially transmits the signals of each column propagated by the column circuit to the output circuit, etc. ing. As the plurality of pixel transistors, for example, a configuration including four transistors including a transfer transistor, a reset transistor, an amplifying transistor, and a selection transistor, or a configuration including three transistors other than the selection transistor is known.

  A general CMOS image sensor is configured by arranging a plurality of unit pixels each having one photodiode and a plurality of pixel transistors. However, in recent years, the pixel size has been remarkably miniaturized. In a CMOS image sensor having a large number of pixels, there are many CMOS image sensors in which a pixel transistor is shared by a plurality of pixels in order to reduce the number of pixel transistors per unit pixel.

  A CMOS image sensor sharing a pixel transistor is described in Patent Document 1, for example. On the other hand, it has been proposed to improve the charge transfer efficiency by devising the structure of the transfer gate in miniaturization of pixel dimensions. For example, in Patent Document 2 (see paragraph [0039], FIG. 3), as shown in FIG. 9, as a part of a pixel, a photodiode PD, a floating diffusion (FD) region 101, and transfer among pixel transistors are performed. A transistor Tr1 is provided. The transfer transistor Tr1 includes a transfer gate electrode 102 and a channel portion 103 directly below the transfer gate electrode 102. In the transfer transistor Tr1, the end of the transfer gate 104 on the photodiode PD side, that is, the end of the transfer gate electrode 102 is formed in a convex shape so that an electric field in the direction of the transfer gate 104 is easily generated in the photodiode PD. . However, in the configuration of FIG. 9, the channel width of the transfer gate 104 on the photodiode PD side (ie, the channel width in contact with the photodiode PD) a is equal to the channel width on the floating diffusion (FD) region side (ie, floating diffusion (FD)). The width of the channel in contact with the region is larger than b).

JP-A-11-331713 JP 2005-129965 A

  Incidentally, in the CMOS image sensor, as the pixel size is reduced, the gate size of the pixel transistor in the pixel is also reduced, and the characteristics of the pixel transistor cannot be maintained. For example, a gate of a transfer transistor (hereinafter referred to as a transfer gate) for reading a signal charge from a photodiode PD to a floating diffusion (FD) region also makes it difficult to achieve both cutoff characteristics and charge transfer characteristics due to the reduction in gate dimensions. ing. That is, when the transfer transistor is turned off, a leak current is likely to be generated from the photodiode (PD) to the floating diffusion (FD) region, and at the time of reading with the transfer transistor turned on, the channel modulation of the transfer gate is weak, so that the potential barrier is sufficient. It ’s not going down. However, increasing the gate size of the transfer gate in the determined pixel area reduces the area of the photodiode PD that performs photoelectric conversion, and has a trade-off relationship with the risk that light incidence is hindered by the transfer gate during light collection. It is in.

  On the other hand, in the configuration of the transfer gate shown in FIG. 9, since the transfer gate protrudes to the photodiode PD side, there is a risk that the area of the photodiode PD is reduced. This transfer gate structure causes a decrease in the saturation charge amount and obstruction of light incidence.

  In view of the above-described points, the present invention includes a solid-state imaging device capable of maintaining the transistor characteristics of the transfer transistor and sufficiently securing the light receiving area of the photoelectric conversion element even when the pixel is miniaturized, and the solid-state imaging device. Provide a camera.

  The solid-state imaging device of the present technology includes a plurality of pixels each including a photoelectric conversion element and a pixel transistor, and the channel width of the transfer gate in the transfer transistor of the pixel transistors is wider on the floating diffusion region side than on the photoelectric conversion element side. The transfer gate is disposed at the corner of the photoelectric conversion element and formed in a convex shape on the floating diffusion region side. The floating diffusion region is provided at a position surrounded by four photoelectric conversion elements, and is floating. The four photoelectric conversion elements surrounding the diffusion region share the floating diffusion region, the reset transistor, the amplification transistor, and the selection transistor.

  A camera of the present technology includes the solid-state imaging device, an optical system that guides incident light to a photoelectric conversion element of the solid-state imaging device, and a signal processing circuit that processes an output signal of the solid-state imaging device.

  According to the present invention, even if the pixel is miniaturized, the transistor characteristics of the transfer transistor can be maintained and the light receiving area of the photoelectric conversion element can be sufficiently secured.

It is a schematic block diagram which shows one Embodiment applied to the solid-state imaging device which concerns on this invention. It is a block diagram which shows the principal part of the pixel of 1st Embodiment which concerns on this invention. It is a block diagram which shows the principal part of the pixel of 2nd Embodiment which concerns on this invention. It is a schematic block diagram which shows other embodiment applied to the solid-state imaging device which concerns on this invention. It is a block diagram which shows the principal part of the pixel of 3rd Embodiment which concerns on this invention. FIG. 6 is a plan view illustrating an example of a layout of an imaging unit using the shared pixel in FIG. 5. FIG. 6 is a plan view illustrating another example of the layout of the imaging unit using the shared pixel in FIG. 5. It is a schematic block diagram which shows embodiment of the camera which concerns on this invention. It is a block diagram of the principal part which shows the example of the conventional pixel.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a schematic configuration of an embodiment applied to a solid-state imaging device according to the present invention, a so-called CMOS image sensor. The solid-state imaging device 1 according to the present embodiment includes an imaging unit (so-called pixel unit) 3 in which a plurality of pixels 2 are regularly arranged in two dimensions, and a peripheral circuit arranged around the imaging unit 3, that is, vertical drive. The unit 4 includes a horizontal transfer unit 5 and an output unit 6. The pixel 2 includes a photodiode PD that is one photoelectric conversion element and a plurality of pixel transistors (MOS transistors) Tr.

The photodiode PD has a region for photoelectrically converting light incident and accumulating signal charges generated by the photoelectric conversion. In this example, the plurality of pixel transistors Tr include four MOS transistors, that is, a transfer transistor Tr1, a reset transistor Tr2, an amplification transistor Tr3, and a selection transistor Tr4. The transfer transistor Tr1 is a transistor that reads the signal charge accumulated in the photodiode PD into a floating diffusion (FD) region described later. The reset transistor Tr2 is a transistor for setting the potential of the floating diffusion (FD) region to a specified value. The amplification transistor Tr3 is a transistor for electrically amplifying the signal charge read to the floating diffusion (FD) region. The selection transistor Tr4 is a transistor for selecting one row of pixels and reading a pixel signal to the vertical signal line 8.
Although not shown, it is possible to form a pixel with three transistors and the photodiode PD in which the selection transistor Tr4 is omitted.

  In the circuit configuration of the pixel 2, the source of the transfer transistor Tr1 is connected to the photodiode PD, and the drain thereof is connected to the source of the reset transistor Tr2. A floating diffusion (FD) region (corresponding to the drain region of the transfer transistor and the source region of the reset transistor) serving as a charge-voltage conversion unit between the transfer transistor Tr1 and the reset transistor Tr2 is connected to the gate of the amplification transistor Tr3. The source of the amplification transistor Tr3 is connected to the drain of the selection transistor Tr4. The drain of the reset transistor Tr2 and the drain of the amplification transistor Tr3 are connected to the power supply voltage supply unit. Further, the source of the selection transistor Tr4 is connected to the vertical signal line 8.

  A row reset signal φRST that is commonly applied from the vertical driving unit 4 to the gates of the reset transistors Tr2 of the pixels arranged in one row is also commonly applied to the gates of the transfer transistors Tr1 of the pixels of one row. Similarly, a row selection signal φSEL, to which the transfer signal φTRG is applied in common to the gates of the selection transistors Tr4 in one row, is supplied.

  The horizontal transfer unit 5 includes an amplifier or an analog / digital converter (ADC) connected to the vertical signal line 8 of each column, in this example, an analog / digital converter 9, a column selection circuit (switch means) SW, a horizontal And a transfer line (for example, a bus line composed of the same number of lines as the data bit lines) 10. The output unit 6 includes an amplifier, an analog / digital converter and / or a signal processing circuit, in this example, a signal processing circuit 11 for processing an output from the horizontal transfer line 10, and an output buffer 12. .

  In this solid-state imaging device 1, the signals of the pixels 2 in each row are analog / digital converted by the analog / digital converters 9 and read out to the horizontal transfer line 10 through the column selection circuits SW that are sequentially selected, and sequentially horizontal. Transferred. The image data read to the horizontal transfer line 10 is output from the output buffer 12 through the signal processing circuit 11.

  In general operation in the pixel 2, first, the gate of the transfer transistor Tr1 and the gate of the reset transistor Tr2 are turned on to empty all charges of the photodiode PD. Next, the gate of the transfer transistor Tr1 and the gate of the reset transistor Tr2 are turned off to perform charge accumulation. Next, immediately before reading out the charge of the photodiode PD, the gate of the reset transistor Tr2 is turned on to reset the potential of the floating diffusion (FD) region. Thereafter, the gate of the reset transistor Tr2 is turned off, and the gate of the transfer transistor Tr1 is turned on to transfer the charge from the photodiode PD to the floating diffusion (FD) region. The amplification transistor Tr3 electrically amplifies the signal charge in response to the charge being applied to the gate. On the other hand, the selection transistor Tr4 is turned on only for the pixel to be read from the floating diffusion reset immediately before the reading, and the charge-voltage converted image signal from the corresponding pixel amplification transistor Tr3 is read to the vertical signal line 8. become.

  In the present embodiment, in the solid-state imaging device 1 described above, the signal charge is transferred to the floating diffusion (FD) region while sufficiently securing the area of the photodiode PD even if the pixel is miniaturized. The transfer gate of the transfer transistor Tr1 is configured so that it can be satisfactorily performed. That is, in this embodiment, the channel width of the transfer gate is configured to be wider on the floating diffusion (FD) region side than on the photodiode PD side. Further, the conversion efficiency can be improved.

  FIG. 2 shows a first embodiment of a region including a photodiode PD, a floating diffusion (FD) region 20, and a transfer transistor Tr1, particularly a transfer gate 21 thereof, constituting the pixel of the present invention. In the first embodiment, the transfer gate electrode 22 constituting the transfer gate 21 of the transfer transistor Tr1 is arranged at one corner of the photodiode PD having a square shape in plan view, and a floating diffusion (so-called diffusion region) FD. It is formed to have a convex shape on the side.

  That is, the transfer gate electrode 22 has a substantially trapezoidal shape in which the top of a triangle is cut, and one side (bottom side) thereof is adjacent to a side obtained by obliquely cutting off a corner on the photodiode PD side, Two sides that are substantially L-shaped are formed adjacent to the floating diffusion (FD) region 20. As a result, in the illustrated example, the photodiode PD of the unit pixel is formed in a pentagonal shape in which one corner of a square shape such as a square or a rectangle is cut slightly diagonally in a straight line. The floating diffusion (FD) region 20 has a substantially L-shaped planar shape.

  The element isolation region 24 is formed so as to surround the photodiode PD, the floating diffusion (FD) region 20, and the transfer transistor Tr1, and is formed so as to partially enter under the transfer gate electrode 22. That is, a part of the element isolation region 24 is formed so that the channel portion 23 of the transfer gate 21 substantially extends to the photodiode PD side with a width across the L-shaped ends of the floating diffusion (FD) region 20. It is formed under the transfer gate electrode 22.

  Here, the photodiode PD is not shown, but in this example, an n-type semiconductor region (n + region) serving as a charge storage region is formed in the p-type semiconductor well region, and accumulation is performed on the surface side of the n-type semiconductor region. This is configured as a buried photodiode in which a p-type semiconductor region (p + region) to be a layer is formed. The floating diffusion (FD) region 20 corresponds to the drain region of the transfer transistor Tr1, and is formed of an n-type semiconductor region (n + region) in this example. Further, the element isolation region 24 is formed of a p-type semiconductor region (p + region) in this example.

  Further, in the present embodiment, a part of the substantially L-shaped floating diffusion (FD) region 20, that is, a part corresponding to the top (protrusion tip) of the transfer gate electrode 22 has a small area. This is formed in a region 26 with a high impurity concentration (so-called high concentration region: n + region in this example). Further, the other part in the region of the substantially L-shaped floating diffusion (FD) region 20, that is, the region surrounding the high concentration region 26 and corresponding to the region between the high concentration region 26 and the element isolation region 24. The portion is formed in a region 27 (so-called low concentration region: n− region in this example) whose impurity concentration is lower than that of the high concentration region 26.

  The impurity concentration of the low concentration region 27 is lower than that of a normal LDD structure, and the region 27 is lower than the low impurity concentration region in the vicinity of the junction that is naturally formed by the formation of a normal PN junction. Also has a large area.

On the other hand, the high concentration region 26 in the floating diffusion (FD) region 20 is shared with the contact region when connecting to the pixel transistor. In this example, the impurity concentration of the high concentration region 26 can be set to 1 × 10 20 cm −3 or more. Further, the impurity concentration of the low concentration region 27 can be less than 1 × 10 18 cm −3 .

  According to the configuration of the first embodiment, the corners of the photodiode PD are slightly reduced by forming the transfer gate electrode 22 in a substantially trapezoidal shape so that the floating diffusion (FD) region 20 side is convex. As a result, the area of the photodiode PD can be secured widely. As a result, even if the pixel is miniaturized, the incident light is not hindered by the transfer gate electrode during light collection, and a sufficient saturation charge amount can be secured.

  Further, as shown in FIG. 2, the channel width of the transfer gate 21 is wider on the floating diffusion (FD) region 20 side than on the photodiode PD side, so that both the cutoff characteristics and charge transfer characteristics of the transfer transistor are achieved. So-called transistor characteristics can be maintained. That is, the channel width B on the floating diffusion (FD) region 20 side is wider than the channel width A on the photodiode PD side. This change in the channel width leads to a change in the potential of the channel portion 23, and when the transfer transistor is turned on, an electric field is generated in which the potential increases from the photodiode PD side to the floating diffusion (FD) region 20 side due to the shape effect. . The narrow channel width A has a shallow potential, and the wide channel width B has a deep potential. Therefore, it is possible to transfer the signal charge from the photodiode PD to the floating diffusion (FD) region 20 satisfactorily, and the signal charge transfer capability can be improved even if the pixel is miniaturized. Leakage current hardly occurs when the transfer transistor is off.

  The reason why the leak current hardly occurs will be described. When the channel width W is constant, the amount of change in the channel potential is the same on the photodiode PD side and the floating diffusion FD side. Therefore, when the potential is varied to apply the transfer direction electric field to the channel when the transfer gate is on, Sometimes there is a difference in potential. In contrast, in this embodiment, since the potential change on the photodiode FD side is large, if the channel potential difference between the photodiode PD side and the floating diffusion FD side when on is the same as the above, the potential difference when off is Can be small. That is, since the closing of the channel when the photodiode FD side is OFF is strengthened, the leakage current can be reduced.

  By sharing the high concentration region 26 of the floatin diffusion (FD) region with the contact portion, that is, sharing it, the area of the high concentration region can be minimized. In the present embodiment, the high concentration region 26 is not required except for the position where the contact portion is placed. In a normal CMOS process, the high-concentration region is formed by impurity implantation using a resist mask, and thus is sufficiently larger than the contact area of the contact portion. In general, only a part of the diffusion region in contact with the gate has a high concentration.

  On the other hand, when the floating diffusion (FD) region 20 is L-shaped, the area of the floating diffusion (FD) region 20 increases. Usually, the increase in area increases the diffusion capacity (so-called junction capacity) in the floating diffusion (FD) region 20, leading to a decrease in conversion efficiency. However, in the present embodiment, a part of the L-shaped floating diffusion (FD) region 20 corresponding to the convex portion of the transfer gate 21 that substantially stores charges and the contact portion are shared. The impurity concentration distribution is set so that the n-type high concentration region 26 is formed and the other regions become the n-type low concentration region 27. The junction capacitance in the low concentration region 27 is very small. Therefore, the entire junction capacitance in the floating diffusion (FD) region 20 does not increase extremely, and the reduction in conversion efficiency is reduced.

  The signal charges transferred from the photodiode PD to the low concentration region 27 where the potential of the floating diffusion (FD) region 20 is shallow are collected in the high concentration region 26 where the potential is deep.

  FIG. 3 shows a second embodiment of a region including a photodiode PD, a floating diffusion (FD) region 20, and a transfer transistor Tr1, particularly its transfer gate, constituting the pixel of the present invention. In the present embodiment, a transfer gate 21 is formed between the photodiode PD and the floating diffusion (FD) region 20 so that the channel width is wider on the floating diffusion (FD) region 20 than on the photodiode PD. A transistor Tr1 is formed.

  The photodiode PD has a square shape such as a square or a rectangle. The floating diffusion (FD) region 20 has a rectangular shape in which the length of the side facing the photodiode PD is the same as the length of the facing side of the photodiode PD. The transfer gate 21 includes a rectangular transfer gate electrode 22 and a trapezoidal channel portion 23. The channel portion 23 has a channel width A on the photodiode PD side narrower than a channel width B on the floating diffusion (FD) region 20 side, and the channel of the transfer gate 21 from the photodiode PD toward the floating diffusion (FD) region 20. The portion 23 is formed in a trapezoidal shape so that the width gradually increases.

  On the other hand, the floating diffusion (FD) region 20 is formed with a high concentration region (n + region in this example) 26 at the center of the rectangle as in the above example, and a low concentration region (n− in this example) in the remaining region. Region) 27 is formed. Other configurations such as the impurity concentration are the same as those described in the first embodiment, and a duplicate description is omitted.

  According to the configuration of the second embodiment, since the photodiode PD is formed in a quadrangular shape, a large area can be secured, and a sufficient saturation charge amount can be secured even if the pixels are miniaturized. Further, an electric field is generated in which the potential of the channel portion 23 of the transfer gate 21 gradually increases from the photodiode PD side toward the floating diffusion (FD) region 20 side. Therefore, it is possible to transfer the signal charge from the photodiode PD to the floating diffusion (FD) region 20 satisfactorily, and the signal charge transfer capability can be improved even if the pixel is miniaturized.

  On the other hand, since the floating diffusion (FD) region 20 is formed by the high concentration region 26 and the low concentration region 27, the entire junction capacitance in the floating diffusion (FD) region 20 can be suppressed to a low level. Efficiency can be reduced.

  Also in the second embodiment, the signal charges transferred to the low concentration region 27 of the floating diffusion (FD) region 20 are collected in the high concentration region 26. In addition, the same effects as described in the first embodiment can be obtained.

  The configuration of the first embodiment shown in FIG. 2 is effective when applied to a CMOS image sensor in which pixel transistors are shared by a plurality of photodiodes. Next, the embodiment will be described.

  FIG. 4 shows a schematic configuration of another embodiment applied to a solid-state imaging device according to the present invention, a so-called CMOS image sensor. The solid-state imaging device according to this embodiment includes a plurality of pixel sets in this example, that is, a pixel configuration in which other pixel transistors except for a transfer transistor are shared with four pixels, that is, four photodiodes that are photoelectric conversion elements ( This is a case where shared pixels are arranged below.

  The solid-state imaging device 31 according to the present embodiment includes an imaging unit (so-called pixel unit) 3 in which a plurality of shared pixels 32 are two-dimensionally arranged with regularity, and a peripheral circuit arranged around the imaging unit 3, that is, a vertical circuit. The drive unit 4, the horizontal transfer unit 5, and the output unit 6 are included. The shared pixel 32 includes a plurality of photodiodes PD, which are four photoelectric conversion elements in this example, four transfer transistors, one reset transistor, an amplification transistor, and a selection transistor.

  In the circuit configuration of the shared pixel 32, as shown in FIG. 4, each of the four photodiodes PD [PD1, PD2, PD3, PD4] is connected to the sources of the corresponding four transfer transistors Tr11, Tr12, Tr13, Tr14. Then, the drains of the transfer transistors Tr11 to Tr14 are connected to the source of one reset transistor Tr2. A common floating diffusion (FD) region serving as charge-voltage conversion means between the transfer transistors Tr11 to Tr14 and the reset transistor Tr2 is connected to the gate of one amplification transistor Tr3. The source of the amplification transistor Tr3 is connected to the drain of one selection transistor Tr4. The drain of the reset transistor Tr2 and the drain of the amplification transistor Tr3 are connected to the power supply voltage supply unit. Further, the source of the selection transistor Tr4 is connected to the vertical signal line 8.

  Row transfer signals φTRG1 to φTRG4 are applied to the gates of the transfer transistors Tr11 to Tr14, respectively, a row reset signal φRST is applied to the gate of the reset transistor Tr2, and a row selection signal φSEL is applied to the gate of the selection transistor Tr4. Is done.

  The configurations of the vertical drive unit 4, the horizontal transfer unit 5, the output unit 6, and others are the same as those described with reference to FIG.

  FIG. 5 shows the configuration of the shared pixel 32 in the present embodiment on the plane, that is, the third embodiment. The set of shared pixels 32 of this embodiment uses the pixel configuration shown in FIG. 2 and has a shared configuration of two horizontal and two vertical pixels. In the present embodiment, as shown in FIG. 5, a common floating diffusion (FD) region 20 is arranged at the center so as to share the floating diffusion (FD) region 20. The four pixels (pixel configuration in FIG. 2) are horizontally and vertically symmetric with respect to the corner on the transfer gate 21 [211 to 214] side so that the floating diffusion (FD) region 20 is sandwiched between them. Be placed. At this time, the central floating diffusion (FD) region 20 has a cross-like shape on a plane, and the center is formed as a high concentration region 26 and the other arms are formed as a low concentration region 27. In addition, the element isolation region 24 that separates the photodiodes PD1 to PD4 comes into contact with only the tip of the low concentration region 27 of each arm with respect to the contact with the floating diffusion (FD) region 20. Other configurations are the same as those in FIG.

  According to the shared pixel configuration according to the third embodiment, the four pixels are arranged symmetrically around the floating diffusion (FD) region 20, in other words, around the corner of the transfer gate. Thus, in the imaging unit 3 that arranges a large number of pixels, the pixel arrangement can be densely arranged. In the present embodiment, the channel width of the transfer gate changes from the photodiode PD side toward the floating diffusion (FD) region 20 due to the shape effect of the transfer gate as described above, and the channel potential changes. The signal charge transfer efficiency is improved.

Further, the shared floating diffusion (FD) region 20 has a cross shape, and has a configuration in which the central portion is a high concentration region 26 and the other is a low concentration region 27, and therefore, the floating diffusion (FD) region 20. The junction capacitance of the capacitor becomes very small, and the conversion efficiency at the time of charge-voltage conversion can be increased, or the decrease in conversion efficiency can be reduced. In particular, the contact portion between the n-type floating diffusion (FD) region 20 and the p-type element isolation region 24 is only the end of the arm portion which is a cross-shaped low-concentration region 27. Therefore, the floating diffusion (FD) The junction capacitance between the region 20 and the element isolation region 24 is further reduced, and the conversion efficiency can be improved correspondingly.
In addition, the same effects as described in the configuration of the first embodiment can be obtained.

  FIG. 6 shows an embodiment of the layout of the imaging unit 3 using the shared pixel 32 of FIG. In the present embodiment, the shared pixels 32 are arranged in a square array. That is, in this embodiment, the reset transistor Tr2, the amplification transistor Tr3, and the selection transistor Tr4 are arranged on one side in the vertical direction in each shared pixel 32, in this example, on the lower side in each shared pixel 32. The shared pixels 32 are arranged in an orthogonal coordinate system in the vertical direction and the horizontal direction. The reset transistor Tr2 includes a source region 41, a drain region 42, and a reset gate electrode 43. The amplification transistor Tr3 includes a source region 44, a drain region 45, and an amplification gate electrode 46. The selection transistor Tr4 includes a source region 47, a drain region 44, and a selection gate electrode 48. At this time, the source region 44 of the amplification transistor Tr3 and the drain region 44 of the selection transistor Tr4 are formed in common.

  Then, the high concentration region 26 of the floating diffusion (FD) region 20 is connected to the source region 41 of the reset transistor Tr2 and the amplification gate electrode 46 of the amplification transistor Tr3 via the wiring 49. Further, the source region 47 of the selection transistor Tr4 and the vertical signal line 8 are connected via the wiring 50.

  According to the layout of the imaging unit in FIG. 6, a large number of shared pixels 32 can be densely arranged in the horizontal and vertical directions, and a high-resolution solid-state imaging device can be provided.

  FIG. 7 shows another embodiment of the layout of the imaging unit 3 using the shared pixel 32 of FIG. In the present embodiment, the shared pixels 32 are arranged in an oblique arrangement (also referred to as a honeycomb arrangement). That is, in the present embodiment, as described with reference to FIG. 5, the reset transistor Tr2, the amplification transistor Tr3, and the selection transistor Tr4 on one side in the vertical direction in each shared pixel 32, in this example, on the lower side in each shared pixel 32. Is placed. The shared pixels 32 are arranged in a coordinate system orthogonal to an axis inclined obliquely from the vertical direction and the horizontal direction. In the example of FIG. 7, the shared pixels 32 are arranged in a coordinate system orthogonal to an axis inclined 45 ° from the vertical direction and the horizontal direction. Since the other configuration is the same as that described with reference to FIG. 6, portions corresponding to those in FIG.

  According to the layout of the imaging unit in FIG. 7, a large number of shared pixels 32 can be densely arranged, and a higher-resolution solid-state imaging device can be provided as compared with FIG.

  FIG. 8 is a schematic configuration of a camera using the above-described CMOS type solid-state imaging device. The camera 40 of this embodiment includes an optical system (optical lens) 41, a CMOS solid-state imaging device 42, and a signal processing circuit 43. The solid-state imaging device 42 is a solid-state imaging device having the pixel configuration of any one of the first to third embodiments described above, preferably the first and third embodiments, and a solid having the layout shown in FIGS. It is applied to an imaging device. The camera of the present embodiment includes a camera module in which an optical system 41, a CMOS solid-state imaging device 42, and a signal processing circuit 43 are modularized. The optical system 41 forms image light (incident light) from the subject on the imaging surface of the CMOS solid-state imaging device 42. Thereby, in the photoelectric conversion element (light receiving part) of the CMOS type solid-state imaging device 42, incident light is converted into a signal charge according to the amount of incident light, and the signal charge is accumulated in the photoelectric conversion element for a certain period. The signal processing circuit 43 performs various signal processing on the output signal of the CMOS type solid-state imaging device 42 and outputs it as a video signal.

  According to the camera of this embodiment, the saturation charge amount and the conversion efficiency are ensured even when the pixel is miniaturized, and the signal charge transfer to the floating diffusion of the signal charge is improved, thereby providing a high-resolution camera. be able to.

  In the present invention, it is also possible to configure an electronic device including the above-described camera of FIG. 8 or a camera module.

  1, 31 Solid-state imaging device, 2 pixels, 3 imaging unit, 4 vertical drive unit, 5 horizontal transfer unit, 6 output unit, PD, PD1 to PD4 electrical conversion element, FD floating diffusion region, 21, 211-214 transfer gate , 22 Transfer gate electrode, 23 channel portion, 24 element isolation region, 26 high concentration region, 27 low concentration region, 32 shared pixels

Claims (19)

  1. A plurality of pixels composed of photoelectric conversion elements and pixel transistors are arranged,
    The channel width of the transfer gate in the transfer transistor of the pixel transistors is configured to be wider on the floating diffusion region side than the photoelectric conversion element side,
    The transfer gate is disposed at a corner of the photoelectric conversion element, and is formed in a convex shape on the floating diffusion region side,
    The floating diffusion region is provided at a position surrounded by the four photoelectric conversion elements,
    The four photoelectric conversion elements surrounding the floating diffusion region share the floating diffusion region, a reset transistor, an amplification transistor, and a selection transistor.
  2.   The solid-state imaging device according to claim 1, wherein the transfer gate has a substantially trapezoidal shape.
  3. The transfer gate is in a direction parallel to a straight line connecting both ends of the position where the floating diffusion region and the transfer gate are in contact with each other.
    The length between the end portions of the transfer gate at a position in contact with the floating diffusion region has a portion that decreases from a straight line connecting the both end portions toward the floating diffusion region side. Solid-state imaging device.
  4.   The solid-state imaging device according to claim 1, wherein a high concentration region is formed in a part of the floating diffusion region.
  5.   The solid-state imaging according to claim 4, wherein the high-concentration region of the floating diffusion region is surrounded by a low-concentration region lower than an impurity concentration of the high-concentration region. apparatus.
  6.   The solid-state imaging device according to claim 4, wherein the high concentration region of the floating diffusion region is shared with a contact portion.
  7.   The solid-state imaging device according to claim 4, wherein the high-concentration region is adjacent to a tip of a convex portion of the transfer gate.
  8.   8. The set of a plurality of photoelectric conversion elements and a plurality of the transfer transistors that read signal charges of the photoelectric conversion elements are arranged in an orthogonal coordinate system in the vertical and horizontal directions. Solid-state imaging device.
  9.   The pixel includes a first row in which two of the four photoelectric conversion elements surrounding the floating diffusion region are arranged, a second row in which the other two photoelectric conversion elements are arranged, and The solid-state imaging device according to claim 1, wherein the solid-state imaging device has a planar arrangement including a third row in which the reset transistor, the amplification transistor, and the selection transistor are arranged.
  10.   The solid-state imaging device according to claim 1, wherein an image signal from the pixel transistor is read out to a vertical signal line.
  11.   The solid-state imaging device according to claim 10, further comprising a horizontal transfer unit connected to the vertical signal line, wherein the image signal is read from the vertical signal line to the horizontal transfer unit.
  12.   The solid-state imaging device according to claim 11, wherein the horizontal transfer unit includes at least one selected from an amplifier, an analog / digital converter, a column selection circuit, and a horizontal transfer line.
  13.   The solid-state imaging device according to claim 1, further comprising an analog / digital converter, which converts a pixel signal into a digital signal.
  14.   The solid-state imaging device according to claim 13, wherein a signal processing circuit is disposed downstream of the analog / digital converter and performs signal processing on the digital signal.
  15.   The solid-state imaging device according to claim 1, wherein the element isolation region is provided at least between the photoelectric conversion element and the reset transistor, the amplification transistor, and the selection transistor. .
  16.   The solid-state imaging device according to claim 1, further comprising a channel portion in a region surrounded by the photoelectric conversion element, the floating diffusion region, and the element isolation region under the transfer gate.
  17.   Under the transfer gate, the length of the channel width on the photoelectric conversion element side where the photoelectric conversion element and the channel part are connected is equal to the floating diffusion area side where the floating diffusion area and the channel part are connected. The solid-state imaging device according to claim 16, which is smaller than the length of the channel width.
  18.   18. The solid according to claim 16, wherein the floating diffusion region, the photoelectric conversion element, and the element isolation region surrounding the channel portion are formed of a semiconductor layer having a conductivity type opposite to that of the floating diffusion region. Imaging device.
  19. A solid-state imaging device;
    An optical system for guiding incident light to the photoelectric conversion element of the solid-state imaging device;
    A signal processing circuit for processing an output signal of the solid-state imaging device,
    The solid-state imaging device
    A plurality of pixels composed of photoelectric conversion elements and pixel transistors are arranged,
    The channel width of the transfer gate in the transfer transistor of the pixel transistors is configured to be wider on the floating diffusion region side than the photoelectric conversion element side,
    The transfer gate is disposed at a corner of the photoelectric conversion element, and is formed in a convex shape on the floating diffusion region side,
    The floating diffusion region is provided at a position surrounded by the four photoelectric conversion elements,
    The four photoelectric conversion elements surrounding the floating diffusion region share the floating diffusion region, a reset transistor, an amplification transistor, and a selection transistor.
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