JP6536627B2 - Solid-state imaging device and electronic device - Google Patents

Description

  The present invention relates to a solid-state imaging device and an electronic apparatus equipped with the solid-state imaging device.

  Solid-state imaging devices are roughly classified into an amplification type solid-state imaging device represented by a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and a charge transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) image sensor.

  Because of their high functionality and low power consumption, CMOS image sensors are rapidly replacing conventional CCD image sensors in image sensors particularly for portable devices. The CMOS image sensor includes an imaging unit in which a plurality of pixels each including a photodiode (PD), which is a photoelectric conversion element, and a plurality of pixel transistors are regularly two-dimensionally arrayed, and peripheral circuits disposed around the imaging unit. It is configured to have.

  The peripheral circuits include a column circuit (so-called vertical drive unit) for propagating a signal in the column direction, a horizontal circuit (so-called horizontal transfer unit) for sequentially transmitting the signals of each column propagated by the column circuit to an output circuit, etc. ing. As the plurality of pixel transistors, for example, a configuration of four transistors of a transfer transistor, a reset transistor, an amplification transistor and a selection transistor, or a configuration of three other transistors excluding the selection transistor is known.

  A general CMOS image sensor is configured by arranging a plurality of unit pixels in which one photodiode and a plurality of pixel transistors are set. However, in recent years, miniaturization of the pixel size is remarkable. In a CMOS image sensor having a large number of pixels, there are also many CMOS image sensors in which pixel transistors are shared by a plurality of pixels in order to reduce the number of pixel transistors per unit pixel.

  A pixel transistor shared CMOS image sensor is described, for example, in Patent Document 1. On the other hand, it has been proposed to improve charge transfer efficiency by devising the structure of transfer gates in the miniaturization of pixel dimensions. For example, in Patent Document 2 (see paragraph [0039] and FIG. 3), as shown in FIG. 9, the photodiode PD, the floating diffusion (FD) region 101, and the transfer of the pixel transistor as part of the pixel. A transistor Tr1 is provided. The transfer transistor Tr1 is configured to include the transfer gate electrode 102 and the channel portion 103 immediately below it. Then, in the transfer transistor Tr1, the end of the transfer gate 104 on the photodiode PD side, that is, the end of the transfer gate electrode 102 is formed in a convex shape, so that an electric field in the direction of the transfer gate 104 can be easily generated in the photodiode PD. . However, in the configuration of FIG. 9, the channel width on the photodiode PD side of the transfer gate 104 (that is, the channel width in contact with the photodiode PD) a is the channel width on the floating diffusion (FD) region side (that is, floating diffusion (FD)). It is wider than the channel width b) in contact with the region.

Unexamined-Japanese-Patent No. 11-331713 gazette JP 2005-129965 A

  By the way, in the CMOS image sensor, as the pixel size is reduced, the gate size of the pixel transistor in the pixel is also reduced, and the characteristics of the pixel transistor can not be maintained. For example, the gate of a transfer transistor for reading out signal charges from the photodiode PD to the floating diffusion (FD) region (hereinafter referred to as a transfer gate) also has difficulty in achieving both cutoff characteristics and charge transfer characteristics due to the reduction of the gate size. ing. That is, when the transfer transistor is off, a leakage current is easily generated from the photodiode (PD) to the floating diffusion (FD) region, and when the transfer transistor is turned on, channel modulation of the transfer gate is weak. It is getting worse. However, increasing the gate size of the transfer gate in a determined pixel area narrows the area of the photodiode PD that performs photoelectric conversion, and has a trade-off relationship with the risk that light incidence is blocked by the transfer gate at the time of light collection. It is in.

  On the other hand, in the configuration of the transfer gate shown in FIG. 9, since the transfer gate protrudes to the photodiode PD side, there is a risk that the area of the photodiode PD may be reduced. This transfer gate structure causes a decrease in the amount of saturation charge and an inhibition of light incidence.

In view of the above, the present invention is provided with a solid-state imaging device capable of maintaining the transistor characteristics of the transfer transistor and sufficiently securing the light receiving area of the photoelectric conversion element even when the pixel is miniaturized, and the solid-state imaging device Provide an electronic device .

In the solid-state imaging device according to the present technology, a plurality of pixels each including a photoelectric conversion element and a pixel transistor are arrayed, and a first photoelectric conversion element, a second photoelectric conversion element, and a third photoelectric conversion element are used as photoelectric conversion elements. , A first photoelectric conversion element, a first photoelectric conversion element, a second photoelectric conversion element, a third photoelectric conversion element, and a first transfer gate corresponding to a fourth photoelectric conversion element, It has a second transfer gate, a third transfer gate, and a fourth transfer gate. Then, as a pixel transistor, having a first transfer transistor, the second transfer transistor, and a third transfer transistor, and a fourth transfer transistor, a reset transistor, an amplification transistor, a selection transistor. At least a part of the floating diffusion region is disposed at a position surrounded by the first photoelectric conversion element, the second photoelectric conversion element, the third photoelectric conversion element, and the fourth photoelectric conversion element. The transfer transistor, the second transfer transistor, the third transfer transistor, and the fourth transfer transistor are connected to the floating diffusion region, the reset transistor, the amplification transistor, and the selection transistor.
Furthermore, the first photoelectric conversion device and the second photoelectric conversion device are disposed in the first row of pixels, and the third photoelectric conversion device and the fourth photoelectric conversion device are arranged in the second row of pixels. And the reset transistor, the amplification transistor, and the selection transistor are disposed in the third row of pixels, and the second row is disposed between the first row and the third row.
The first transfer gate, the second transfer gate, the third transfer gate, and the fourth transfer gate respectively have a first side, a second side, a third side, and a fourth side. Have. The first side of the first transfer gate, the first side of the second transfer gate, the first side of the third transfer gate, and the first side of the fourth transfer gate are each a floating diffusion. It is formed facing the area. The second side of the first transfer gate, the second side of the second transfer gate, the second side of the third transfer gate, and the second side of the fourth transfer gate are respectively the first And the second photoelectric conversion element, the third photoelectric conversion element, and the fourth photoelectric conversion element. As for the first transfer gate, the second transfer gate, the third transfer gate, and the fourth transfer gate, the first side is closer to the second side, the third side, and the fourth side. The second side is formed longer than the first side, the third side, and the fourth side .

In addition, an electronic device according to the present technology includes the solid-state imaging device, an optical system that guides incident light to a photoelectric conversion element of the solid-state imaging device, and a signal processing circuit that processes an output signal of the solid-state imaging device.

  According to the present invention, even if the pixel is miniaturized, the transistor characteristics of the transfer transistor can be maintained, and the light receiving area of the photoelectric conversion element can be sufficiently secured.

It is a schematic block diagram which shows one Embodiment applied to the solid-state imaging device concerning this invention. It is a block diagram which shows the principal part of the pixel of 1st Embodiment which concerns on this invention. It is a block diagram which shows the principal part of the pixel of 2nd Embodiment concerning this invention. It is a schematic block diagram which shows other embodiment applied to the solid-state imaging device concerning this invention. It is a block diagram which shows the principal part of the pixel of 3rd Embodiment concerning this invention. It is a top view which shows an example of a layout of an imaging part using the share pixel of FIG. It is a top view which shows the other example of the layout of the imaging part using the share pixel of FIG. It is a schematic block diagram which shows embodiment of the camera which concerns on this invention. It is a block diagram of the principal part which shows the example of the conventional pixel.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a schematic configuration of an embodiment applied to a solid-state imaging device according to the present invention, a so-called CMOS image sensor. The solid-state imaging device 1 according to the present embodiment includes an imaging unit (so-called pixel unit) 3 in which a plurality of pixels 2 are two-dimensionally arrayed with regularity, and peripheral circuits disposed around the imaging unit 3, that is, vertical drive The configuration includes a unit 4, a horizontal transfer unit 5, and an output unit 6. The pixel 2 includes a photodiode PD, which is one photoelectric conversion element, and a plurality of pixel transistors (MOS transistors) Tr.

The photodiode PD has a region that is photoelectrically converted upon light incidence and stores the signal charge generated by the photoelectric conversion. In this example, the plurality of pixel transistors Tr include four MOS transistors of a transfer transistor Tr1, a reset transistor Tr2, an amplification transistor Tr3, and a selection transistor Tr4. The transfer transistor Tr1 is a transistor that reads out the signal charge stored in the photodiode PD into a floating diffusion (FD) region described later. The reset transistor Tr2 is a transistor for setting the potential of the floating diffusion (FD) region to a prescribed value. The amplification transistor Tr3 is a transistor for electrically amplifying the signal charge read out to the floating diffusion (FD) region. The selection transistor Tr4 is a transistor for selecting a row of pixels and reading a pixel signal to the vertical signal line 8.
Although not shown, it is also possible to form a pixel with three transistors in which the selection transistor Tr4 is omitted and the photodiode PD.

  In the circuit configuration of the pixel 2, the source of the transfer transistor Tr1 is connected to the photodiode PD, and the drain thereof is connected to the source of the reset transistor Tr2. A floating diffusion (FD) region (corresponding to a drain region of the transfer transistor and a source region of the reset transistor) serving as charge-voltage conversion means between the transfer transistor Tr1 and the reset transistor Tr2 is connected to the gate of the amplification transistor Tr3. The source of the amplification transistor Tr3 is connected to the drain of the selection transistor Tr4. The drain of the reset transistor Tr2 and the drain of the amplification transistor Tr3 are connected to the power supply voltage supply unit. Further, the source of the selection transistor Tr4 is connected to the vertical signal line 8.

  A row reset signal φRST commonly applied to the gates of the reset transistors Tr2 of the pixels arranged in one row from the vertical drive unit 4 is commonly applied to the gates of the transfer transistors Tr1 of the pixels in one row. A row selection signal .phi.SEL to which the transfer signal .phi.TRG is applied in common to the gates of the selection transistors Tr4 in one row is also supplied.

  The horizontal transfer unit 5 includes an amplifier or an analog / digital converter (ADC) connected to the vertical signal line 8 of each column, in this example, an analog / digital converter 9, a column selection circuit (switching means) SW, and a horizontal And a transfer line (e.g., a bus line composed of the same number of lines as the data bit line) 10. The output unit 6 is configured to include an amplifier or an analog / digital converter and / or a signal processing circuit, a signal processing circuit 11 processing an output from the horizontal transfer line 10 in this example, and an output buffer 12 .

  In this solid-state imaging device 1, the signals of the pixels 2 in each row are analog / digital converted by each analog / digital converter 9, read out to the horizontal transfer line 10 through the sequentially selected column selection circuit SW, and sequentially horizontal To be transferred. The image data read out to the horizontal transfer line 10 is output from the output buffer 12 through the signal processing circuit 11.

  In the general operation of the pixel 2, first, the gate of the transfer transistor Tr1 and the gate of the reset transistor Tr2 are turned on to empty all the charge of the photodiode PD. Next, charge accumulation is performed with the gate of the transfer transistor Tr1 and the gate of the reset transistor Tr2 turned off. Next, immediately before reading out the charge of the photodiode PD, the gate of the reset transistor Tr2 is turned on to reset the potential of the floating diffusion (FD) region. Thereafter, the gate of the reset transistor Tr2 is turned off, and the gate of the transfer transistor Tr1 is turned on to transfer the charge from the photodiode PD to the floating diffusion (FD) region. The amplification transistor Tr3 electrically amplifies the signal charge in response to the charge applied to the gate. On the other hand, the selection transistor Tr4 turns on only the readout target pixel from the floating diffusion reset immediately before the readout, and the charge-voltage converted image signal from the corresponding in-pixel amplification transistor Tr3 is read out to the vertical signal line 8. become.

  Then, in the present embodiment, in the solid-state imaging device 1 described above, transfer of signal charges to the floating diffusion (FD) region is performed while securing the area of the photodiode PD sufficiently even if the pixels are miniaturized. The transfer gate of the transfer transistor Tr1 is configured to perform well. That is, in the present embodiment, the channel width of the transfer gate is configured to be wider on the floating diffusion (FD) region side than on the photodiode PD side. Furthermore, it is configured to be able to improve the conversion efficiency.

  FIG. 2 shows a first embodiment of a region including the photodiode PD constituting the pixel of the present invention, the floating diffusion (FD) region 20, and the transfer transistor Tr1, particularly the transfer gate 21 thereof. In the first embodiment, the transfer gate electrode 22 constituting the transfer gate 21 of the transfer transistor Tr1 is disposed at one corner of the photodiode PD having a square planar shape, and the floating diffusion (so-called diffusion region) FD It is formed to be convex on the side.

  That is, transfer gate electrode 22 has a substantially trapezoidal shape such that the top of a triangle is cut, and one side (bottom side) is adjacent to the side obtained by obliquely cutting the corner on the photodiode PD side in a straight line. The two substantially L-shaped sides are formed adjacent to the floating diffusion (FD) region 20. As a result, in the illustrated example, the photodiode PD of the unit pixel is formed into a pentagon in which one corner of a square such as a square or a rectangle having a planar shape is obliquely cut in a slightly linear manner. In addition, the floating diffusion (FD) region 20 is formed to be substantially L-shaped in plan view.

  The element isolation region 24 is formed so as to surround the photodiode PD, the floating diffusion (FD) region 20, and the transfer transistor Tr1, and is formed so as to partially enter under the transfer gate electrode 22. That is, a part of the element isolation region 24 is extended such that the channel portion 23 of the transfer gate 21 substantially extends across the L-shaped end of the floating diffusion (FD) region 20 to the photodiode PD side. It is formed under the transfer gate electrode 22.

  Here, although the photodiode PD is not illustrated, in this example, an n-type semiconductor region (n + region) to be a charge storage region is formed in the p-type semiconductor well region, and accumulation is performed on the surface side of the n-type semiconductor region. It is configured as a buried type photodiode in which a p-type semiconductor region (p + region) to be a layer is formed. The floating diffusion (FD) region 20 corresponds to the drain region of the transfer transistor Tr1, and is formed of an n-type semiconductor region (n + region) in this example. Furthermore, the element isolation region 24 is formed of a p-type semiconductor region (p + region) in this example.

  Furthermore, in the present embodiment, a part of the region of the substantially L-shaped floating diffusion (FD) region 20, that is, a part corresponding to the top (the tip of the protrusion) of the transfer gate electrode 22 has a small area. The region 26 has a high impurity concentration (so-called high concentration region: n + region in this example). In addition, the other part in the region of the substantially L-shaped floating diffusion (FD) region 20, that is, the other region corresponding to the region between the high concentration region 26 and the element isolation region 24 and surrounding the high concentration region 26. The portion is formed in a region 27 in which the impurity concentration is lower than that of the high concentration region 26 (so-called low concentration region: n − region in this example).

  The impurity concentration of the low concentration region 27 is lower than the low concentration region of the normal LDD structure, and the region 27 is lower than the low impurity concentration region in the vicinity of the junction formed naturally by the formation of the normal PN junction. Also has a large area.

On the other hand, the high concentration region 26 in the floating diffusion (FD) region 20 is shared with the contact region when connecting to the pixel transistor. In this example, the impurity concentration of the high concentration region 26 can be set to 1 × 10 ²⁰ cm ⁻³ or more. Further, the impurity concentration of the low concentration region 27 can be less than 1 × 10 ¹⁸ cm ⁻³ .

  According to the configuration of the first embodiment, the transfer gate electrode 22 is formed in a substantially trapezoidal shape so that the floating diffusion (FD) region 20 side has a convex shape, so that the corner portion of the photodiode PD is slightly reduced. The area of the photodiode PD can be widely secured. As a result, even if the pixel is miniaturized, the transfer gate electrode does not inhibit light incidence at the time of focusing, and a sufficient saturation charge amount can be secured.

  Further, as shown in FIG. 2, the channel width of the transfer gate 21 is expanded from the photodiode PD side to the floating diffusion (FD) region 20 side, which achieves both the cut-off characteristics and the charge transfer characteristics of the transfer transistor. So-called transistor characteristics can be maintained. That is, the channel width B on the floating diffusion (FD) region 20 side is wider than the channel width A on the photodiode PD side. This change in channel width leads to a change in potential of the channel portion 23. When the transfer transistor is turned on, an electric field is generated in which the potential becomes deeper from the photodiode PD side to the floating diffusion (FD) region 20 side due to shape effect. . In the narrow channel width A, the potential is shallow, and in the wide channel width B, the potential is deep. Therefore, the signal charge can be favorably transferred from the photodiode PD to the floating diffusion (FD) region 20, and the transfer capability of the signal charge can be improved even if the pixel is miniaturized. When the transfer transistor is off, leakage current is less likely to occur.

  The reason why the leak current is hard to occur will be described. When the channel width W is constant, the amount of change in the channel potential is the same on the photodiode PD side and the floating diffusion FD side. Therefore, when the transfer direction electric field is applied to the channel when the transfer gate is on, the potential is off. Sometimes there is a difference in potential. On the other hand, in the present embodiment, since the potential change on the photodiode FD side is large, assuming that the channel potential difference between the photodiode PD side and the floating diffusion FD side at the on state is the same, the potential difference at the off state is the same. It can be made smaller. That is, since the closing of the channel at the off time on the photodiode FD side is strengthened, the leakage current can be reduced.

  The area of the high concentration region can be minimized by sharing the high concentration region 26 of the floating diffusion (FD) region with the contact portion, that is, sharing. In the present embodiment, the high concentration region 26 is not necessary except at the position where the contact portion is to be placed. In a normal CMOS process, the high concentration region is formed by impurity implantation using a resist mask, and thus is sufficiently larger than the contact area of the contact portion. In general, only a part of the diffusion region in contact with the gate is not configured to have a high concentration.

  On the other hand, when the floating diffusion (FD) region 20 is L-shaped, the area of the floating diffusion (FD) region 20 is increased. Generally, the increase in area causes the diffusion capacitance (so-called junction capacitance) in the floating diffusion (FD) region 20 to increase, leading to a decrease in conversion efficiency. However, in the present embodiment, in the L-shaped floating diffusion (FD) region 20, the contact portion is shared with the region where a portion of the charge is substantially stored corresponding to the convex portion of the transfer gate 21. The impurity concentration distribution is set such that the n-type high concentration region 26 is formed, and the other regions become the n-type low concentration region 27. The junction capacitance in the low concentration region 27 is very small. Therefore, the overall junction capacitance in the floating diffusion (FD) region 20 is not extremely increased, and the reduction in conversion efficiency is mitigated.

  The signal charge transferred from the photodiode PD to the low concentration region 27 where the potential of the floating diffusion (FD) region 20 is shallow is collected to the deep high concentration region 26 of the potential.

  FIG. 3 shows a second embodiment of a region including the photodiode PD constituting the pixel of the present invention, the floating diffusion (FD) region 20, and the transfer transistor Tr1 and particularly its transfer gate. In the present embodiment, a transfer gate 21 is formed between the photodiode PD and the floating diffusion (FD) region 20 such that the channel width is wider on the floating diffusion (FD) region 20 side than on the photodiode PD side. A transistor Tr1 is formed.

  The photodiode PD has a square shape such as a square or a rectangle. The floating diffusion (FD) region 20 has a rectangular shape in which the length of the side opposite to the photodiode PD is equal to the length of the opposite side of the photodiode PD. The transfer gate 21 has a rectangular transfer gate electrode 22 and a trapezoidal channel portion 23. The channel portion 23 has a channel width A on the photodiode PD side narrower than a channel width B on the floating diffusion (FD) region 20 side, and the channel of the transfer gate 21 from the photodiode PD toward the floating diffusion (FD) region 20 It is formed in trapezoid shape so that the width of the part 23 may become wide gradually.

  On the other hand, the floating diffusion (FD) region 20 forms a high concentration region (in this embodiment, n + region) 26 in the center of the rectangle as in the above example, and a low concentration region (in this embodiment, n−) in the remaining region. Region 27 is formed. The configuration of the other impurity concentration and the like is the same as that described in the first embodiment, and thus the description thereof will not be repeated.

  According to the configuration of the second embodiment, since the photodiode PD is formed in a square shape, a wide area can be secured, and a sufficient amount of saturation charge can be secured even if the pixel is miniaturized. In addition, an electric field is generated such that the potential of the channel portion 23 of the transfer gate 21 becomes gradually deeper from the photodiode PD side to the floating diffusion (FD) region 20 side. Therefore, the signal charge can be favorably transferred from the photodiode PD to the floating diffusion (FD) region 20, and the transfer capability of the signal charge can be improved even if the pixel is miniaturized.

  On the other hand, in the floating diffusion (FD) region 20, since the high concentration region 26 and the low concentration region 27 are formed, the entire junction capacitance in the floating diffusion (FD) region 20 can be suppressed low. Efficiency can be reduced.

  Also in the second embodiment, the signal charges transferred to the low concentration region 27 of the floating diffusion (FD) region 20 are collected to the high concentration region 26. The other effects are similar to those described in the first embodiment.

  The configuration of the first embodiment shown in FIG. 2 is effective when applied to a CMOS image sensor in which pixel transistors are shared with a plurality of photodiodes. Next, the embodiment will be described.

  FIG. 4 shows a schematic configuration of another embodiment applied to a solid-state imaging device according to the present invention, a so-called CMOS image sensor. The solid-state imaging device according to the present embodiment has a set of pixel configurations in which pixel transistors other than the transfer transistor are shared for plural, four pixels in this example, that is, four photodiodes that are photoelectric conversion elements ( Hereinafter, it is a case where the shared pixels are arranged.

  The solid-state imaging device 31 according to the present embodiment includes an imaging unit (so-called pixel unit) 3 in which a plurality of shared pixels 32 are two-dimensionally arrayed with regularity, and peripheral circuits disposed around the imaging unit 3, that is, vertical The drive unit 4, the horizontal transfer unit 5, and the output unit 6 are configured. The shared pixel 32 includes a plurality of photodiodes PD, which are four photoelectric conversion elements in this example, four transfer transistors, one reset transistor, one amplification transistor, and one selection transistor.

  In the circuit configuration of the shared pixel 32, as shown in FIG. 4, the four photodiodes PD [PD1, PD2, PD3, PD4] are connected to the sources of the corresponding four transfer transistors Tr11, Tr12, Tr13, Tr14, respectively. The drains of the transfer transistors Tr11 to Tr14 are connected to the source of one reset transistor Tr2. A common floating diffusion (FD) region serving as charge-voltage conversion means between the transfer transistors Tr11 to Tr14 and the reset transistor Tr2 is connected to the gate of one amplification transistor Tr3. The source of the amplification transistor Tr3 is connected to the drain of one selection transistor Tr4. The drain of the reset transistor Tr2 and the drain of the amplification transistor Tr3 are connected to the power supply voltage supply unit. Further, the source of the selection transistor Tr4 is connected to the vertical signal line 8.

  The row transfer signals φTRG1 to φTRG4 are applied to the gates of the transfer transistors Tr11 to Tr14, the row reset signal φRST is applied to the gate of the reset transistor Tr2, and the row selection signal φSEL is applied to the gate of the selection transistor Tr4. Be done.

  The configurations of the vertical drive unit 4, the horizontal transfer unit 5, the output unit 6 and the like are the same as those described with reference to FIG.

  The configuration on the plane of the shared pixel 32 of the present embodiment, that is, the third embodiment is shown in FIG. One set of sharing pixels 32 in the present embodiment uses the pixel configuration shown in FIG. 2 and shares two horizontal and vertical pixels. In the present embodiment, as shown in FIG. 5, a common floating diffusion (FD) region 20 is disposed at the central portion so as to share the floating diffusion (FD) region 20. In order to sandwich the floating diffusion (FD) region 20 at the center, four pixels (the pixel configuration in FIG. 2) are horizontally and vertically point-symmetrically centered on the corner on the transfer gate 21 [211 to 214] side. Be placed. At this time, the central floating diffusion (FD) region 20 has a cross-like shape on a plane, and the high concentration region 26 is formed at the center thereof, and the other arms are formed as the low concentration region 27. Further, with respect to contact with the floating diffusion (FD) region 20, the element isolation region 24 separating the respective photodiodes PD1 to PD4 contacts only the tip of the low concentration region 27 of each arm. The other configuration is the same as that shown in FIG.

  According to the shared pixel configuration according to the third embodiment, four pixels are arranged point-symmetrically around the floating diffusion (FD) region 20, in other words, around the corner of the transfer gate. The pixel array can be densely arranged in the imaging unit 3 in which a large number of pixels are arranged. Then, in the present embodiment, the channel width of the transfer gate changes from the photodiode PD side to the floating diffusion (FD) region 20 side by the shape effect of the transfer gate as described above, and the channel potential changes. The transfer efficiency of the signal charge is improved.

Further, the floating diffusion (FD) region 20 to be shared is in the shape of a cross, and the central portion thereof is the high concentration region 26 and the other regions are the low concentration region 27, so the floating diffusion (FD) region 20 is The junction capacitance of the device can be very small, the conversion efficiency in charge-voltage conversion can be increased, or the decrease in conversion efficiency can be reduced. In particular, since the contact portion between the n-type floating diffusion (FD) region 20 and the p-type element isolation region 24 is only the arm end which is the cross-shaped low concentration region 27, the floating diffusion (FD) The junction capacitance between the region 20 and the element isolation region 24 is further reduced, and the conversion efficiency can be improved accordingly.
The other effects are the same as those described in the configuration of the first embodiment.

  FIG. 6 shows an embodiment of the layout of the imaging unit 3 using the shared pixel 32 of FIG. The present embodiment is a layout in which the shared pixels 32 are arranged in a square arrangement. That is, in the present embodiment, the reset transistor Tr2, the amplification transistor Tr3, and the selection transistor Tr4 are disposed on one side in the vertical direction in each sharing pixel 32, that is, on the lower side in each sharing pixel 32 in this example. The shared pixels 32 are arranged in the vertical and horizontal orthogonal coordinate systems. The reset transistor Tr2 is configured to have a source region 41, a drain region 42, and a reset gate electrode 43. The amplification transistor Tr3 is configured to have a source region 44, a drain region 45, and an amplification gate electrode 46. The selection transistor Tr4 is configured to have a source region 47, a drain region 44, and a selection gate electrode 48. At this time, the source region 44 of the amplification transistor Tr3 and the drain region 44 of the selection transistor Tr4 are formed in common.

  The high concentration region 26 of the floating diffusion (FD) region 20 is connected to the source region 41 of the reset transistor Tr2 and the amplification gate electrode 46 of the amplification transistor Tr3 through the wiring 49. Further, the source region 47 of the selection transistor Tr4 and the vertical signal line 8 are connected through the wiring 50.

  According to the layout of the imaging unit of FIG. 6, a large number of shared pixels 32 can be densely arranged in the horizontal and vertical directions, and a high-resolution solid-state imaging device can be provided.

  FIG. 7 shows another embodiment of the layout of the imaging unit 3 using the shared pixel 32 of FIG. The present embodiment is a layout in which the shared pixels 32 are arranged obliquely (also referred to as a honeycomb arrangement). That is, in the present embodiment, as described with reference to FIG. 5, the reset transistor Tr2, the amplification transistor Tr3, and the selection transistor Tr4 are provided on one side in the vertical direction in each sharing pixel 32, in this example, below the sharing pixel 32. Is placed. The shared pixels 32 are arranged in a coordinate system orthogonal to an axis obliquely inclined from the vertical direction and the horizontal direction. In the example of FIG. 7, the shared pixels 32 are arranged in a coordinate system orthogonal to the vertical direction and an axis inclined 45 ° from the horizontal direction. The other configuration is the same as that described with reference to FIG. 6, and therefore, the parts corresponding to those in FIG.

  According to the layout of the imaging unit of FIG. 7, a large number of shared pixels 32 can be densely arranged, and a solid-state imaging device with higher resolution than that of FIG. 6 can be provided.

  FIG. 8 is a schematic configuration of a camera using the above-described CMOS type solid-state imaging device. The camera 40 according to the present embodiment includes an optical system (optical lens) 41, a CMOS solid-state imaging device 42, and a signal processing circuit 43. The solid-state imaging device 42 is a solid-state imaging device having the pixel configuration of any one of the first to third embodiments described above, preferably the first and third embodiments, and a solid having the layout shown in FIG. 6 and FIG. It applies to an imaging device etc. The camera of the present embodiment includes the form of a camera module in which the optical system 41, the solid-state imaging device 42 of CMOS type, and the signal processing circuit 43 are modularized. The optical system 41 focuses image light (incident light) from a subject on an imaging surface of a CMOS solid-state imaging device 42. As a result, in the photoelectric conversion element (light receiving unit) of the CMOS solid-state imaging device 42, incident light is converted into signal charge according to the amount of incident light, and signal charge is accumulated in the photoelectric conversion element for a fixed period. The signal processing circuit 43 performs various signal processing on the output signal of the CMOS type solid-state imaging device 42 and outputs it as a video signal.

  According to the camera of the present embodiment, even if the pixel is miniaturized, the saturated charge amount and the conversion efficiency are ensured, and the signal charge transfer to the floating diffusion of the signal charge is improved, and a high resolution camera is provided. be able to.

  In the present invention, it is also possible to configure an electronic device provided with the above-described camera of FIG. 8 or a camera module.

  1, 31 solid-state imaging device, 2 pixels, 3 imaging units, 4 vertical driving units, 5 horizontal transfer units, 6 outputs, PD, PD1 to PD4 conversion elements, FD floating diffusion regions, 21, 21 to 214 transfer gates , 22 transfer gate electrode, 23 channel portion, 24 element isolation region, 26 high concentration region, 27 low concentration region, 32 shared pixel

Claims (16)

A plurality of pixels including a photoelectric conversion element and a pixel transistor are arrayed,
As the photoelectric conversion element, a first photoelectric conversion element, a second photoelectric conversion element, a third photoelectric conversion element, and a fourth photoelectric conversion element,
First transfer gate, second transfer gate corresponding to each of the first photoelectric conversion device, the second photoelectric conversion device, the third photoelectric conversion device, and the fourth photoelectric conversion device , A third transfer gate, and a fourth transfer gate,
The pixel transistor includes a first transfer transistor, a second transfer transistor, a third transfer transistor, a fourth transfer transistor, a reset transistor, an amplification transistor, and a selection transistor.
At least a part of the floating diffusion region is disposed at a position surrounded by the first photoelectric conversion device, the second photoelectric conversion device, the third photoelectric conversion device, and the fourth photoelectric conversion device. ,
The first transfer transistor, the second transfer transistor, the third transfer transistor, and the fourth transfer transistor include the floating diffusion region, the reset transistor, the amplification transistor, and the selection transistor. And connected to
The first photoelectric conversion element and the second photoelectric conversion element are disposed in a first row of the pixels;
The third photoelectric conversion element and the fourth photoelectric conversion element are disposed in a second row of the pixels;
The reset transistor, the amplification transistor, and the selection transistor are disposed in a third row of the pixels;
The second row is disposed between the first row and the third row,
The first transfer gate, the second transfer gate, the third transfer gate, and the fourth transfer gate have a first side, a second side, a third side, and a third side, respectively. Have four sides,
The first side of the first transfer gate, the first side of the second transfer gate, the first side of the third transfer gate, and the first side of the fourth transfer gate , Respectively facing the floating diffusion region,
The second side of the first transfer gate, the second side of the second transfer gate, the second side of the third transfer gate, and the second side of the fourth transfer gate Formed facing the first photoelectric conversion element, the second photoelectric conversion element, the third photoelectric conversion element, and the fourth photoelectric conversion element, respectively;
In the first transfer gate, the second transfer gate, the third transfer gate, and the fourth transfer gate, the first side is the second side, and the third side is the third side And a solid-state imaging device which is formed shorter than the fourth side, and the second side is formed longer than the first side, the third side, and the fourth side. The third side of the first transfer gate, the third side of the second transfer gate, the third side of the third transfer gate, and the third side of the fourth transfer gate , Each formed in a direction parallel to the first row,
The fourth side of the first transfer gate, the fourth side of the second transfer gate, the fourth side of the third transfer gate, and the fourth side of the fourth transfer gate The solid-state imaging device according to claim 1, formed in a direction perpendicular to the first row. In the first transfer gate, the second transfer gate, the third transfer gate, and the fourth transfer gate, the third side is formed to have the same length as the fourth side. The solid-state imaging device according to claim 2. The reset transistor, the amplification transistor, and the selection transistor are disposed in the order of the reset transistor, the amplification transistor, and the selection transistor in the direction from the first photoelectric conversion element to the second photoelectric conversion element. The solid-state imaging device according to any one of 1 to 3. The solid-state imaging according to any one of claims 1 to 4, wherein each of the first transfer gate, the second transfer gate, the third transfer gate, and the fourth transfer gate has a substantially trapezoidal shape. apparatus. The solid-state imaging device according to any one of claims 1 to 5, wherein a high concentration region is formed in a part of the floating diffusion region. The solid-state imaging device according to claim 6, wherein in the floating diffusion region, a low concentration region lower than the impurity concentration of the high concentration region is formed so as to surround the high concentration region. The solid-state imaging device according to claim 6, wherein the high concentration region of the floating diffusion region is formed to share a contact region connected to the pixel transistor. The solid-state imaging device according to any one of claims 1 to 8, further comprising a vertical signal line connected to the selection transistor. The solid-state imaging device according to claim 9, wherein the vertical signal line is connected to an amplifier or an analog / digital converter of a horizontal transfer unit. A device isolation region is formed to separate the first photoelectric conversion device, the second photoelectric conversion device, the third photoelectric conversion device, and the fourth photoelectric conversion device, respectively. The solid-state imaging device according to any one of the above. The solid-state imaging device according to claim 11, wherein the element isolation region is formed to surround the floating diffusion region. The first transfer gate, the second transfer gate, the third transfer gate, and the fourth transfer gate are provided at the first side, the third side, and the fourth side. The solid-state imaging device according to any one of claims 1 to 12, wherein a length in contact with the floating diffusion is larger than a length in contact with the photoelectric conversion element on the second side. A solid-state imaging device,
An optical system for guiding incident light to a photoelectric conversion element of the solid-state imaging device;
A signal processing circuit that processes an output signal of the solid-state imaging device;
Equipped with
The solid-state imaging device is
A plurality of pixels including a photoelectric conversion element and a pixel transistor are arrayed,
As the photoelectric conversion element, a first photoelectric conversion element, a second photoelectric conversion element, a third photoelectric conversion element, and a fourth photoelectric conversion element,
First transfer gate, second transfer gate corresponding to each of the first photoelectric conversion device, the second photoelectric conversion device, the third photoelectric conversion device, and the fourth photoelectric conversion device , A third transfer gate, and a fourth transfer gate,
The pixel transistor includes a first transfer transistor, a second transfer transistor, a third transfer transistor, a fourth transfer transistor, a reset transistor, an amplification transistor, and a selection transistor.
At least a part of the floating diffusion region is disposed at a position surrounded by the first photoelectric conversion device, the second photoelectric conversion device, the third photoelectric conversion device, and the fourth photoelectric conversion device. ,
The first transfer transistor, the second transfer transistor, the third transfer transistor, and the fourth transfer transistor include the floating diffusion region, the reset transistor, the amplification transistor, and the selection transistor. And connected to
The floating diffusion region is disposed at a position surrounded by the first photoelectric conversion device, the second photoelectric conversion device, the third photoelectric conversion device, and the fourth photoelectric conversion device.
The first photoelectric conversion element and the second photoelectric conversion element are disposed in a first row of the pixels;
The third photoelectric conversion element and the fourth photoelectric conversion element are disposed in a second row of the pixels;
The reset transistor, the amplification transistor, and the selection transistor are disposed in a third row of the pixels;
The second row is disposed between the first row and the third row,
The first transfer gate, the second transfer gate, the third transfer gate, and the fourth transfer gate have a first side, a second side, a third side, and a third side, respectively. Have four sides,
The first side of the first transfer gate, the first side of the second transfer gate, the first side of the third transfer gate, and the first side of the fourth transfer gate , Respectively facing the floating diffusion region,
The second side of the first transfer gate, the second side of the second transfer gate, the second side of the third transfer gate, and the second side of the fourth transfer gate Formed facing the first photoelectric conversion element, the second photoelectric conversion element, the third photoelectric conversion element, and the fourth photoelectric conversion element, respectively;
In the first transfer gate, the second transfer gate, the third transfer gate, and the fourth transfer gate, the first side is the second side, and the third side is the third side And an electronic device which is shorter than the fourth side, and the second side is longer than the first side, the third side, and the fourth side. A part of the third side of the first transfer gate, a part of the third side of the second transfer gate, a part of the third side of the third transfer gate, and the fourth Part of the third side of the transfer gate, part of the fourth side of the first transfer gate, part of the fourth side of the second transfer gate, and the third transfer gate A portion of a fourth side of the second transfer gate and a portion of a fourth side of the fourth transfer gate are formed to face the floating diffusion region, respectively.
The solid-state imaging device according to any one of claims 1 to 13. A part of the third side of the first transfer gate, a part of the third side of the second transfer gate, a part of the third side of the third transfer gate, and the fourth Part of the third side of the transfer gate, part of the fourth side of the first transfer gate, part of the fourth side of the second transfer gate, and the third transfer gate A portion of a fourth side of the second transfer gate and a portion of a fourth side of the fourth transfer gate are formed to face the floating diffusion region, respectively.
The electronic device according to claim 14.

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