JP2011054880A - Solid-state imaging device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device hardly causing trouble in reset operation of an FD part even when capacitance of the FD part is reduced. <P>SOLUTION: The solid-state imaging device includes: a light reception part for subjecting incident light to photoelectric conversion to signal charge; a floating diffusion part 120 for receiving the signal charge; a transfer part 140 for transferring the signal charge from the light reception part to the floating diffusion part 120; and a reset part 130 formed on the side opposite to the transfer part 140 interposing the floating diffusion part 120, to discharge the charge from the floating diffusion part 120. The floating diffusion part 120 includes: a first region 121; and a second region 122 formed in the first region 121, and higher in concentration of impurity than the first region 121. The distance between the second region 122 and the transfer part 140 is larger than that between the second region 122 and the reset part 130. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly to a solid-state imaging device having a floating diffusion portion and a manufacturing method thereof.

  In recent years, the demand for solid-state imaging devices has increased as imaging devices for digital still cameras and digital video cameras. Further, in many cases, a camera function is mounted on a mobile terminal device typified by a mobile phone, and the demand for a solid-state imaging device is expanding as an imaging device for the mobile terminal device.

  Digital still cameras, digital video cameras, portable terminal devices, and the like are required to have high image quality, and the number of pixels of solid-state imaging devices tends to increase year by year. On the other hand, downsizing is also required, and the pixel size is miniaturized in order to achieve both downsizing and higher pixels. However, when the pixel is miniaturized, the light receiving area of the pixel is also reduced, so that the signal charge is reduced. When the amount of change in the signal charge in the floating diffusion (FD) portion where the capacitance is C is ΔQ, the voltage change ΔV is ΔV = ΔQ / C. Therefore, the sensitivity (charge detection sensitivity) of the signal voltage output from the source follower circuit connected to the FD unit depends on the capacitance C of the FD unit. Therefore, it is preferable to make the capacity of the FD portion as small as possible in order to compensate for the decrease in signal charge. The simplest method for reducing the capacity of the FD portion is to reduce the area of the FD portion. However, since the pixel size is further miniaturized, the parasitic capacitance between the wiring and the gate cannot be ignored, and the effective capacitance cannot be reduced even if the area of the FD portion is further reduced. For this reason, a method for reducing the capacity of the FD portion by reducing the impurity concentration has been studied (see, for example, Patent Document 1).

JP 2003-197893 A

  However, it has been found that when the impurity concentration of the FD part is reduced to reduce the capacity of the FD part, a malfunction occurs in the reset operation for sweeping out charges from the FD part. When the impurity concentration of the FD portion is reduced, a completely depleted region is generated between the FD portion and the reset electrode. For this reason, even if the reset operation is performed, the charge cannot be completely discharged from the FD portion, and the potential of the FD portion becomes shallower than the potential of the reset drain. Furthermore, since the potential of the depletion region is not stabilized due to the influence of the electrostatic charge, the reference potential when there is no signal becomes unstable. For this reason, there arises a problem that noise increases and reset saturation variation occurs.

  An object of the present invention is to solve the above problems and to realize a solid-state imaging device that is less likely to cause problems in the reset operation of the FD section even when the capacity of the FD section is reduced.

  In order to achieve the above object, according to the present invention, the solid-state imaging device has a configuration in which the interval between the second region having a high impurity concentration and the reset unit is narrowed.

  Specifically, a solid-state imaging device according to the present invention includes a semiconductor substrate, a light receiving portion that is formed on the semiconductor substrate and photoelectrically converts incident light into signal charges, an FD portion that receives signal charges, and a light receiving portion to an FD portion. A transfer unit that transfers a signal charge; and a reset unit that is formed on the opposite side of the transfer unit across the FD unit and discharges the charge from the FD unit. The FD unit includes a first region and a first region And a second region having a higher impurity concentration than the first region, and a distance between the second region and the transfer unit is larger than a distance between the second region and the reset unit. .

  In the solid-state imaging device according to the present invention, the interval between the second region having a higher impurity concentration than the first region and the transfer unit is larger than the interval between the second region and the reset unit. Therefore, even when the impurity concentration of the first region is lowered in order to improve the charge detection sensitivity of the FD portion, a fully depleted region is unlikely to occur between the second region and the reset portion. Accordingly, it is possible to make it difficult to cause a problem that charges remain in the FD portion during the reset operation.

  In the solid-state imaging device of the present invention, the distance between the second region and the reset unit may be 0.15 μm or more and 0.3 μm or less.

  In the solid-state imaging device of the present invention, the transfer unit includes a transfer unit diffusion layer formed on the semiconductor substrate, and a transfer electrode formed by interposing an insulating film on the transfer unit diffusion layer, and the reset unit A reset drain formed on the semiconductor substrate, a reset portion diffusion layer formed between the reset drain and the FD portion, and a reset electrode formed with an insulating film interposed on the reset portion diffusion layer. The transfer part diffusion layer, the FD part, the reset part diffusion layer, and the reset drain are integrally formed, and the interval between the second region and the transfer electrode is larger than the interval between the second region and the reset electrode. Also good.

  In the solid-state imaging device according to the present invention, the first region may have a lower impurity concentration than the transfer portion diffusion layer and the reset portion diffusion layer. With this configuration, the charge detection sensitivity of the FD portion can be increased.

  In the solid-state imaging device of the present invention, the planar shape of the second region may be such that the width at the end on the reset electrode side is narrower than the width at the end on the transfer electrode side. With such a configuration, it is possible to reduce the distance between the second region and the reset electrode while keeping the area of the second region small.

  In the solid-state imaging device of the present invention, the second region may be configured such that the concentration of impurities is lower on the reset electrode side than on the transfer electrode side.

  In the solid-state imaging device of the present invention, the first region has a portion that is narrower than the region between the second region and the reset electrode in the region other than between the second region and the reset electrode. It is good also as a structure.

  In the solid-state imaging device of the present invention, the direction in which the transfer part diffusion layer extends and the direction in which the reset part diffusion layer extend may be configured to intersect each other.

  In the solid-state imaging device according to the present invention, the transfer unit is a transfer transistor connected between the light receiving unit and the FD unit, and the reset unit is a reset transistor connected between the FD unit and the power source. The distance between the gate electrode of the transistor and the second region may be larger than the distance between the gate electrode of the reset transistor and the second region.

  A method of manufacturing a solid-state imaging device according to the present invention includes a light receiving unit that injects impurities into a semiconductor substrate, photoelectrically converts incident light into signal charges, an FD unit that receives signal charges, and a reset that discharges signal charges in the FD unit. Forming a drain, and forming a first gate electrode for transferring signal charges to the FD portion and a second gate electrode for transferring signal charges to the reset drain via an insulating layer on the semiconductor substrate; And the step of forming the FD portion includes a step of forming a first region, and a step of forming a second region having an impurity concentration higher than that of the first region in the first region, The step of forming the second region includes a step of implanting impurities from a direction perpendicular to the semiconductor substrate and a step of implanting impurities from an oblique direction to the semiconductor substrate.

  In the method for manufacturing a solid-state imaging device of the present invention, the step of forming the second region includes a step of implanting impurities from a direction perpendicular to the semiconductor substrate, and a step of implanting impurities from a direction oblique to the semiconductor substrate. including. Therefore, the high concentration region and the intermediate concentration region can be formed using one implantation mask. Therefore, the process can be simplified.

  According to the solid-state imaging device and the method for manufacturing the same according to the present invention, it is possible to realize a solid-state imaging device that is less likely to cause a malfunction in the reset operation of the FD unit even if the capacity of the FD unit is reduced.

(A) And (b) shows the solid-state imaging device which concerns on 1st Embodiment, (a) is a top view, (b) is sectional drawing in the Ib-Ib line | wire of (a). (A) and (b) are potential diagrams in the case of d1> d2 and d1 = d2, respectively. It is a figure which shows the correlation with d2, a charge detection sensitivity, and reset saturation. It is a top view which shows the solid-state imaging device which concerns on the 1st modification of 1st Embodiment. It is a top view which shows the solid-state imaging device which concerns on the 1st modification of 1st Embodiment. It is a top view which shows the solid-state imaging device which concerns on the 2nd modification of 1st Embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the solid-state imaging device which concerns on the 2nd modification of 1st Embodiment. It is a top view which shows the solid-state imaging device which concerns on the 3rd modification of 1st Embodiment. It is a top view which shows the solid-state imaging device which concerns on the 4th modification of 1st Embodiment. It is a top view which shows the solid-state imaging device which concerns on 2nd Embodiment.

  A first embodiment will be described with reference to the drawings. FIGS. 1A and 1B show a schematic configuration around the charge detection unit of the solid-state imaging device according to the present embodiment. (A) shows a planar configuration, and (b) shows a cross-sectional configuration taken along line Ib-Ib in (a). In FIG. 1A, the description of the insulating film 161 is omitted.

  The solid-state imaging device of the present embodiment is an interline transfer type charge coupled device (CCD) type imaging device. The solid-state imaging device has a plurality of light receiving units that are two-dimensionally arranged in a matrix on a substrate. The light receiving unit converts incident light into signal charges corresponding to the amount of light and accumulates the signal charges. A vertical CCD extending in the column direction is formed between the light receiving portions. The vertical CCD vertically transfers signal charges read from each photoelectric conversion element. The vertical CCD is connected to the horizontal CCD. The horizontal CCD horizontally transfers signal charges for one line (row) transferred from the vertical CCD. The horizontal CCD is connected to the charge detection unit. The charge detection unit converts the signal charge transferred by the horizontal CCD into an electric signal and outputs it.

  As shown in FIG. 1, the charge detection unit includes a floating diffusion (FD) unit 120, a transfer unit 140 that transfers charges to the FD unit 120, and a reset unit 130 that sweeps out charges from the FD unit. The transfer unit 140 includes a transfer unit diffusion layer 142 and a transfer electrode 141 formed on the transfer unit diffusion layer 142 with an insulating film 161 interposed therebetween. The horizontal CCD 150 has a horizontal transfer channel 152 and a horizontal transfer electrode 151 formed on the horizontal transfer channel with an insulating film 161 interposed therebetween. In FIG. 1, only the horizontal transfer electrode 151 at the final stage is shown. The FD unit 120 includes a first region 121 and a second region 122 that is surrounded by the first region 121 and has a higher impurity concentration than the first region 121. A contact 125 is formed in the second region 122. The contact 125 is connected to a source follower circuit (not shown) via a wiring (not shown). The reset unit 130 includes a reset unit diffusion layer 132, a reset electrode 131 formed on the reset unit diffusion layer 132 with an insulating film 161 interposed therebetween, a reset drain 133 having a higher impurity concentration than the reset unit diffusion layer 132, have. The reset drain 133 is connected to a power source (not shown) via a wiring (not shown).

The horizontal transfer channel 152, the transfer part diffusion layer 142, the FD part 120, the reset part diffusion layer 132, and the reset drain 133 are n-type impurity diffusion layers that are successively formed in the p-well 102 of the semiconductor substrate 101. The impurity concentrations of the horizontal transfer channel 152, the transfer portion diffusion layer 142, and the reset portion diffusion layer 132 are not particularly limited, but may be the same. The impurity concentration of the first region 121 is preferably as low as possible in order to reduce the capacitance of the FD portion 120. The impurity concentration of the first region 121 is preferably lower than that of the reset part diffusion layer 132 and the transfer part diffusion layer 142. Since the contact 125 for extracting a signal from the FD portion 120 is formed in the second region 122, the impurity concentration is set higher than that of the first region 121. For example, the impurity concentration of the reset part diffusion layer 132 and the transfer part diffusion layer 142 is set to about 10 ¹⁸ cm ⁻³ , the impurity concentration of the first region 121 is set to about 10 ¹⁷ cm ^−3, and the impurity concentration of the second region 122 is set. ^Is about 10 ²⁰ cm ⁻³ . The impurity concentration of the reset drain 133 is set higher than that of the reset part diffusion layer 132.

  An interval d2 between the second region 122 and the reset electrode 131 is formed to be smaller than an interval d1 between the second region 122 and the transfer electrode 141. In addition, the contact 125 is formed at substantially the center between the transfer electrode 141 and the reset electrode 131. This is for facilitating the drawing of the wiring from the contact 125. Further, the interlayer capacitance between the transfer electrode 141 and the reset electrode 131 and the wiring affects the charge detection sensitivity in the same manner as the capacitance of the FD portion 120 itself. Therefore, the interlayer capacitance is made as small as possible. When the contact 125 is formed approximately at the center between the transfer electrode 141 and the reset electrode 131, the second region 122 has a planar rectangular shape, and the distance d3 between the contact 125 and the end portion of the second region 122 on the transfer electrode 141 side. The distance d4 between the contact 125 and the end of the second region 122 on the reset electrode 131 side is larger. The size of the interval d3 is determined by the alignment accuracy for forming the contact 125.

  Hereinafter, the impurity concentration of the first region 121 is lowered by setting the distance d2 between the second region 122 and the reset electrode 131 to be smaller than the distance d1 between the second region 122 and the transfer electrode 141. In addition, the principle that can solve the problem of the reset operation will be described.

  2A and 2B show potentials of the horizontal CCD, transfer unit, FD unit, and reset unit. FIG. 2A shows a case where d1 is smaller than d2. FIG. 2B shows a case where d1 and d2 are equal. Shows the case.

  At timing t1, signal charges are accumulated under the horizontal transfer electrode 151 in the final stage of the horizontal CCD 150. Next, when the horizontal transfer electrode 151 at the final stage is changed from the high level to the low level at the timing t <b> 2, the signal charge passes below the transfer electrode 141 and is transferred to the FD unit 120. Thereby, the potential of the FD portion 120 becomes shallow corresponding to the signal charge. Next, by applying a high-level pulse to the reset electrode 131 at a timing t3, the lower potential of the reset electrode 131 is set to be equal to or higher than the potential of the power supply voltage applied to the reset drain 133. Thereby, the signal charge of the FD unit 120 should be absorbed by the power supply of the reset drain 133 and fixed to the potential of the power supply. However, when the impurity concentration of the FD unit 120 is lowered in order to reduce the capacitance of the FD unit 120, the depletion is completely performed on the reset electrode 131 side in the FD unit 120 as shown in FIG. Will be generated. For this reason, the potential of the FD unit 120 cannot be completely swept out, and the potential of the FD unit 120 at the timing t4 becomes shallower than the potential of the reset drain 133. For this reason, reset saturation, which is the difference between the low-level potential of the reset electrode 131 and the potential of the FD unit 120 after reset, is reduced.

  On the other hand, in the solid-state imaging device of the present embodiment, the interval d2 between the second region 122 and the reset electrode 131 is narrow. For this reason, when the potential of the reset unit 130 is fixed to the potential of the reset drain 133, the potential affects the second region 122 beyond the low-concentration first region 121. Therefore, a depletion region does not occur as shown in FIG. 2A, and the FD portion 120 can be stably reset to the potential of the reset drain 133.

If the distance d2 between the second region 122 and the reset electrode 131 is made as small as possible, a depleted region is less likely to occur. However, as described above, since the position where the contact 125 is formed is limited, if d2 is reduced, the distance d4 between the contact 125 and the end of the second region 122 on the reset electrode 131 side is increased. For this reason, the second region 122 having a high impurity concentration becomes large, the capacity of the FD portion 120 increases, and the charge detection sensitivity decreases. FIG. 3 shows the correlation between the distance d2 between the second region 122 and the reset electrode 131, the charge detection sensitivity, and the reset saturation. In FIG. 3, the impurity concentration of the first region 121 is 1 × 10 ¹⁷ cm ^−3, and the impurity concentration of the second region 122 is 1 × 10 ²⁰ cm ⁻³ .

As shown in FIG. 3, the charge detection sensitivity increases as the second region 122 becomes smaller and the distance d2 between the second region 122 and the reset electrode 131 becomes larger. However, the reset saturation is greatly reduced when the distance d2 between the second region 122 and the reset electrode 131 exceeds 0.3 μm. On the other hand, when the impurity concentration of the first region is about 1 × 10 ¹⁸ cm ⁻³ and the distance d2 between the second region 122 and the reset electrode is about 0.4 μm, a decrease in reset saturation is observed. However, the charge detection sensitivity is greatly reduced. For this reason, in order to achieve both the improvement in charge detection sensitivity in the FD unit 120 by reducing the impurity concentration in the first region 121 and the suppression of the decrease in reset saturation, the second region 122 and the reset electrode 131 are used. The distance d <b> 2 may be about 0.15 μm to 0.3 μm.

  When the distance d1 between the second region 122 and the transfer electrode 141 is reduced, the size of the second region 122 is increased. In addition, the interlayer capacitance between the wiring connecting the FD unit 120 and the source follower circuit and the transfer electrode 141 increases. For this reason, it is preferable to make d1 larger than d2. However, if d1 is increased too much, the wiring and the reset electrode 131 approach each other and the interlayer capacitance increases. Therefore, d1 needs to be determined in consideration of the distance between the transfer electrode 141 and the reset electrode 131, the size of the contact 125, and the like. Further, when the distance d3 between the contact 125 and the end of the second region 122 on the transfer electrode 141 side is increased, the second region 122 is increased. Therefore, d3 is preferably as small as possible within the range of machining accuracy. From the viewpoint of reducing the interlayer capacitance of the wiring and facilitating the drawing of the wiring, it is preferable to make d1 + d3 and d2 + d4 substantially equal and to arrange the contact 125 at the center of the transfer electrode 141 and the reset electrode 131.

Specifically, when the impurity concentration of the first region 121 is about 1 × 10 ¹⁷ cm ⁻³ and the impurity concentration of the second region 122 is about 1 × 10 ²⁰ cm ⁻³ , the second region 122 is used. The distance d2 between the second electrode 122 and the reset electrode 131 may be about 0.25 μm, and the distance d1 between the second region 122 and the transfer electrode 141 may be about 0.4 μm. In this case, since the contact 125 is about 0.3 μm square, the distance d3 between the end of the second region 122 on the transfer electrode 141 side and the contact 125 is about 0.15 μm, and the reset electrode of the second region 122 The distance d4 between the end portion on the 131 side and the contact 125 may be about 0.3 μm. In this way, even with the current processing accuracy, the contact 125 can be aligned without any problem. However, the optimum value of d2 varies depending on the reset drain voltage and the like. When the voltage applied to the reset drain 133 is about 12V, d2 may be about 0.25 μm. However, when the reset drain voltage is further increased, depletion is likely to occur. Therefore, it is preferable to further reduce d2.

(First modification of the first embodiment)
FIG. 1 shows an example in which the width of the second region 122 is made constant and is formed into a planar rectangular shape. However, as shown in FIG. 4, the width of the end portion on the reset electrode 131 side in the second region 122 may be narrower than the width of the end portion on the transfer electrode 141 side. In this way, it is possible to suppress an increase in the area of the second region 122 while narrowing the distance d1 between the second region 122 and the reset electrode 131. Accordingly, it is possible to further improve the charge detection sensitivity while suppressing a decrease in reset saturation. Further, as shown in FIG. 5, the planar shape of the second region may be a shape in which a square part and a triangular part are combined.

(Second modification of the first embodiment)
The concentration of the second region 122 does not need to be constant. As shown in FIG. 6, the second region 122 is formed on the transfer electrode 141 side, and the intermediate region formed on the reset electrode 131 side. You may comprise by the density | concentration area | region 122B. The impurity concentration in the intermediate concentration region 122B may be higher than that in the first region 121 so that the generation of a depletion layer can be prevented. The high concentration region 122A and the intermediate concentration region 122B may be a region having an impurity concentration of about 10 ²⁰ cm ^{−3 and} a region of about 10 ¹⁸ cm ⁻³ , for example. In this way, it is possible to suppress an increase in the capacitance of the FD unit 120 while narrowing the distance d1 between the second region 122 and the reset electrode 131. Accordingly, it is possible to further improve the charge detection sensitivity while suppressing a decrease in reset saturation.

  The FD portion 120 may be formed by any method, for example, as follows. First, as shown in FIG. 7, ion implantation is performed perpendicularly to the semiconductor substrate using a resist mask 171 to form a high concentration region 122A. Thereafter, using the resist mask 171, the intermediate concentration region 122 </ b> B is formed by performing ion implantation on the semiconductor substrate from an oblique direction. In this way, since the mask for ion implantation can be shared, the FD portion 120 having the intermediate concentration region 122B can be formed only by adding an ion implantation step. Note that the impurity implantation amount in the case of performing ion implantation from an oblique direction is set lower than that in the case of performing ion implantation vertically.

(Third Modification of First Embodiment)
In order to reduce the capacitance of the FD unit 120, the area of the first region 121 may be reduced. A portion between the second region 122 and the reset electrode 131 in the first region 121 is not preferable to be narrowed because it is involved in the reset operation. However, even if the width of the portion on the transfer electrode 141 side in the first region 121 is reduced, the reset operation and the charge transfer operation are not significantly affected. For this reason, as shown in FIG. 8, the width w1 of the portion on the transfer electrode 141 side in the first region 121 is made narrower than the width w2 of the portion on the reset electrode 131 side, thereby reducing the capacitance of the FD portion 120. Further, the transfer efficiency can be improved by reducing the size. In addition, the size of the second region 122 can be increased or the impurity concentration of the second region 122 can be increased without changing the capacitance of the FD portion 120.

  In FIG. 8, the width of all the portions of the first region 121 other than the portion between the second region 122 and the reset electrode 131 is narrowed, but only a portion of the width may be narrowed.

  In addition, you may combine this modification, a 1st modification, or a 2nd modification.

(Fourth modification of the first embodiment)
As shown in FIG. 9, the direction in which the transfer part diffusion layer 142 extends may be different from the direction in which the reset part diffusion layer 132 extends, and the transfer electrode 141 and the reset electrode 131 may be arranged obliquely. In this case, even if the direction is changed in the middle of the FD unit 120 as shown in FIG. 9A, the boundary between the transfer unit 140 and the FD unit 120 and the FD unit 120 and the reset unit as shown in FIG. 9B. The direction may be changed at least at one of the boundaries with 130. With such a layout, it is easy to pull out the wiring from the FD unit 120, and thus the wiring 127 that connects the FD unit 120 and the source follower circuit can be shortened. The capacitance contributing to the charge detection sensitivity includes not only the capacitance of the FD unit 120 itself but also the interlayer capacitance of the wiring connecting the FD unit 120 and the source follower circuit. With the layout as in this modified example, the distance between the reset electrode 131 and the transfer electrode 141 and the wiring 127 can be increased, so that an effect of reducing the interlayer capacitance of the wiring 127 can be obtained. As a result, the capacitance that contributes to transfer efficiency can be further reduced.

  In the present modification, as in the first modification, the second region 122 is configured such that the width of the end on the reset electrode 131 side is narrower than the width of the end on the transfer electrode 141 side. However, as shown in the second modification, the second region 122 may be composed of a high concentration region and an intermediate concentration region. Further, as shown in the third modification, the first region 121 may have a narrower width on the transfer electrode 141 side.

(Second Embodiment)
Although the CCD type solid-state imaging device has been described in the first embodiment and its modification, it is also possible to apply these configurations to a MOS (metal oxide semiconductor) type solid-state imaging device. FIG. 10 shows a planar configuration of the solid-state imaging device according to the second embodiment. In FIG. 10, only one pixel cell is shown enlarged.

  The MOS type solid-state imaging device includes a light receiving unit 201 that includes a photodiode and generates a signal charge according to the amount of incident light, a pixel transistor that processes the signal charge generated in the light receiving unit 201 and outputs the signal charge to a signal line, have. The pixel transistor includes a transfer transistor 240, a reset transistor 230, an amplification transistor 250, and a selection transistor 260. The transfer transistor 203 is connected between the light receiving unit 201 and the FD unit 220 and transfers charges generated in the light receiving unit 201 to the FD unit 220. The reset transistor 230 is connected between the power supply line and the FD unit 220 and resets the electric charge of the FD unit 220. The amplification transistor 250 is connected to the FD unit 220, amplifies the electric charge of the FD unit 220, and converts it into a signal voltage. The selection transistor 260 outputs the signal voltage converted in the amplification transistor 250 to the signal line.

  As shown in FIG. 10, an n-type impurity is implanted into the substrate 200 to form a light receiving portion 201, an impurity diffusion layer of the pixel transistor, and an FD portion 220. The transfer transistor 240 is formed between the light receiving unit 201 and the FD unit 220. The reset transistor 230 is formed on the opposite side of the transfer transistor 240 with the FD portion 220 interposed therebetween. In FIG. 10, only the gate electrode is shown for the pixel transistor. The FD portion 220 includes a first region 221 and a second region 222 that is surrounded by the first region 221 and has a higher impurity concentration than the first region 221. The second region 222 and the gate electrode of the amplification transistor 250 are connected by a wiring. A distance d2 between the gate electrode of the reset transistor 230 and the second region 222 is smaller than a distance d1 between the gate electrode of the transfer transistor 240 and the second region 222. For this reason, even when the impurity concentration of the first region 221 is lowered, a fully depleted region is hardly generated between the gate electrode of the transfer transistor 240 and the second region 222, and the reset operation of the FD portion 220 is performed. It becomes possible to carry out stably.

  Also in the present embodiment, as in the first embodiment, the shapes of the first region and the second region are changed, or the second region is configured to include a plurality of portions having different impurity concentrations. Also good.

  The solid-state imaging device and the manufacturing method thereof according to the present invention can realize a solid-state imaging device that is less likely to cause a malfunction in the reset operation of the FD unit even when the capacity of the FD unit is reduced, and particularly has an FD unit with high charge detection sensitivity. It is useful as a solid-state imaging device and a manufacturing method thereof.

DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 102 P well 120 Floating diffusion part 121 1st area | region 122 2nd area | region 122A High concentration area | region 122B Intermediate concentration area | region 125 Contact 127 Wiring 130 Reset part 131 Reset electrode 132 Reset part diffusion layer 133 Reset drain 140 Transfer part 141 Transfer electrode 142 Transfer portion diffusion layer 150 Horizontal CCD
151 Horizontal transfer electrode 152 Horizontal transfer channel 161 Insulating film 171 Resist mask 200 Substrate 201 Light receiving part 220 Floating diffusion part 221 First area 222 Second area 230 Reset transistor 240 Transfer transistor 250 Amplifying transistor 260 Select transistor

Claims (10)

A semiconductor substrate;
A light receiving portion formed on the semiconductor substrate for photoelectrically converting incident light into a signal charge;
A floating diffusion portion for receiving the signal charge;
A transfer unit that transfers the signal charge from the light receiving unit to the floating diffusion unit;
A reset unit that is formed on the opposite side of the transfer unit across the floating diffusion unit, and discharges charges from the floating diffusion unit,
The floating diffusion portion includes a first region and a second region formed in the first region and having a higher impurity concentration than the first region,
The solid-state imaging device, wherein an interval between the second region and the transfer unit is larger than an interval between the second region and the reset unit.   2. The solid-state imaging device according to claim 1, wherein an interval between the second region and the reset unit is 0.15 μm or more and 0.3 μm or less. The transfer unit includes a transfer unit diffusion layer formed on the semiconductor substrate, and a transfer electrode formed on the transfer unit diffusion layer with an insulating film interposed therebetween,
The reset unit includes a reset drain formed on the semiconductor substrate, a reset unit diffusion layer formed between the reset drain and the floating diffusion unit, and an insulating film interposed on the reset unit diffusion layer. A reset electrode formed by
3. The solid-state imaging device according to claim 1, wherein an interval between the second region and the transfer electrode is larger than an interval between the second region and the reset electrode.   The solid-state imaging device according to claim 3, wherein the first region has a lower impurity concentration than the transfer unit diffusion layer and the reset unit diffusion layer.   5. The solid-state imaging device according to claim 3, wherein the planar shape of the second region is such that a width at an end portion on the reset electrode side is narrower than a width at an end portion on the transfer electrode side.   The solid-state imaging device according to claim 3, wherein the second region has a lower impurity concentration on the reset electrode side than on the transfer electrode side.   The first region has a portion narrower than a region between the second region and the reset electrode in a region except between the second region and the reset electrode. The solid-state imaging device according to any one of claims 3 to 6.   8. The solid-state imaging device according to claim 3, wherein a direction in which the transfer unit diffusion layer extends and a direction in which the reset unit diffusion layer extends intersect each other. The transfer unit is a transfer transistor connected between the light receiving unit and the floating diffusion unit,
The reset unit is a reset transistor connected between the floating diffusion unit and a power source;
3. The solid-state imaging according to claim 1, wherein an interval between the gate electrode of the transfer transistor and the second region is larger than an interval between the gate electrode of the reset transistor and the second region. apparatus. Injecting impurities into the semiconductor substrate, forming a photodiode that photoelectrically converts incident light into a signal charge, a floating diffusion part that receives the signal charge, and a reset drain that discharges the signal charge of the floating diffusion part;
Forming a first gate electrode for transferring the signal charge to the floating diffusion portion and a second gate electrode for transferring the signal charge to the reset drain via an insulating layer on the semiconductor substrate; ,
The step of forming the floating diffusion portion includes a step of forming a first region, and a step of forming a second region having an impurity concentration higher than that of the first region in the first region,
The step of forming the second region includes a step of implanting impurities from a direction perpendicular to the semiconductor substrate and a step of implanting impurities from a direction oblique to the semiconductor substrate. Device manufacturing method.

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