JP2008016612A - Solid-state image sensing element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image sensing element with a degradation of the S/N involved in the pixel miniaturization suppressed, and capable of improving an on/off characteristic of a selective transistor. <P>SOLUTION: In the solid-state image sensing element having the selective transistor 206 adjacent to an amplifying transistor 205, an interlayer insulating layer 7 is provided between a first well region 2a of the amplifying transistor 205 and a second well region 2b of the selective transistor 206, and an impurity concentration of the second well region 2b is higher than that of the first well region 2a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

With the recent popularization of digital cameras, camera-equipped mobile phones, and the like and the increase in storage capacity, the demand for small, high-definition solid-state imaging devices is increasing. In particular, a CMOS solid-state image sensor (manufactured by a CMOS process, which is a general semiconductor manufacturing process)
The demand for CMOS sensors is increasing. In recent years, such CMOS sensors have been increasingly demanded for further downsizing and increasing the number of pixels. In order to achieve these requirements, miniaturization of the pixel size has become an important issue.

Such miniaturization of the pixel size accelerates the reduction of the area occupied by the photodiode as the photoelectric conversion unit, and thus the S / N as the solid-state imaging device is inevitably deteriorated. In other words, the amount of incident light decreases with the miniaturization of pixels, and the amount of signal charge accumulated in the pixel portion decreases. This miniaturization of the pixel also reduces the channel area of the amplification transistor constituting the pixel.
As a result, there is a problem that 1 / f noise generated in the amplification transistor increases.
This 1 / f noise becomes a large noise with respect to the signal charge whose strength is reduced as the pixel is miniaturized, and is a major cause of deterioration of S / N as a solid-state imaging device.

In general, a solid-state imaging device has a CDS (removal noise) to remove fixed pattern noise caused by threshold variation of amplification transistors and reset noise in a following fusion that is a charge-voltage conversion (QV conversion) structure inside a pixel. Correlated Double
A Sampling (correlated double sampling) circuit is provided. As a result, CDS
Low frequency noise components below the circuit sampling frequency are removed.

However, as the above-described pixel miniaturization proceeds, the channel area of the amplification transistor is further reduced, and 1 / f noise existing on the higher frequency side than the sampling frequency (fs) of the CDS circuit cannot be ignored. (See FIG. 6).

As a technique for improving noise characteristics (1 / f noise) of a semiconductor integrated circuit device having an analog / digital hybrid circuit, a technique is disclosed in which a buried channel layer is provided between a source region and a drain region of a transistor. (For example, patent document 1).
JP 2002-151599 A

However, in the solid-state imaging device, removal of 1 / f noise is also an important issue, and importance is attached to the off characteristics of the selection transistor.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device capable of suppressing the deterioration of S / N due to pixel miniaturization and improving the off characteristics of a selection transistor. To do.

The solid-state imaging device according to the present invention removes noise of a semiconductor substrate, an imaging region provided on the semiconductor substrate, in which a plurality of photoelectric conversion pixels that perform photoelectric conversion are arranged, and signal charges output from the imaging region. A photoelectric conversion element that performs photoelectric conversion, a transfer transistor connected to the photoelectric conversion element, a reset transistor and an amplification transistor connected to the transfer transistor, and the amplification A selection transistor connected in series to the transistor, wherein the amplification transistor includes a first conductivity type first well region provided in the semiconductor substrate, and a second conductivity provided in the first well region. A first source region and a first drain region of the mold, and between the first source region and the first drain region in the first well region. A first channel impurity region of a second conductivity type having an impurity concentration lower than that of the first source region and the first drain region, a first gate insulating film provided on at least the first channel impurity region, A first gate electrode provided on the first channel impurity region via the first gate insulating film, and the selection transistor is a second well of the first conductivity type provided in the semiconductor substrate. A region, a second conductivity type second source region and a second drain region provided in the second well region, and between the second source region and the second drain region in the second well region A channel region of the first conductivity type provided in the channel, a second gate insulating film provided at least on the channel region, and a second gate insulating film provided on the channel region via the second gate insulating film. An insulating layer is provided in the semiconductor substrate between the first well region and the second well region, and the first source region and the second electrode are provided on the insulating layer. A connection portion for electrically connecting the drain region is provided, and the impurity concentration of the second Will region is higher than the impurity concentration of the first well region.

According to the present invention, it is possible to provide a solid-state imaging device that can suppress the deterioration of S / N due to pixel miniaturization and improve the off characteristics of the selection transistor.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic plan view for explaining an example of a chip configuration of a solid-state imaging device according to an embodiment of the present invention.

As shown in FIG. 1, the solid-state imaging device 100 according to the present embodiment includes an imaging region 101, a load transistor unit 102, a CDS circuit unit 103, a V selection unit 104, and an H selection provided around the imaging region 101. Means 105, AGC (automatic gain control) circuit 106, ADC (A /
D converter) 107, digital amplifier 108, TG (timing generator) circuit 109
Is arranged.

In the imaging region 101, a plurality of photoelectric conversion pixels 200 (not shown in FIG. 1) that convert incident light into electric charges are arranged on the array.

Among the configurations described above, the ADC 107 may be a column-type CDS-ADC circuit configured integrally with the CDS circuit 103.

In addition, the TG circuit 109, the AGC circuit 106, the ADC circuit 107, and the digital amplifier 108
May be formed on different chips.

FIG. 2 is a circuit diagram illustrating a part of a specific configuration of the imaging region 101 and the load transistor unit 102 illustrated in FIG. 1.

As shown in FIG. 2, a photoelectric conversion pixel 200 provided in the imaging region 101 includes a photoelectric conversion element (hereinafter simply referred to as PD) 201 that performs photoelectric conversion, a transfer transistor 202 connected to the PD 201, and transfer. A floating diffusion (hereinafter simply referred to as FD) 203 connected to the transistor 202 and a transfer transistor 202 via the FD 203
The reset transistor 204 and the amplification transistor 205 connected to each other, and the selection transistor 206 connected in series to the amplification transistor 205 are provided.

Specifically, the PD 201 is formed in the drain region of the transfer transistor 202.
The FD 203 is connected to the source of the transfer transistor 202, the drain of the reset transistor 204, and the gate of the amplification transistor 205. The source of the reset transistor 204 is connected to Vdd. The drain of the amplification transistor 205 is V
The source is connected to the drain of the selection transistor 206 at dd. The source of the selection transistor 206 is connected to the vertical signal line 207.

One end of the vertical signal line 207 is connected to the load transistor 2 in the load transistor unit 102.
The drain of the load transistor 208 is connected to the ground. The other end of the vertical signal line 207 is connected to the CDS circuit 103 outside the imaging area 101.

The amplification transistor 205 and the load transistor 208 that are vertically connected to the vertical signal line 207 constitute a source follower circuit, and the signal voltage generated in the FD 203 is supplied to the CDS circuit 10.
3 is output.

The selection transistor 206 connected in series to the amplification transistor 205 operates as a switch, and separates the amplification transistor 205 and the vertical signal line 207 in the non-selected row.

In FIG. 2, photoelectric conversion (PD 201), signal charge accumulation (
PD201), qv conversion (FD203), source follower circuit (amplification transistor 205)
, The load transistors 208) are formed. However, the present invention is not limited to this, and a plurality of PDs 201 and transfer transistors 202 are connected to one FD 203 as necessary.
The other reset transistor 204, amplification transistor 205, and selection transistor 206 may be shared, and a configuration of two pixels, one cell, four pixels, one cell, or the like can be adopted. Further, the amplification transistor 205 and the selection transistor 206 shown in FIG.

FIG. 3 is a cross-sectional view of the amplification transistor 205 and the selection transistor 206 according to the embodiment of the present invention.

The amplification transistor 205 and the selection transistor 206 according to the present embodiment are provided adjacent to each other on the semiconductor substrate 1 as shown in FIG. The amplification transistor 205 includes a first well region 2a provided in the semiconductor substrate 1, a first source region 3a and a first drain region 3b provided in the first well region 2a, and a first well region 2a. A channel impurity region 4a provided between the first source region 3a and the first drain region 3b, a gate insulating film 5 provided on the channel impurity region 4a, and the channel impurity region 4 via the gate insulating film 5
a first gate electrode 6a provided on a. The selection transistor 206 includes a first transistor
A second well region 2b provided in the semiconductor substrate 1 adjacent to the well region 2a, a second source region 3c and a second drain region 3d provided in the second well region 2b, and a second well region 2b A channel region 4b provided between the second source region 3c and the second drain region 3d, a gate insulating film 5 provided on the channel region 4b, and the channel region 4b via the gate insulating film 5. And a second gate electrode 6b provided thereon.

An interlayer insulating layer 7 is provided in the semiconductor substrate 1 between the first well region 2a and the second well region 2b, and the first well region 2a and the second well region 2b are electrically separated in the layer direction. ing. In addition, the first source region 3a of the amplification transistor 205 and the selection transistor 2
The second drain region 3d of 06 is electrically connected to the connection wiring 8 through the gate insulating layer 5, for example.

  The semiconductor substrate 1 is composed of a p-type semiconductor silicon substrate.

The first well region 2a and the second well region 2b are formed of a p-type semiconductor silicon layer (p-wel).
l (1) and p-well (2)). These regions can be formed, for example, by ion-implanting p-type impurities (for example, boron) from the surface of the semiconductor substrate 1.

The first source region 3a, the first drain region 3b, the second source region 3c, and the second drain region 3d are each a high-concentration n-type impurity diffusion layer (hereinafter, referred to as a high-concentration n-type impurity diffusion layer).
n + layer). These regions are, for example, n from the surface of the semiconductor substrate 1.
It can be formed by ion-implanting a type impurity (for example, phosphorus) at a high concentration.

The channel impurity region 4a is composed of an n-type impurity diffusion layer having an impurity concentration lower than that of the first source region 3a and the first drain region 3b. The channel impurity region 4a can be formed, for example, by ion-implanting n-type impurities from the surface of the semiconductor substrate 1.

The channel region 4b is composed of a region provided between the second source region 3c and the second drain region 3d, so-called second well region 2b. The channel impurity region 4a and the channel region 4b described above are described using different terms, but the channel impurity region 4a is an n-type impurity diffusion region in which an n-type impurity is diffused. The channel region 4b indicates a p-type impurity diffusion region in which n-type impurities are not diffused.

The gate insulating film 5 is made of, for example, a silicon oxide film or an oxynitride film. When an oxynitride film is used as the gate insulating film 5, it can be formed by forming an oxide film on the semiconductor substrate 1 and further nitriding the oxide film.

In FIG. 3, the gate insulating film 5 is on the semiconductor substrate 1, that is, the amplification transistor 2.
The first source region 3a, the first drain region 3b, the channel impurity region 4a, and the second source region 3c, the second drain region 3d, the channel region 4b, and the interlayer insulating layer 7 of the selection transistor 206 are provided. However, the present invention is not limited to this, and may be provided at least on the channel impurity region 4a and the channel region 4b.

The first gate electrode 6a and the second gate electrode 6b are composed of, for example, an n-type polycrystalline silicon layer. The first gate electrode 6a and the second gate electrode 6b can be formed by patterning after forming an n-type polycrystalline silicon layer by LP-CVD, for example.

The interlayer insulating layer 7 is made of, for example, a buried oxide film. For example, the interlayer insulating layer 7 is formed by performing trench etching on the semiconductor substrate 1 and then embedding a silicon oxide layer.
It can be formed by flattening with P.

For the connection wiring 8, for example, an Al wiring can be used. As shown in FIG. 3, when the gate insulating film 5 is formed on the interlayer insulating layer 7, the connection wiring 8 is connected to the first source region 3a and the second drain region 3d with respect to the gate insulating film 5. A contact hole is formed and A
It can be formed by forming l and the like by sputtering and patterning.

The first well region 2a is preferably composed of a relatively low concentration impurity diffusion layer in order to form the channel impurity region 4a. When the impurity concentration of the first well region 2a is high, the channel formed in the channel impurity region 4a has a potential peak in the vicinity of the surface, and a buried channel for reducing noise is formed. In some cases, the channel modulation cannot be performed, and the channel modulation degree (α = δΦ / δVg) of the amplification transistor is lowered, which is not preferable.

On the other hand, it is preferable that the impurity concentration of the second well region 2b is configured to be relatively high in consideration of the off characteristics of the selection transistor. If the impurity concentration of the second well region 2b is low, it is not preferable because the off characteristics of the selection transistor are deteriorated.

That is, the impurity concentration of the second well region 2b of the selection transistor 206 is preferably higher than the impurity concentration of the first well region 2a of the amplification transistor 205. That is, in order to reduce 1 / f noise as a solid-state imaging device and to improve the off characteristics of the selection transistor, well regions having different concentrations must be formed in adjacent regions of the semiconductor substrate 1.

However, it is practically impossible to simply form two well regions having different impurity concentrations adjacent to each other on the semiconductor substrate 1 without intervening each other. For example, as shown in FIG. 4, without providing the interlayer insulating layer 7 between the adjacent first well region 2a and second well region 2b, the first well region 2a in which the impurity concentration is changed by ion implantation or the like. When the second well region 2b is formed, the second well region 2b having a high impurity concentration is used.
Impurity diffusion from the first to the first well region 2a having a low impurity concentration occurs, and the first well region 2a
This is not preferable because the concentration of the liquid cannot be controlled.

The amplification transistor 205 and the selection transistor 206 that satisfy the above configuration are configured under the following conditions, for example.

-Impurity concentration of the semiconductor substrate 1 ... ^{2x10 15} cm ^-3 ,
-Impurity concentration of the first well region 2a ... 5 x 10 ¹⁶ cm ^-3 ,
-Impurity concentration of second well region 2b ... 5 × 10 ¹⁷ cm ^-3
Impurity concentration on the surface of the n + layer: 1 × 10 ²¹ cm ⁻³ ,
The maximum impurity concentration of the channel impurity layer 4a ... 5 × 10 ¹⁶ cm ⁻³ ,
・ Thickness of gate insulating film 5: 5 nm
* The measured value of the impurity concentration is based on the “SIMS” method.

It is more preferable that the load transistor 208 has a configuration similar to that of the amplification transistor 205. FIG. 5 is a sectional view of the load transistor 208 according to this embodiment. The load transistor 208 includes a third well region 2 provided in the semiconductor substrate 1.
c, a third source region 3e and a third drain region 3f provided in the third well region 2c
A channel impurity region 4c provided between the third source region 3e and the third drain region 3f in the third well region 2c, and a gate insulating film 5 provided on the channel impurity region 4c.
And a third gate electrode 6c provided on the channel impurity region 4c via the gate insulating film 5
And.

  The semiconductor substrate 1 is composed of a p-type semiconductor silicon substrate.

The third well region 2c is composed of a p-type semiconductor silicon layer (p-well (3)). This region can be formed, for example, by ion-implanting p-type impurities from the surface of the semiconductor substrate 1.

The third source region 3e and the third drain region 3f are each composed of an n + layer in which high-concentration n-type impurities are diffused. These regions can be formed, for example, by ion-implanting n-type impurities at a high concentration from the surface of the semiconductor substrate 1.

The channel impurity region 4c is composed of an n-type impurity diffusion layer having a lower impurity concentration than the third source region 3e and the third drain region 3f. The channel impurity region 4 c can be formed, for example, by ion-implanting n-type impurities from the surface of the semiconductor substrate 1.

The gate insulating film 5 is made of, for example, a silicon oxide film or an oxynitride film. When an oxynitride film is used as the gate insulating film 5, it can be formed by forming an oxide film on the semiconductor substrate 1 and further nitriding the oxide film.

In FIG. 5, the gate insulating film 5 is on the semiconductor substrate 1, that is, the load transistor 2.
Although the structure is provided on the third source region 3e, the third drain region 3f, and the channel impurity region 4c of 08, the present invention is not limited to this, and at least on the channel impurity region 4c. What is necessary is just to be provided.

The third gate electrode 6c is composed of, for example, an n-type polycrystalline silicon layer. The third gate electrode 6c can be formed by patterning after forming an n-type polycrystalline silicon layer by, for example, LP-CVD.

As described above, by providing the channel impurity region 4c also in the load transistor 208, 1 / f noise generated in the load transistor 208 can be suppressed, so that the 1 / f noise of the entire solid-state imaging device is reduced. And deterioration of S / N can be suppressed.

  The load transistor 208 that satisfies the above configuration is configured under the following conditions, for example.

-Impurity concentration of the third well region 5 × 10 ¹⁶ cm ⁻³
Impurity concentration on the surface of the N + layer: 1 × 10 ²¹ cm ⁻³ ,
-Maximum impurity concentration of the channel layer 4b ... 5 x 10 ¹⁶ cm ^-3 ,
・ Thickness of gate insulating film 5: 5 nm
* The measured value of the impurity concentration is based on the “SIMS” method.

  Moreover, the solid-state imaging device according to the first embodiment described above also has the effects described below.

The conversion gain in the qv conversion of the FD 203 is inversely proportional to the capacity of the FD 203. In order to reduce the S / N in the vertical signal line 207, the above-mentioned 1 / f noise is reduced, and
Increasing the signal voltage by increasing the conversion gain is also an important factor.

As shown in FIG. 2, the FD 203 is a capacitance formed by the drain capacitance of the transfer transistor 202 and the source capacitance of the reset transistor 204. Furthermore, q in FD203
In order to read the v-converted signal voltage, it is connected to the gate of the amplification transistor 204.

Therefore, by controlling the capacitance formed by the drain capacitance of the transfer transistor 202 and the source capacitance of the reset transistor 204, the FD 203 can
As a result, the qv conversion gain of the FD 203 is increased, the signal voltage is increased, and the S / N of the vertical signal line 207 is improved.

(Example 1)
The solid-state imaging device shown in FIGS. 1 to 3 was manufactured by a CMOS process. The amplification transistor 205 and selection transistor 206 shown in FIG. 3 at this time are configured as follows.

-Impurity concentration of the semiconductor substrate 1 ... 2 x 10 ¹⁵ cm ^-3
-Impurity concentration of the first well region 2a ... 5 x 10 ¹⁶ cm ^-3 ,
-Impurity concentration of second well region 2b ... 5 × 10 ¹⁷ cm ^-3
Gate and source regions 3a to 3d ... 1 x 10 ²¹ cm ^-3 ,
The maximum impurity concentration of the channel layer 4a ... 5 × 10 ¹⁶ cm ⁻³ ,
・ Thickness of the gate insulating film 3 ... 5 nm
The solid-state imaging device having the above configuration was operated, and imaging characteristics were evaluated.

As a result, by making the amplifying transistor a buried channel type, the S / N was improved by 3 dB, the off characteristics of the selection transistor were good, and desired imaging characteristics could be obtained.

(Comparative Example 1)
The solid-state imaging device shown in FIGS. 1 to 3 was manufactured by a CMOS process. The amplification transistor 205 and selection transistor 206 shown in FIG. 3 at this time are configured as follows.

-Impurity concentration of the semiconductor substrate 1 ... 2 x 10 ¹⁵ cm ^-3
-Impurity concentration of the first well region 2a ... 5 x 10 ¹⁶ cm ^-3 ,
Impurity concentration of second well region 2b ... 5 × 10 ¹⁶ cm ⁻³
Gate and source regions 3a to 3d ... 1 x 10 ²¹ cm ^-3 ,
The maximum impurity concentration of the channel layer 4a ... 5 × 10 ¹⁶ cm ⁻³ ,
・ Thickness of the gate insulating film 3 ... 5 nm
The solid-state imaging device having the above configuration was operated, and imaging characteristics were evaluated.

As a result, when a signal corresponding to saturation is generated in the pixel in the selected row, a current flows through the non-saturated amplification transistor in the non-selected row, and the signal line is higher than saturation (0 [V]). A voltage is generated, resulting in a decrease in saturation voltage and a decrease in dynamic range.

(Comparative Example 2)
The solid-state imaging device shown in FIGS. 1 to 3 was manufactured by a CMOS process. The amplification transistor 205 and selection transistor 206 shown in FIG. 3 at this time are configured as follows.

-Impurity concentration of the semiconductor substrate 1 ... 2 x 10 ¹⁵ cm ^-3
-Impurity concentration of the first well region 2a ... 5 x 10 ¹⁷ cm ^-3 ,
Impurity concentration of second well region 2b ... 5 × 10 ¹⁷ cm ⁻³
Gate and source regions 3a to 3d ... 1 x 10 ²¹ cm ^-3 ,
The maximum impurity concentration of the channel layer 4a ... 5 × 10 ¹⁶ cm ⁻³ ,
・ Thickness of the gate insulating film 3 ... 5 nm
The solid-state imaging device having the above configuration was operated, and imaging characteristics were evaluated.

As a result, the off characteristics of the selection transistor were sufficient and the imaging characteristics were normal, but the channel of the amplification transistor was not a buried channel type, the S / N was not improved,
The device sensitivity is reduced due to a decrease in the channel modulation degree (α = δΦ / δVg) of the amplification transistor.

(Other)
When the impurity concentration of the first well region 2a is higher than that of the first embodiment, the channel of the amplification transistor does not become a buried channel type, the S / N is not improved, and the channel modulation degree (α = The device sensitivity was lowered due to a decrease in (δΦ / δVg).

When the impurity concentration of the second well region 2b is lower than that of the first embodiment, the off characteristics of the selection transistor are insufficient and “selection transistor gate voltage = 0 [V]”, which is a non-selection state.
Even in this state, the channel potential of the selected transistor is higher than 0 [V]. As a result, when a signal corresponding to saturation is generated in the pixel of the selected row, the current through the unsaturated amplifying transistor in the unselected row is As a result, a voltage higher than saturation (0 [V]) is generated on the signal line. As a result, the saturation voltage is lowered and the dynamic range is lowered.

1 is a schematic plan view illustrating an example of a chip configuration of a solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a part of a specific configuration of an imaging region 101 and a load transistor unit 102 illustrated in FIG. 1. Sectional drawing of the amplification transistor and selection transistor which concern on embodiment of this invention. Sectional drawing for demonstrating the case where an interlayer insulation layer is not provided in FIG. Sectional drawing of the load transistor which concerns on embodiment of this invention. The figure for demonstrating the 1 / f noise which exists in the high frequency side rather than the sampling frequency (fs) of a CDS circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2a 1st well region 2b 2nd well region 3a 1st source region 3b 1st gate region 3c 2nd source region 3d 2nd gate region 3e 3rd source region 3f 3rd gate region 4a Channel impurity region 4b Channel region 4c Channel impurity region 5 Gate insulating film 6a First gate electrode 6b Second gate electrode 6c Third gate electrode 7 Interlayer insulating layer 8 Connection wiring

Claims (3)

A semiconductor substrate;
An imaging region provided on the semiconductor substrate and provided with a plurality of photoelectric conversion pixels for performing photoelectric conversion;
A CDS circuit for removing noise of signal charges output from the imaging region,
The photoelectric conversion pixel is
A photoelectric conversion element that performs photoelectric conversion;
A transfer transistor connected to the photoelectric conversion element;
A reset transistor and an amplification transistor connected to the transfer transistor;
A selection transistor connected in series to the amplification transistor,
The amplification transistor is
A first conductivity type first well region provided in the semiconductor substrate;
A first source region and a first drain region of a second conductivity type provided in the first well region;
A second channel of a second conductivity type provided between the first source region and the first drain region in the first well region and having an impurity concentration lower than that of the first source region and the first drain region; An impurity region;
A first gate insulating film provided on at least the first channel impurity region;
A first gate electrode provided on the first channel impurity region via the first gate insulating film,
The selection transistor is:
A second well region of a first conductivity type provided in the semiconductor substrate;
A second source region and a second drain region of a second conductivity type provided in the second well region;
A channel region of a first conductivity type provided between the second source region and the second drain region in the second well region;
A second gate insulating film provided on at least the channel region;
A second gate electrode provided on the channel region via the second gate insulating film,
An insulating layer is provided in the semiconductor substrate between the first well region and the second well region, and the first source region and the second drain region are electrically connected to the insulating layer. A solid-state imaging device comprising a connecting portion to be connected, wherein the impurity concentration of the second Will region is higher than the impurity concentration of the first well region. A load transistor connected to the selection transistor and the CDS circuit;
The load transistor is
A third well region of a first conductivity type provided in the semiconductor substrate;
A third source region and a third drain region of the second conductivity type provided in the third well region;
A second channel impurity region provided between the third source region and the third drain region in the third well region and having an impurity concentration lower than that of the third source region and the third drain region;
A third gate insulating film provided on at least the second channel impurity region;
The solid-state imaging device according to claim 1, further comprising: a third gate electrode provided on the second channel impurity region via the third gate insulating film. The solid-state imaging device according to claim 1, wherein the connection portion is a connection wiring provided on the gate insulating film.

Images