JP2011205109A - Solid-state imaging apparatus and camera using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a small quantity of noise by forming transistors having high controllability, using simple processes, and to provide a method of manufacturing the same.SOLUTION: There is provided a photoelectric conversion element prepared by forming a p-type well 102 on an n-type substrate 101, further, forming an n-layer 104 of a photodiode, forming thereon a p-layer 105 of the photodiode by increasing the surface concentration thereof, and forming a gate region 103 of a transferring MOS transistor via an insulating layer. A diffusion floating region FD107 is formed in the lateral lower portion of the gate region 103, to connect it with the gate of the amplifying MOS transistor of an output circuit. The drain of a MOS transistor 111 for a row selecting switch is connected to the source of the amplifying MOS transistor, and a current source 112 is connected with the source of the MOS transistor 111, to constitute an amplifying circuit of a source follower. As the transistor 110 for the source follower, an embedded MOS transistor is used and 1/f noise is reduced.

Description

  The present invention relates to a semiconductor device and a solid-state imaging device using the same, and more particularly to a CMOS image sensor.

  Typical solid-state imaging devices include a CCD sensor composed of a photodiode and a CCD shift register, and a CMOS sensor such as an APS (Active Pixel Sensor) composed of a photodiode and a MOS transistor.

  APS includes photodiodes, MOS switches, and amplification circuits for amplifying signals from the photodiodes for each pixel, and offers many advantages such as "XY addressing" and "single-chip sensor and signal processing circuit". have. However, on the other hand, since the number of elements in one pixel is large, it is difficult to reduce the pixel aperture ratio and to reduce the chip size that determines the size of the optical system, and the CCD occupies most of the market. ing.

  In recent years, it has attracted attention due to the improvement in the miniaturization technology of MOS transistors and the increasing demand for “single-chip sensor and signal processing circuit” and “low power consumption”.

  FIG. 5 shows an equivalent circuit diagram of a conventional APS (see, for example, Patent Document 1). The configuration of the prior art will be briefly described below.

  501 is a power supply line, 502 is a reset switch line for selecting a reset transistor, 503 is a selection switch line for selecting a selection transistor, 504 is a signal output line, 505 is a photodiode as a photoelectric conversion unit, and 506 is for selecting a transfer transistor Transfer switch line, Q1 is a transfer transistor, Q2 is a reset transistor, Q3 is a selection transistor, and Q4 is an amplifying transistor. The photoelectric conversion unit is an embedded photodiode used in a CMOS or CCD. The buried type photodiode suppresses dark current generated on the SiO2 surface by providing a high impurity concentration region (for example, p layer) on the surface, and between the accumulation portion (for example, n layer) and the surface p layer. In addition, a junction capacitance can be provided, and the saturation charge amount of the photodiode can be increased.

  The optical signal charge Qsig accumulated in the photoelectric conversion unit 505 is read out to a floating diffusion area through a transfer unit Q1 made of a MOS transistor. Q2 is a transistor for resetting the potential of the floating diffusion region.

  Voltage is converted into signal charge Qsig / CFD by the capacitance CFD of the floating diffusion region, and a signal is read out through the source follower circuit Q3. Q4 is a selection switch for row selection.

  In addition, there is a solid-state imaging device using a buried channel type MOS transistor as a reset transistor and a transfer transistor (for example, see Patent Document 2).

JP-A-11-274454 JP 2001-309243 A

  However, the conventional technique has a problem that a noise component is added to the output voltage due to 1 / f noise generated in the transistor portion of the source follower portion. For this reason, there is a method of forming the source follower portion with an embedded pMOS transistor, but the process becomes complicated and causes an increase in cost. In addition to the solid-state imaging device, when a surface channel type MOS transistor and a buried channel type transistor are used together in a chip, there is a problem that the manufacturing process becomes complicated.

  Therefore, an object of the present invention is to provide a semiconductor device with less noise by forming a transistor with high controllability by a simple process.

  In order to solve the above-described problems, a semiconductor device of the present invention includes both a buried channel type first conductivity type MOS transistor and a surface channel type first conductivity type MOS transistor, and the first conductivity type channel is located near the surface. The doped layer is present in both the buried channel and surface channel type MOS transistors, and a transistor for which 1 / f noise is to be suppressed can be formed in a necessary portion. Particularly in a solid-state imaging device that is sensitive to noise, the effect is tremendous. In addition, if a buried channel type transistor is used for the source follower type MOS transistor of the output unit of the solid state imaging device, a solid state imaging device with less noise can be formed, and it is particularly effective when there is a source follower MOS transistor in the pixel unit like a CMOS image sensor. It is. The surface channel type transistor preferably has a second conductivity type channel dope layer in the vicinity of the surface in addition to the first conductivity type channel dope layer, so that a transistor having excellent off characteristics can be formed at the same time. The dose amount of the first conductivity type channel dope layer is preferably smaller than the dose amount of the second conductivity type channel dope layer.

  Furthermore, the first conductivity type is n-type, and the channel doping layer of the first conductivity type is preferably arsenic. Thus, a semiconductor device with high controllability can be formed.

  Further, the embedded channel type first conductivity type MOS transistor and the surface channel type first conductivity type MOS transistor are both provided, and the first conductivity type channel doped layer is provided near the surface of the embedded channel and surface channel type MOS transistor. Both are manufactured in one step by an ion implantation method, and a transistor with high controllability can be formed by a simple process, so that a low-cost and low-noise semiconductor device can be provided.

  According to the present invention, both the buried channel type first conductivity type MOS transistor and the surface channel type first conductivity type MOS transistor are provided, and the first conductivity type channel doped layer is formed in the vicinity of the surface. By being present in both types of MOS transistors, a transistor in which 1 / f noise is desired to be suppressed can be formed in a necessary portion, and a semiconductor device with less noise can be formed. The surface channel type transistor preferably has a second conductivity type channel dope layer in the vicinity of the surface in addition to the first conductivity type channel dope layer, and a transistor having excellent off characteristics can be formed at the same time.

  In addition, both the buried channel type first conductivity type MOS transistor and the surface channel type first conductivity type MOS transistor have both the buried channel type and the surface channel type MOS transistor. In addition, since a transistor with high controllability can be formed in one step by using an ion implantation method, a low-cost and low-noise semiconductor device can be provided.

It is a figure showing embodiment of this invention. It is sectional drawing showing 1st Example of this invention. It is an impurity profile figure of 1st Example of this invention. It is sectional drawing showing 2nd Example of this invention. It is an equivalent circuit schematic of the pixel of a solid-state imaging device. It is an equivalent circuit diagram including the readout circuit of the area sensor using the present invention. It is sectional drawing showing the 4th Example of this invention. 1 is a configuration block diagram of a camera system using a solid-state imaging device according to the present invention.

  Next, the best mode of the present invention will be described by taking a solid-state imaging device as an example with reference to the drawings.

  FIG. 1 is a cross-sectional structure diagram that best represents the features of the present invention. In FIG. 1, the photoelectric conversion element is formed by forming a p-type well 102 on an n-type substrate 101, forming a thin n-type layer thereon, further forming an n-layer 104 of a photodiode, and forming a buried region and The p layer 105 is formed, and the gate region 103 of the transfer MOS transistor is formed on the side surface of the photodiode through the insulating layer.

  Further, a diffusion floating region FD107 is formed below the side surface of the gate region 103 of the transfer MOS transistor. The diffusion floating region FD107 is connected to the gate of the amplification MOS transistor of the output circuit, and the source of the amplification MOS transistor is The drain of the row selection switch MOS transistor 111 is connected, and the source of the row selection switch MOS transistor 111 is connected to the current source 112 serving as a load of the amplification MOS transistor to constitute a source follower amplifier circuit. An embedded MOS transistor is used as the source follower transistor 110 to reduce 1 / f noise. Here, the buried MOS transistor is a MOS transistor in which an impurity region having the same conductivity type as that of the source / drain regions is also formed in the channel region immediately below the gate.

  Further, the source of a reset MOS transistor 108 for resetting the diffusion floating region FD107 is connected to the diffusion floating region FD107, and the reset power source 109 is connected to the drain thereof. Here, the MOS transistors other than the source follower transistor are, for example, surface channel MOS transistors having a threshold voltage of 0.4V.

  Next, features of the present invention will be described in detail while explaining a read operation. Light enters and electrons generated by photoelectric conversion accumulate in the n-layer of the photodiode. At this time, the transfer MOS transistor is in an OFF state. After a predetermined accumulation time has elapsed, a positive voltage is applied to the control electrode (gate region) 103 of the transfer MOS transistor, the transfer MOS transistor is turned on, and the accumulated charge in the n layer of the photodiode is transferred to the diffusion floating region. . Before the transfer MOS transistor is turned on, the diffusion floating region is reset to a predetermined voltage in advance. When the stored charge is transferred to the diffusion floating region, the voltage of the diffusion floating region decreases from the reset voltage because the transfer charge is an electron when the transfer charge Qsig and the diffusion floating capacitance CFD are used. To do. If the storage layer of the photodiode is p-type, since the transfer charge is a hole, the voltage rises conversely.

  In such an APS, the output signal Vr1 immediately after the reset of the diffusion floating region 107 is temporarily held, and the difference (Vsig1-Vr1) from the output signal Vsig1 superimposed on the reset signal by Qsig / CFD is taken or the source By making the follower MOS transistor an embedded MOS transistor, most of noise components such as reset noise in the diffusion floating region 107 can be removed. In particular, when the photodiode and the transfer MOS transistor 103 satisfy the conditions described below, a higher noise removal rate is achieved. In other words, it is important to read out the signal charge accumulated in the n layer of the photodiode at a higher rate.

More specifically, if the voltage of the diffusion floating region, which is lowered from the reset voltage after reading the signal by the voltage of Qsig / CFD, is VFDsig1, and the transfer MOS transistor is in a sufficient ON state, the n layer of the photodiode A reverse bias of VFDsig1 is applied to the GND potential of the p-type well and the deep p-layer on the surface. At this time, in the n layer, a depletion layer extends from the p-type well and the deep p layer on the surface, and the entire n layer of the photodiode is depleted, so that the signal charge in the diffusion floating region is hardly left in the photodiode. Can be read out.
In this case, the photodiode is reset simultaneously with reading out the signal charges to the diffusion floating region. If the number of electrons remaining in the n layer is zero after reading, that is, with the reverse bias of VFDsig1 applied to the n layer of the photodiode, it is superimposed on the output signal Vr1 and the reset signal immediately after reset by Qsig / CFD By taking the difference from the output signal Vsig1, the reset noise can be completely removed, and an output signal Vsig1−Vr1 = Qsig / CFD × A (A is a gain of an output circuit for each pixel) can be obtained. .

  The output signal noise ΔVn1 such as 1 / f noise for each pixel is superimposed on this output signal, and the output from the integrated circuit IC formed as the final area sensor is the readout system after the output circuit for each pixel. Noise ΔVn2 is superimposed.

  In order to realize reading as described above, if a reverse bias is applied to the n-layer of the photodiode and the voltage at which the entire n-layer begins to be depleted is Vdep, it is necessary to satisfy Vdep <Vsig1. Here, the depletion voltage of the photodiode generally means a reverse bias voltage in which the number of accumulated charges in the accumulation unit <the number of net impurities. Ideally, the number of electrons remaining in the n-layer of the photodiode after reading is zero, but how completely read out is a matter of design. ΔVn1 is dominated by 1 / f noise and the like. In this case, there are methods such as thinning the gate oxide film or cleaning the surface, but a buried channel MOS transistor is very effective. In practice, if the noise in the photodiode section and ΔVn1 are sufficiently smaller than the above-described readout system noise ΔVn2, the noise component is dominated by ΔVn2.

  In the case of forming a buried MOS transistor which is a transistor in the source follower portion, an impurity 114 having the same conductivity type as that of the source / drain region is doped in the channel portion, and a region having the lowest potential is created in a region slightly deeper than the surface. In order to keep the cost low, it is necessary to perform the channel doping process of this embedded transistor without patterning, and it is necessary to reduce the doping amount in order to minimize the influence on other transistors. . In order to reduce the doping amount, it is preferable to use a well having the same conductivity type as the source / drain region. At this time, it is likely that the configuration does not turn off even when the gate voltage is 0 V, but there is no problem in using the source follower. It is preferable to use it as long as linearity is maintained. Transistors other than the source follower portion are required to have an off characteristic and a low substrate bias effect. In the off characteristics, the threshold voltage is controlled by doping impurities 115 of different conductivity types into the channel portion. Compared to the channel doping amount of the same conductivity type used for the embedded MOS transistor, a normal surface channel type transistor can be formed by implanting more impurities 115 of different conductivity types, and the threshold voltage can be raised until it becomes an enhancement type. is important. In terms of depth, the buried channel dope is formed slightly deeper from the surface, and the surface channel type dope is formed closer to the surface. This makes it possible to perform channel doping of the same conductivity type for the buried channel in one step without patterning. Therefore, the process is simple and low cost is realized, and also in the surface channel type MOS transistor, the substrate concentration under the channel portion is reduced, and the effect of reducing the substrate bias effect is obtained.

  Here, the first conductivity type is not particularly limited. The n-type dopant is preferable, and arsenic is preferable from the viewpoint of controllability because a steep profile in a shallow portion can be obtained. The well type is not particularly limited, and it is needless to say that wells of different conductivity types may be used. This will be described in detail in the examples.

  Example 1 will be described with reference to FIG. The photodiode of this embodiment and its periphery are formed by the following procedure.

  Boron was introduced into the p-type substrate 201 using ion implantation, and heat treatment was performed to form an n-type well 202 having a surface concentration of about 2 × 10 16 cm −3. A photoresist 208 was formed to form a p-layer 204 of a photodiode <FIG. 2 (a)>.

  After forming the gate oxide film on the entire substrate surface, boron was implanted at a dose of 2E12 cm −2 and 35 KeV by ion implantation to form a P-type first channel doped region 205. Next, a photoresist was formed in the buried channel portion, and phosphorus was implanted at 6E12 cm −2 and 50 KeV to form an n-type second channel doped region 206. FIG. 3 shows impurity profiles of the buried channel portion and the surface channel portion. In the buried channel type, the potential is determined by the gate voltage and the concentration profile of boron, and a potential valley exists at a position away from the surface to realize a buried channel. On the other hand, in the surface channel type, phosphorus is dominant as an impurity and determines the potential. However, in the lower part of the channel, carriers are offset by boron, the carrier concentration is reduced, and the substrate bias effect is reduced.

  Next, after removing the photoresist, a polysilicon control electrode doped with phosphorus was formed and patterned to form a control electrode 203 such as a source follower MOS transistor or a transfer MOS transistor (FIG. 2B). Next, a photoresist was formed on the photodiode on the substrate surface and in another region of a part of the control electrode, and a thick n layer 207 was formed using the control electrode 203 as a mask.

  Next, boron is ion-implanted into the pMOS transistor to form source / drain regions, and then the MOS transistor in the buried channel portion is covered with a photoresist, and further boron is ion-implanted to make the polysilicon control electrode p-type (209). A surface channel MOS transistor is formed.

  In this step, a source / drain region of a normal pMOS transistor including a peripheral circuit portion (not shown) was formed. The nMOS transistor is formed by a normal semiconductor process <FIG. 2 (c)>.

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, a second metal wiring, A passivation film was sequentially formed.

  As a result, it was possible to independently form the threshold voltages of the buried pMOS transistor whose polysilicon control electrode is an n-type diffusion electrode and the surface MOS transistor whose polysilicon control electrode is a p-type diffusion electrode. Compared to the noise of the source follower portion when all are formed by surface channel type MOS transistors, the noise is reduced to about 1/3 when the embedded channel type MOS transistor is used for the source follower portion as in this embodiment, which is good. Characteristics were obtained. Further, in the surface channel MOS transistor, since the impurity concentration under the channel portion is low, the substrate bias effect is small and good output characteristics can be obtained.

  Example 2 will be described with reference to FIG. The photodiode of this embodiment and its periphery are formed by the following procedure.

  Boron is introduced into the n-type substrate 410 by using ion implantation to form a deep P well 401. After resist patterning, boron is ion-implanted except for the photodiode portion, thereby creating a potential barrier against n-type and a well 402 of an N-type surface channel MOS transistor. Next, a photoresist 408 is formed, and an n-layer 404 of the photodiode is formed <FIG. 4A>.

  Next, arsenic was implanted at a dose of 6E11 cm −2 and 60 KeV without patterning by ion implantation to form a first channel doped region 405. Further, a photoresist was formed in the buried channel portion, and boron was ion-implanted into the channel portion of the N-type surface channel transistor at 2E12 cm −2 and 20 KeV to form the second channel doped region 406. In the N-type buried channel type, the potential is determined by the arsenic concentration profile, the gate voltage, and the deep P-well voltage, and a potential valley exists at a position away from the oxide film surface to realize a buried channel as a carrier path. On the other hand, in the surface channel type, boron is dominant as an impurity and determines the potential. This is because the boron concentration is increased compared to the arsenic concentration.

  After the gate oxide film is formed on the entire surface of the substrate, a polysilicon control electrode 403 doped with phosphorus at a high concentration is formed and patterned (FIG. 4B). Next, a photoresist extraction pattern was formed on the photodiode on the substrate surface and in a part of the control electrode, and a p-layer 407 having a dark surface was formed using the control electrode 403 as a mask.

  Thereafter, an nMOS transistor and a pMOS transistor including a peripheral circuit portion (not shown) were formed by a normal semiconductor process <FIG. 4C>.

  Further, according to a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, a second metal wiring, and a passivation Films were sequentially formed.

  As a result, the threshold voltages of the embedded NMOS transistor and other surface MOS transistors formed in the source follower portion can be independently controlled and formed. Compared to the noise of the source follower portion when all are formed by surface channel type MOS transistors, the noise is reduced to about 1/3 when the buried channel type NMOS transistor is used for the source follower portion as in this embodiment. Good characteristics were obtained. Unlike the first embodiment, since the nMOS is used in the pixel portion, the operation speed is high, and the photo diodes are also generated by the carriers generated by light. Sensitivity is also greatly improved due to the formation of a large vessel in terms of potential.

  Using the photodiode 505 and the transfer MOS transistor Q1 of Examples 1 and 2, an area sensor having the pixel configuration shown in FIG. 5 and the readout circuit shown in FIG. 6 was produced.

  In FIG. 5, a photodiode 505 and a transfer switch Q1 of a transfer MOS transistor are provided, Q2 is a reset switch of a reset MOS transistor for resetting the diffusion floating region, Q3 is connected to the gate of the diffusion floating region, and a load on the source side Q4 is an input MOS transistor of the source follower amplifier circuit formed by a buried channel transistor composed of a constant current source 812 connected as a selection switch for selecting a readout pixel.

  FIG. 6 shows a solid-state imaging device using pixel cells of photoelectric conversion elements constituted by these in 3 rows and 3 columns.

  The basic operation of FIGS. 5 and 6 will be described below. A reset operation for inputting a reset voltage to the input gate of the source follower by the reset switch Q2 and row selection by the selection switch Q4 are performed.

  The gate of the floating diffusion region of the input node of the source follower is floated, and noise components including fixed pattern noise such as reset noise and variation in threshold voltage of the source follower MOS are read, and the information is temporarily stored in the signal storage unit 805 To do.

  Thereafter, the transfer switch Q1 is opened and closed, the accumulated charge of the photodiode generated by the optical signal is transferred to the input node of the source follower, the sum of the noise component and the optical signal component described above is read and held in the signal storage unit 805.

  The common signal line 809 and 809 ′ are connected to the common signal line 809 and 809 ′ via the transfer switches 808 and 808 ′ to the common signal line, respectively, and the signal of the noise component and the sum of the optical signal component and the common signal line 1 (808). , The common signal line 2 (808 ′) is turned on, read out, and output as outputs 811 and 811 ′ through the output amplifiers 810, respectively.

  Thereafter, by taking the difference between the outputs 811 and 811 ′, the reset noise and the fixed pattern noise are removed, the optical signal component is extracted, and an image signal having a high S / N can be obtained.

  Reading was performed by the above method, and signal and noise were evaluated. As a result, a high S / N of dynamic range (S / N) = 75 to 85 dB for each bit was obtained.

  A fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view of a CCD image sensor using the present invention. Carriers from a photodiode pass through a potential well and are transferred with clocks φ1 and φ2.

  In the final stage, a diffusion floating region FD907 is formed below the side surface of the gate region 903 of the transfer MOS transistor, and this diffusion floating region FD907 is connected to the gate of the amplification MOS transistor of the output circuit and outputs as a source follower amplification circuit. . An embedded MOS transistor is used for the source follower transistor 910 to reduce 1 / f noise.

  Further, the source of a reset MOS transistor 908 for resetting the diffusion floating region FD907 is connected to the diffusion floating region FD907, and the reset power source 909 is connected to the drain thereof. Here, the MOS transistors other than the source follower transistor are surface channel type MOS transistors. The method for producing the surface channel type MOS transistor of the same type as the buried channel type MOS transistor is the same as that of the above embodiment, and it has been found that the present invention is applied to the CCD structure and has a great effect of noise reduction.

  FIG. 8 shows an example of a circuit block when the solid-state imaging device according to the present invention is applied to a camera. A shutter 1001 is provided in front of the taking lens 1002 and controls exposure. The amount of light is controlled by the diaphragm 1003 as necessary, and an image is formed on the solid-state imaging device 1004. A signal output from the solid-state imaging device 1004 is processed by a signal processing circuit 1005 and converted from an analog signal to a digital signal by an A / D converter 1006. The output digital signal is further processed by a signal processing unit 1007. The processed digital signal is stored in the memory 1010 or sent to an external device through the external I / F 1013. The solid-state imaging device 1004, the imaging signal processing circuit 1005, the A / D converter 1006, and the signal processing unit 1007 are controlled by a timing generation unit 1008, and the entire system is controlled by an overall control unit / arithmetic unit 1009. In order to record an image on the recording medium 1012, the output digital signal is recorded through a recording medium control I / F unit 1011 controlled by the overall control unit / arithmetic unit.

101, 201, 401, 901 Substrate 102, 202, 402, 902 Well 103, 203, 209, 403, 903 Control electrode 104, 204, 404 Photodiode portion 107, 907 Diffusion floating region 108, 908 Reset MOS transistor 109, 501 , 801, 909 Power source 110, 910 Source follower transistor 111 Row selection switch transistor 112, 812 Current source 113 Output terminal 114, 205, 405, 914 First channel dope 115, 206, 406 Second channel dope 207, 407 Surface layer 208, 408 Photoresist 410 Deep well 502, 802 Reset switch line 503, 803 Select switch line 504, 804 Signal output line 505 Photo diode 506, 813 Transfer switch line 8 5 signal storage unit 808 transfer switch 809 common signal line 1 to the transfer switch 808 'the common signal line 2 to the common signal line 1
809 'common signal line 2
810 Output amplifier 811 Output 1
811 'output 2
906 Charge transfer unit well

Claims (3)

A solid-state imaging device having a plurality of pixels each having a photoelectric conversion unit and a plurality of MOS transistors including a first conductivity type amplification MOS transistor for amplifying a signal based on the charge of the photoelectric conversion unit,
The plurality of MOS transistors include a surface channel type MOS transistor and a buried channel type MOS transistor, and the amplification MOS transistor is the buried channel type,
In the channel portion of the buried channel type MOS transistor, the first impurity of the first conductivity type is disposed at a predetermined depth from the surface, and the potential is low.
A channel portion of the surface channel type MOS transistor is formed in the same step as the first impurity, and a second impurity having the same conductivity type as the first impurity is disposed, and the surface side of the second impurity is the surface of the MOS transistor. A solid-state imaging device, wherein a third impurity having a conductivity type opposite to that of the second impurity is disposed.   2. The second conductivity type impurity is implanted into the gate electrode of the amplification MOS transistor, and the first conductivity type impurity is implanted into the surface channel type gate electrode. The solid-state imaging device described in 1.   An imaging optical system that forms an image of light, a solid-state imaging device according to claim 1 that photoelectrically converts the formed image, and an output signal from the solid-state imaging device is converted into a digital signal. And a signal processing circuit for processing.

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