JP2005123517A - Solid-state imaging apparatus, method of manufacturing thereof, line sensor, and solid-state imaging unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus which can be driven with a low voltage while the allowable ranges of impurity concentration and width of a bypass region are expanded, and to provide a method of manufacturing thereof and so on. <P>SOLUTION: The solid-state imaging apparatus includes at least a photodiode comprising an n-layer 104 formed in a p-well 102 and a p-layer 105 formed in the n-layer 104, a diffused layer 107 formed in the p-well 102, and a charge-transfer section for transferring the signal charge stored in the photodiode to the diffused region 107. The charge-transfer section comprises the p-well 102 located between the photodiode and the diffused region 107, an insulating film formed on the p-well 102 and on the diffused region 107, and a control electrode (gate region 103) formed on the insulating film. The n-layer 104 is so formed as to be arranged between the end of the charge-transfer-section side of the p-layer 105 and the p-well 102 of the charge-transfer section at the surface of the p-well 102 and of the p-layer 105, and is formed to be extended to the underneath of the control electrode (gate region 103). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof.

  Typical solid-state imaging devices include a CCD sensor composed of a photodiode and a CCD shift register, and a CMOS sensor such as an APS (Active Pixel Sensor) composed of a photodiode and a MOS transistor.

  APS includes photodiodes, MOS switches, and amplification circuits for amplifying signals from the photodiodes for each pixel, and offers many advantages such as "XY addressing" and "single-chip sensor and signal processing circuit". have. In particular, in recent years, APS has also attracted attention due to the improvement in the miniaturization technology of MOS transistors and the increasing demands for “single-chip sensor and signal processing circuit” and “low power consumption”. However, on the other hand, since the number of elements in one pixel is large, it is difficult to reduce the pixel aperture ratio and to reduce the chip size that determines the size of the optical system, and the CCD occupies most of the market. ing.

  In particular, a line sensor in which such sensors are arranged in a row is used for various applications including printers and scanners, and the market size is large.

  Here, a pixel portion of a general CCD line sensor and a solid-state imaging device using the pixel portion will be described.

In a general CCD line sensor, the photoelectric conversion unit is composed of an embedded photodiode. The buried photodiode suppresses dark current generated on the SiO ₂ surface by providing a thick p layer on the surface, and also provides a junction capacitance between the n layer of the storage portion and the p layer on the surface. And the saturation charge amount of the photodiode can be increased.

The optical signal charge Q _sig accumulated in the photoelectric conversion unit is read out to the charge transfer register unit via the transfer unit having the MOS structure. The charge transfer register section is composed of a signal charge transfer region made of n + type impurities formed on the substrate surface side, and a transfer electrode formed thereabove via an insulating layer made of a silicon oxide film SiO ₂ . . A P + type impurity region is formed between the photodiode and the transfer register, and the potential of the P + type impurity region is controlled by a read gate. As the gate electrode of the read gate 22, for example, the first phase (φV1) and third phase (φV3) transfer electrodes of the charge transfer register section are also used. In the final stage, for example, a signal is read through a source follower circuit.

  However, in the prior art, since the n layer which is the charge storage part is in a part away from the surface, in order to read the charge from here to the transfer register region, the control electrode of the transfer MOS transistor used in the transfer part is used. Therefore, it was necessary to apply a voltage higher than that of a normal MOS transistor.

FIG. 11 is a diagram showing the potential of the channel portion of a normal MOS transistor and a transfer MOS transistor. According to the figure, light is incident from the left side of the figure, and from the left side of the figure, a transparent insulating film such as transparent SiO ₂ , SiN, etc., a dark p layer of a photodiode, and an n layer are sequentially laminated. At this time, a level change curve indicated by the potential when the threshold voltage is applied is shown.

  That is, as described above, it is necessary to apply a higher voltage to the control electrode of the transfer MOS transistor than the normal MOS transistor because the n layer is located away from the surface as shown in the potential diagram of FIG. This is because the potential level change curve needs to be bent more greatly.

  In the prior art, almost all charges cannot be read from the photodiode as the threshold voltage increases. As a result, there is a problem in that unread reading of charges occurs in the photodiode, resulting in an afterimage or noise, and the image is significantly deteriorated.

  In order to solve this problem, a solid-state imaging device having a configuration in which a bypass region having the same conductivity type as the charge storage layer is provided in a region between the photodiode and the transfer MOS transistor is known. The concept of the bypass region has already been implemented and is reported by Non-Patent Document 1 and the like as shown in FIG.

  Such a solid-state imaging device includes an n-type charge accumulation portion (n layer) 504 provided in a p-type well 502 and a dark p-type surface layer 505 on the surface of the charge accumulation portion. An n-type impurity region to be a bypass region 508 is provided in the part. The fact that the bypass region 508 is formed by shifting the dark surface p layer 505 by using a mask is explained by providing a resist 507 to form the dark surface p layer 505 as shown in FIG. .

In the solid-state imaging device having the configuration in which the bypass region is provided, the electrons in the charge storage portion reach the transfer register through the surface of the transfer electrode 503 through the bypass region 508 having a low potential, so that the transfer voltage becomes smaller.
Television Society Technical Report, 1989, Vol. 13, no. 11, p. 73

  However, the demand for driving the solid-state imaging device at a lower voltage is still high.

Here, the above-described bypass region must satisfy the following conditions.
(A) A certain concentration and width are required to function as a bypass region. (B) Since depletion transfer is performed, the bypass region is depleted for all readout conditions. That is, the concentration and width of the bypass region are the same as the conditions. The lower limit is determined by (A), and the upper limit is determined by condition (B). As the substrate density increases as the pixels are reduced, the allowable range of the density and width of the bypass region is reduced.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device that can be driven at a low voltage by expanding the allowable range of the concentration and width of the bypass region, a manufacturing method thereof, and the like.

  In order to achieve the above object, a solid-state imaging device of the present invention is provided in a second semiconductor region of a second conductivity type in the first semiconductor region of the first conductivity type, and in the second semiconductor region. A photoelectric conversion unit having a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type in the first semiconductor region, and a signal charge accumulated in the photoelectric conversion unit. The first semiconductor region between the photoelectric conversion unit and the fourth semiconductor region, the first semiconductor region and the fourth semiconductor region for transferring the first semiconductor region to the fourth semiconductor region In the solid-state imaging device having at least a charge transfer unit including an insulating film formed thereon and a control electrode provided on the insulating film, the second semiconductor region includes the first and third semiconductor regions. The end of the third semiconductor region on the charge transfer portion side at the surface of the semiconductor region And it provided to be disposed between the first semiconductor region of said charge transfer section, and characterized in that it is provided to extend to the bottom of the control electrode.

  According to the solid-state imaging device of the present invention, the dynamic range can be widened by reducing the threshold value of the charge transfer unit that transfers the photocharge accumulated in the photoelectric conversion unit. In particular, since a bypass region that can effectively transfer the accumulated charge of electrons or holes is provided between the photoelectric conversion unit and the control electrode of the charge transfer unit, the bypass region can be obtained by making the voltage during reading appropriate. It becomes possible to push down the nearby potential barrier appropriately and to easily read out the photocharge. Therefore, an effect of assisting extraction of electrons from the charge storage layer can be obtained, the allowable range of the concentration and width of the bypass region can be increased, and the solid-state imaging device can be driven at a low voltage.

  Further, the second semiconductor region may be doped with arsenic ions.

  The peripheral circuit including at least an nMOS transistor may be provided, and the peripheral circuit may include an nMOS transistor and a pMOS transistor.

  The solid-state imaging device manufacturing method of the present invention is the above-described manufacturing method of the solid-state imaging device of the present invention, wherein the step of forming the second semiconductor region includes masking the control electrode of the charge transfer unit. And at least a step of introducing an impurity having the second conductivity type by an ion implantation method.

  Another method for manufacturing a solid-state imaging device according to the present invention is the method for manufacturing a solid-state imaging device according to the present invention, wherein the step of forming the second semiconductor region includes ion implantation using the control electrode as a mask material. Is performed at least twice.

  Still another solid-state imaging device manufacturing method according to the present invention is the above-described solid-state imaging device manufacturing method according to the present invention, wherein at least the control electrode is used as a mask material to form the second semiconductor region. After the implantation, ion implantation is performed using at least the control electrode as a mask material in order to form the third semiconductor region.

  Still another solid-state imaging device manufacturing method according to the present invention is the above-described solid-state imaging device manufacturing method according to the present invention, wherein the second semiconductor region is inclined so that ions are implanted under the control electrode. It is formed by ion implantation.

  In this case, the oblique ion implantation is performed a plurality of times, and the ion implantation angle to the relatively shallow portion of the second semiconductor region is larger than the ion implantation angle to the relatively deep portion of the second semiconductor region. It is good also as composition to do.

  Still another solid-state imaging device manufacturing method according to the present invention is the above-described solid-state imaging device manufacturing method according to the present invention, wherein the third semiconductor region is inclined so that ions are implanted away from the control electrode. It is formed by ion implantation.

  Still another solid-state imaging device manufacturing method according to the present invention is the above-described solid-state imaging device manufacturing method, wherein the solid-state imaging device includes a peripheral circuit having an LDD structure. In order to protect the photoelectric conversion unit from etching, the photoelectric conversion unit is masked.

  A line sensor of the present invention is a line sensor having a plurality of the solid-state imaging devices of the present invention, and has an output circuit including at least an nMOS transistor in an output stage.

  Another line sensor of the present invention is a line sensor having a plurality of the solid-state imaging devices of the present invention, and has an output circuit including at least an nMOS transistor and a pMOS transistor in an output stage.

  Moreover, the solid-state imaging unit of the present invention has a plurality of the solid-state imaging devices of the present invention.

  The solid-state imaging unit may include a control circuit that controls timings between the solid-state imaging devices or output values from the solid-state imaging devices.

  As described above, in the solid-state imaging device according to the present invention, the second semiconductor region has the charge transfer unit and the end of the third semiconductor region on the charge transfer unit side on the surfaces of the first and third semiconductor regions. The first semiconductor region is disposed so as to extend under the control electrode. Therefore, the solid-state imaging device according to the present invention has a configuration in which a bypass region that can effectively transfer the accumulated charge of electrons or holes is provided between the photoelectric conversion unit and the control electrode of the charge transfer unit. Therefore, by making the voltage at the time of reading appropriate, the potential barrier in the vicinity of the bypass region can be pushed down moderately and the photocharge can be easily read. Therefore, an effect of assisting extraction of electrons from the charge storage layer can be obtained, the allowable range of the concentration and width of the bypass region can be increased, and the solid-state imaging device can be driven at a low voltage.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional structure diagram that best represents the features of an embodiment of the present invention.

  The solid-state imaging device shown in FIG. 1 includes a p-type well 102 that is a first conductivity type first semiconductor region formed on an n-type substrate 101, and a second conductivity type formed on the upper surface side thereof. A photodiode n layer 104 which is a second semiconductor region, and a photodiode p layer 105 which is a third semiconductor region of the first conductivity type and which is formed with a deep surface on the upper surface side thereof. Yes. The n layer 104 and the p layer 105 constitute a photodiode which is a photoelectric conversion unit.

  Further, a gate region 103 formed of a control electrode of the transfer MOS transistor is formed on the side surface side of the photodiode via an insulating layer, and between the gate region 103 of the transfer MOS transistor and the side surface of the photodiode, an n layer of the photodiode is formed. A bypass region 106 that extends continuously from 104 to below the gate region 103 (control electrode) is formed. Further, a p-type well 102 between the photodiode and the diffusion region 107 for transferring the signal charge accumulated in the photodiode which is the photoelectric conversion unit to the diffusion region 107 which is the second conductivity type fourth semiconductor region, The charge transfer portion is constituted by the insulating film formed on the insulating film and the gate region 103 (control electrode) provided on the insulating film. The electrons that have passed through the bypass region 106 reach the diffusion region 107 that is the fourth semiconductor region of the second conductivity type, and are vertically transferred therefrom.

The vertical transfer register is composed of a signal charge transfer region made of N + type impurities formed on the substrate surface side, and a transfer electrode formed thereon via an insulating layer made of a silicon oxide film (SiO ₂ ), For example, the first phase (φV1) and third phase (φV3) transfer electrodes and the read gate of the vertical transfer register are also used.

  FIG. 2 is a timing chart of vertical transfer clocks φV1 to φV4 for driving the vertical transfer register in four phases.

  As described above, since the first-phase and third-phase transfer electrodes also serve as the gate electrodes of the readout gates, among the four-phase vertical transfer clocks φV1 to φV4, the vertical transfer clocks φV1 and φV3 are VL, The three voltage levels VH and VT are taken. The voltages VL and VH are transfer pulses for vertical transfer, and the highest voltage VT is a read pulse for reading signal charges from the photosensor to the vertical transfer register.

  A source follower circuit is connected to the final stage of the vertical transfer register, and a current source serving as a load of the amplifying MOS transistor is connected to the source follower circuit to constitute a source follower amplifier circuit.

  Next, features of the present invention will be described in detail while explaining a read operation.

  When light enters the photoelectric conversion unit, electrons generated by photoelectric conversion accumulate in the n layer of the photodiode. At this time, the transfer MOS transistor is in an off state. After a predetermined accumulation time has elapsed, a positive voltage is applied to the control electrode (gate region) 103 of the transfer MOS transistor to turn on the transfer MOS transistor, and the accumulated charge in the n layer of the photodiode is transferred to the diffusion region. Before the transfer MOS transistor is turned on, all the accumulated charges in the diffusion region are swept out in advance. The accumulated charge is transferred to the diffusion region and then transferred by the vertical transfer register.

  In order to further increase the noise removal rate, it is required that the photodiode and the transfer MOS transistor satisfy the conditions described below, and it is important to read out the signal charge accumulated in the n layer of the photodiode at a higher rate.

  More specifically, if the transfer MOS transistor is sufficiently on (that is, having a large potential difference), the n-type layer of the photodiode has a p-type well and a GND layer with a deep p-layer with respect to the GND potential. A reverse bias is applied. At this time, in the n layer, a depletion layer extends from the p-type well and the deep p layer on the surface, and the entire n layer of the photodiode is depleted, so that the signal charge in the diffusion region is hardly left in the photodiode. Can be read out. After reading the signal charge to the diffusion region, the signal charge is read by complete transfer by the vertical transfer register.

  Ideally, the number of electrons remaining in the n-layer of the photodiode after reading is zero, but how completely read out is a matter of design. In practice, it is sufficient if it is sufficiently smaller than the noise of the readout system.

  What is important here is that the transfer MOS transistor needs to be in a sufficiently on state, that is, a smooth potential state without a barrier layer, in order to realize the above-described operation. A bypass region 106 was provided between the type photodiode and the transfer MOS transistor. This bypass region is not necessarily in contact with the semiconductor surface. This is because the bypass region is interposed between the n-layer of the photodiode and the channel of the transfer MOS transistor, and of course, if it is a buried channel, the bypass region does not need to reach the surface. Also, even when there is a channel on the surface, it is best that the bypass region reaches the channel on the surface, but even if it does not, a transfer MOS transistor having a transfer voltage sufficiently lower than that of the prior art can be obtained.

  Furthermore, the fact that this bypass region exists under the gate of the transfer MOS transistor is also an effective point. When a gate voltage is applied, the potential under the gate is pushed up, but this effect is also added to the bypass and the potential is increased. Can be made lower.

It is known that connecting the transfer MOS transistor to the diffusion region in this way has the following effects.
(1) The impurity concentration of the diffusion floating region can be set high, and the depletion layer generated between the well and the diffusion floating region can be effectively spread to the p-type well side by the applied bias. This is because the voltage at the time of reading can be input arbitrarily and directly.
(2) A wide dynamic range that can be controlled by an external voltage can be ensured with respect to a small dynamic range that can be determined by the built-in potential of the impurity profile as in a CCD.
(3) By making the voltage at the time of reading appropriate, the potential barrier in the vicinity of the bypass region is moderately pushed down to facilitate reading.

  In order to reduce the size of the pixel, the transistor itself must be miniaturized, and the well concentration of the photodiode and the transfer MOS transistor inevitably increases. In addition, with the miniaturization of transistors, it is necessary to reduce the power supply voltage. In order to reduce the voltage while maintaining the amount of charge handled by the photodiode, it is necessary to increase the impurity concentration of the accumulation layer (n layer 104 in FIG. 1) of the depleted photodiode and make it thinner, and the bypass region is also a photodiode. Since it is necessary to deplete like the n layer, the width of the bypass region needs to be narrowed.

  Furthermore, while the processing dimensional accuracy of the width of the n-layer and bypass region of the photodiode becomes severe, the well concentration increases, thereby increasing the factors causing variations in processing, and further processing dimensional accuracy is required, resulting in a decrease in yield. Connected. In particular, the width of the bypass region is determined by the accuracy in the surface direction of the silicon substrate, and generally the processing accuracy is lower than that in the depth direction, which is a major factor in yield reduction. In the present invention, due to the effect (3) described above, the allowable range of the width of the bypass region is widened, and the yield is improved.

  In the present invention, the processing method is as follows, thereby improving the processing accuracy of the width of the bypass region and improving the yield.

  The bypass region of the CCD, which is the prior art, is formed by the ion implantation of the n layer of the photodiode before the formation of the control electrode of the transfer MOS transistor and the ion implantation of the deep p layer of the surface using the control electrode of the transfer MOS transistor as a mask material. Therefore, the width of the bypass region varies greatly depending on the alignment accuracy of the exposure apparatus.

  On the other hand, in the present invention, for example, as shown in the fourth embodiment, the bypass layer is formed by implanting ions obliquely using the n layer of the photodiode as a mask material for the control electrode (for example, polycrystalline silicon) of the transfer MOS transistor. By doing so, the width can be determined by the projection range of the ion implantation from the control electrode. Since the projection range of the ion implantation is used, the processing accuracy is increased. In addition, some examples will be shown in the embodiments described later. Essentially, the bypass region is formed by using the ion implantation using the control electrode of the transfer MOS transistor as a mask material, thereby improving the processing accuracy. Is. Furthermore, it is more effective to form the second semiconductor region (here, n-type) of the photodiode by a plurality of ion implantations, earn signal charges in a certain deep region, and transfer using the bypass region. As shown in the fifth embodiment, a great effect can be obtained by making the ion implantation angle into the relatively shallow portion larger than the ion implantation angle into the relatively deep portion.

  In the above description, the case where electrons are accumulated is described as an example. However, the present invention is not limited to the case where holes are accumulated or the type of accumulated charges and transfer MOS transistors. .

  For the purpose of driving at a low voltage, it is most preferable to dope the second semiconductor region of the photodiode with arsenic ions that can be easily thinned. In the case of doping with arsenic ions, the controllability by the mask is good and the accuracy can be improved, so that the yield is increased. Furthermore, it is preferable to dope arsenic ions in terms of dark current characteristics.

  A line sensor can also be created using a plurality of such solid-state imaging devices. At this time, it is preferable that the peripheral circuit is also composed of a low voltage drive CMOS circuit. Thereby, since all the line sensors can be configured with a low voltage system, the power consumption of the line sensors can be reduced. Furthermore, it is possible to create a line sensor unit (solid-state imaging unit) capable of obtaining a uniform image at low cost by incorporating a timing generator in a CMOS circuit and controlling each output value and timing.

[Example 1]
A first embodiment of the present invention will be described with reference to FIG. The photodiode according to the present embodiment and its peripheral configuration are formed by the following procedure.

Boron is introduced into the n-type substrate 901 by ion implantation, heat treatment is performed, a p-type well 902 having a surface concentration of about 2 × 10 ¹⁶ cm ⁻³ is formed, a photoresist 908 is formed thereon, and a photodiode is formed. N layer 904 was formed (FIG. 3A). Thereafter, the photoresist 908 was removed.

  In accordance with a normal semiconductor manufacturing process, a diffusion region 907 made of arsenic is formed, a source / drain region of a normal MOS transistor is formed, and a gate oxide film 910 is formed to a thickness of 30 nm on the entire substrate surface by thermal oxidation. After the formation, the transfer MOS transistor and the control electrode 903 of the charge transfer portion were formed (FIG. 3B).

  Next, after heat treatment at 950 ° C./20 minutes in a nitrogen atmosphere, a photoresist (not shown) is formed on the photodiode on the substrate surface and in a part of the control electrode, and the control electrode 903 is used as a mask. A p-layer 905 having a deep surface was formed (FIG. 3C).

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, and a second metal wiring Then, a passivation film was sequentially formed.

  By the above process, a bypass region 906 of about 100 nm was formed in the photodiode. When the transfer voltage of the transfer MOS transistor composed of the n layer in which the source is buried is not present and when it is present (in this embodiment), the transfer voltage is evaluated to be 12 volts and 7 volts, respectively. As a result, it was confirmed that the transfer voltage was greatly reduced by the bypass region.

[Example 2]
A second embodiment of the present invention will be described with reference to FIG. The photodiode according to the present embodiment and its peripheral configuration are formed by the following procedure.

Boron was introduced into the n-type substrate 601 by ion implantation and heat treatment was performed to form a p-type well 602 having a surface concentration of about 4 × 10 ¹⁶ cm ⁻³ . After forming a diffusion region 607 made of arsenic according to a normal semiconductor manufacturing process, a gate oxide film 610 is formed to a thickness of 15 nm by a thermal oxidation method, and polycrystalline silicon is deposited thereon to a thickness of 400 nm. Thus, the transfer MOS transistor and the control electrode 603 of the charge transfer part were formed (FIG. 4A).

  Thereafter, a photoresist (not shown) and a control electrode 603 were used as a mask material, and phosphorus ions were implanted at 100 KeV to form a photodiode n layer 604 (FIG. 4B). At this time, the projected range and standard deviation of phosphorus ions were 120 nm and 45 nm, respectively, with respect to the film thickness of 400 nm of polycrystalline silicon (control electrode 603), and the polycrystalline silicon sufficiently functioned as a mask material.

  Next, the photoresist is removed, heat treatment is performed at 950 ° C./20 minutes in a nitrogen atmosphere, phosphorus ions are slightly diffused, a photoresist 609 is formed, and the photoresist 609 and the control electrode 603 are used as a mask material. BF2 ions were implanted at 35 KeV (FIG. 4 (c)). Thereafter, the photoresist 609 was removed.

  Thereafter, the source / drain regions of the nMOS transistor constituting the peripheral circuit were formed.

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, and a second metal wiring Then, a passivation film was sequentially formed.

  Through the above steps, a bypass region 606 of about 100 nm was formed. When the transfer voltage of the transfer MOS transistor composed of the n layer in which the source is buried without the bypass region and the threshold voltage in the case of the present invention (invention) were evaluated, respectively, they were 12 volts and 7 volts, respectively. As a result, it was confirmed that the transfer voltage was greatly reduced by the bypass region.

  Further, since the peripheral circuit is also composed of a low-voltage driven nMOS circuit, it can be formed by the same process, and low voltage and power consumption can be reduced. Furthermore, when a CMOS process including pMOS is used, the number of processes increases, but a solid-state imaging device with high performance and low power consumption can be formed.

[Example 3]
A third embodiment of the present invention will be described with reference to FIG. 4 again. The photodiode according to the present embodiment and its peripheral configuration are formed by the following procedure.

Boron was introduced into the n-type substrate 601 by ion implantation and heat treatment was performed to form a p-type well 602 having a surface concentration of about 4 × 10 ¹⁶ cm ⁻³ . After forming a diffusion region 607 made of arsenic in accordance with a normal semiconductor manufacturing process, a gate oxide film 610 is formed to a thickness of 15 nm by a thermal oxidation method, and polycrystalline silicon is further deposited thereon to a thickness of 400 nm. Thus, the transfer MOS transistor and the control electrode 603 of the charge transfer part were formed (FIG. 4A).

  Thereafter, using a photoresist (not shown) and the control electrode 603 as a mask material, arsenic ions were implanted at 300 KeV to form an n-layer 604 of the photodiode (FIG. 4B). At this time, the projection range and standard deviation of arsenic ions were 160 nm and 53 nm, respectively, with respect to the film thickness of polycrystalline silicon (control electrode 603) of 400 nm, and the polycrystalline silicon sufficiently functioned as a mask material.

  Next, the photoresist is removed, heat treatment is performed at 950 ° C./20 minutes in a nitrogen atmosphere, arsenic ions are slightly diffused, a photoresist 609 is formed, and the photoresist 609 and the control electrode 603 are used as a mask material. BF2 ions were implanted at 35 KeV (FIG. 4 (c)). Thereafter, the photoresist 609 was removed.

  Further, source / drain regions of normal MOS transistors in the peripheral circuit were formed.

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, a second metal wiring, A passivation film was sequentially formed.

  Through the above steps, a bypass region 606 of about 100 nm was formed. When the transfer voltage of the transfer MOS transistor composed of the n layer in which the source is buried without the bypass region and the threshold voltage in the case of the present invention (invention) were evaluated, they were 12 volts and 6 volts, respectively. As a result, it was confirmed that the transfer voltage was greatly reduced by the bypass region. Furthermore, in the configuration of this example, more charges could be accumulated than in the configuration of Example 2 even at the same voltage.

[Example 4]
A fourth embodiment of the present invention will be described with reference to FIGS. The photodiode according to the present embodiment and its peripheral configuration are formed by the following procedure.

First, boron was introduced into the n-type substrate 601 by ion implantation and heat treatment was performed to form a p-type well 602 having a surface concentration of about 4 × 10 ¹⁶ cm ⁻³ . In accordance with a normal semiconductor manufacturing process, after forming the diffusion region 607, a gate oxide film 610 is formed to a thickness of 15 nm by a thermal oxidation method, and polycrystalline silicon is further deposited thereon to a thickness of 400 nm for transfer. A control electrode 603 of the MOS transistor and the charge transfer unit was formed (FIG. 4A).

  Thereafter, using the photoresist 1008 and the control electrode 603 as a mask material, arsenic ions were implanted obliquely at 300 KeV to form an n-layer 604 of the photodiode (FIG. 5). The ion implantation angle θ at this time was 20 °. Since ion implantation is performed obliquely in this manner, arsenic ions extend under the control electrode 603 even immediately after ion implantation. At this time, the projection range and standard deviation of arsenic ions were 160 nm and 53 nm, respectively, with respect to the film thickness of polycrystalline silicon (control electrode 603) of 400 nm, and the polycrystalline silicon sufficiently functioned as a mask material.

  Next, another photoresist 609 was formed, and BF 2 ions were implanted at 35 KeV using the photoresist 609 and the control electrode 603 as a mask material (FIG. 4C). At this time, the ion implantation angle θ is set to 7 ° to suppress channeling. Thereafter, the photoresist 609 was removed.

  Further, source / drain regions of normal MOS transistors in the peripheral circuit were formed.

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, and a second metal wiring Then, a passivation film was sequentially formed.

  Through the above steps, a bypass region 606 of about 100 nm was formed. When the transfer voltage of the transfer MOS transistor composed of the n layer in which the source is buried without the bypass region and the threshold voltage in the case of the present invention (invention) were evaluated, they were 12 volts and 6 volts, respectively. As a result, it was confirmed that the transfer voltage was greatly reduced by the bypass region.

  In this embodiment, arsenic is ion-implanted obliquely to form the bypass region 606, so that the heat treatment at 950 ° C./20 minutes in the nitrogen atmosphere performed for diffusing arsenic in Embodiment 3 can be omitted. Therefore, the heat treatment time of the semiconductor process can be shortened, and the peripheral MOS transistors used for signal processing and the like can be further miniaturized.

[Example 5]
As Embodiment 5 of the present invention, in the formation process in Embodiment 4 described above, arsenic ion implantation is performed using a first ion implantation for providing a bypass region and a second ion implantation for providing an n layer of a photodiode. It was divided into two times.

  The first ion implantation was performed at an ion implantation angle θ of 45 ° and 300 KeV. The ion implantation angle θ is set to be greater than 20 ° in order to place a peak value near the surface and secure a bypass region.

  The second ion implantation was performed at an ion implantation angle θ of 7 ° and 400 KeV in order to control the saturation amount of the n layer of the photodiode.

  According to this embodiment, the ion implantation angle in the bypass region and the ion implantation in the n layer of the photodiode are separated, so that the ion implantation angle, ion implantation energy, and ion implantation dose can be optimized according to the respective characteristics. It was.

[Example 6]
Embodiment 6 of the present invention will be described with reference to FIG. The photodiode according to the present embodiment and its peripheral configuration are formed by the following procedure.

Boron was introduced into the n-type substrate 1101 by ion implantation and heat treatment was performed to form a p-type well 1102 having a surface concentration of about 2 × 10 ¹⁶ cm ⁻³ . In accordance with a normal semiconductor manufacturing process, after forming a vertical transfer region 1107 made of arsenic, a gate oxide film 1110 is formed to a thickness of 30 nm by thermal oxidation, and a transfer MOS transistor and a control electrode 1103 of a charge transfer unit are formed. . Thereafter, using a photoresist (not shown) and the control electrode 1103 as a mask material, arsenic ions were implanted at 300 KeV to form an n-layer 1104 of the photodiode (FIG. 6A). In the step of forming the vertical transfer region 1107 and the like, the source / drain regions of a normal MOS transistor were formed.

  Next, the photoresist (not shown) is removed, heat treatment is performed at 950 ° C./20 minutes in a nitrogen atmosphere, and after arsenic ions are diffused slightly, the peripheral CMOS transistor is subjected to a low concentration for an LDD (Lightly-Doped Drain) structure. After providing the n layer and the p layer, a side spacer 1111 as a mask means was formed on the side surface of the control electrode 1103 with a width of 150 nm (FIG. 6B). The side spacers 1111 are made of SiO, SiN, or the like, and are formed as described above by etching after leaving a predetermined portion after coating the entire surface of the substrate.

  Subsequently, a photoresist 1109 was formed, and BF2 ions were implanted at 35 KeV using the photoresist 1109, the control electrode 1103, and the side spacer 1111 as a mask material (FIG. 6C). At this time, the ion implantation angle θ is set to 7 ° to suppress channeling.

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, and a second metal wiring Then, a passivation film was sequentially formed.

  As a result, a bypass region 1106 of about 150 nm was formed. When the transfer voltage of the transfer MOS transistor composed of the n layer in which the source is buried without the bypass region and the transfer voltage in the case of the present invention (invention) were evaluated, respectively, they were 12 volts and 6 volts, respectively. As a result, it was confirmed that the transfer voltage was greatly reduced by the bypass region 1106.

  Note that when the side spacer 1111 is formed and etching is performed in a state where the photodiode portion is masked and protected by the side spacer 1111 and a photoresist (not shown) or the like, dark current generated in the photodiode portion can be suppressed (FIG. 7).

[Example 7]
A seventh embodiment of the present invention will be described with reference to FIGS. 4, 5, and 8. The photodiode according to the present embodiment and its peripheral configuration are formed by the following procedure.

Boron was introduced into the n-type substrate 601 by ion implantation and heat treatment was performed to form a p-type well 602 having a surface concentration of about 4 × 10 ¹⁶ cm ⁻³ . In accordance with a normal semiconductor manufacturing process, a vertical transfer region 607 made of arsenic is formed, and after forming a source / drain region of a normal MOS transistor, a gate oxide film is formed to 15 nm by thermal oxidation, and polycrystalline silicon is formed to 400 nm. To form a transfer MOS transistor and a control electrode 603 of the charge transfer portion (FIG. 4A).

  Thereafter, using the photoresist 609 and the control electrode 603 as a mask material, arsenic ions were implanted obliquely at 300 KeV to form a photodiode n layer 604 (FIG. 5). The ion implantation angle θ at this time was 10 °. In order to perform this oblique ion implantation, arsenic ions extend under the control electrode 603 even immediately after the ion implantation. At this time, the projected range and standard deviation of arsenic ions were 160 nm and 53 nm, respectively, with respect to the film thickness of 400 nm of the polycrystalline silicon (control electrode 603), and the polycrystalline silicon sufficiently functioned as a mask material.

  Next, another photoresist 1203 was formed, and BF 2 ions were implanted at 35 KeV using the photoresist 1203 and the control electrode 603 as a mask material (FIG. 8). The ion implantation angle θ at this time was −15 °.

  Since the control electrode 603 forms a shade, the p-layer 605 having a thick surface can be provided by being separated from the control electrode 603 by 400 × sin (15 °) = 100 nm.

  Thereafter, in accordance with a normal semiconductor manufacturing process, a first interlayer insulating film, a contact, a first metal wiring, a second interlayer insulating film, a via connecting the first metal wiring and the second metal wiring, and a second metal wiring Then, a passivation film was sequentially formed.

  As a result, a bypass region 606 of about 150 nm was formed. In this embodiment, arsenic ions are implanted obliquely to form a bypass region, so that the heat treatment at 950 ° C./20 minutes in the nitrogen atmosphere for diffusing the phosphorus ions performed in Embodiment 2 can be omitted. . Therefore, the heat treatment time of the semiconductor process can be shortened, and the peripheral MOS transistors used for signal processing and the like can be further miniaturized.

  In addition, as a result of evaluating the variation of the S / N ratio in each example, the magnitude of the variation is (Example 4, Example 5) <(Example 3, Example 6, Example 7) <(Implementation) Example 2) There is a relationship of << (Example 1). From the result, it is effective to form arsenic at a low temperature and in a self-aligned manner by the control electrode in terms of variation in S / N ratio. It turns out that it is.

[Example 8]
As Example 8, a line sensor including the readout circuit shown in FIG. 9 was manufactured using the photodiode having the configuration described in Examples 1 to 7, the transfer MOS transistor Q1, and the charge transfer unit.

  The line sensor of this embodiment includes a plurality of photosensors that perform photoelectric conversion and a vertical transfer register that transfers the photoelectrically converted charge, and the charge is transferred from the vertical transfer register to the charge detection unit. . The charge detection unit is configured by, for example, a floating diffusion amplifier, and converts the charge transferred from the vertical transfer register into a signal voltage and outputs the signal voltage.

The vertical transfer register includes a signal charge transfer region 5 made of N + type impurities formed on the surface side of the substrate, and a transfer electrode 6 formed thereon via an insulating layer made of a silicon oxide film SiO _2. ing. As the gate electrode of the readout gate, for example, the transfer electrode 6 of the first phase (φV1) and the third phase (φV3) of the vertical transfer register is also used.

In the line sensor shown in FIG. 9, the transfer MOS transistor Q1 includes an output switch and transfers charges to the diffusion layer. This diffusion layer is connected to the gate of the input MOS transistor of the source follower amplifier circuit composed of a constant current source connected as a load on the source side, and constitutes a floating diffusion amplifier (FDA). The diffusion layer is charged to the reset potential before the output gate is turned on. The output from the FDA is amplified by the amplifier, the signal charges cut a DC component in capacitors, the clamp voltage fluctuation component due to the capacitive coupling when the switch S1 has passed a certain time t ₁ has is turned on is the V _cl Is done. Thereafter, when the time t ₂ has elapsed and the switch S2 is turned on, a signal from which the noise component has been removed can be extracted. By configuring such a peripheral circuit with nMOS transistors, it can be formed by the same process as the pixel portion, and low voltage and low power consumption can be achieved. Furthermore, using a CMOS process with pMOS added to such a peripheral circuit increases the process, but a line sensor with high circuit performance and low power consumption can be formed, and the dynamic range is large and low noise and low voltage operation is possible. Can be obtained.

  Thus, an image signal having a high S / N ratio could be obtained by removing the reset noise and the fixed pattern noise and extracting the optical signal component.

  In this embodiment, a multi-chip line sensor unit is configured by connecting the plurality of line sensors described above. FIG. 10 shows a configuration diagram thereof.

  The shift register 201 of the vertical transfer unit is connected to an external substrate and transmits a signal to an adjacent line sensor. Furthermore, the timing generator 200 and the like are also configured in the same chip, and control each other's timing. Further, the line sensor unit may include a feedback control circuit so that each line sensor generates the same output when receiving a certain amount of light.

  According to the present embodiment, a multi-chip line sensor unit (solid-state imaging unit) that can be driven at a low voltage, has high uniformity, has high performance, and is low in cost can be configured.

1 is a cross-sectional structure diagram that best represents the features of an embodiment of the present invention. 5 is a timing chart of vertical transfer clocks φV1 to φV4 for driving a vertical transfer register in four phases. It is a figure which shows the photodiode which concerns on Example 1 of this invention, and its periphery structure. It is a figure which shows the photodiode which concerns on Example 2, 3, 4, 7 of this invention, and its periphery structure. It is a figure which shows the photodiode which concerns on Example 5, 7 of this invention, and its periphery structure. It is a figure which shows the photodiode which concerns on Example 6 of this invention, and its periphery structure. It is a figure which shows the photodiode which concerns on Example 6 of this invention, and its periphery structure. It is a figure which shows the photodiode which concerns on Example 7 of this invention, and its periphery structure. It is a figure which shows the line sensor which concerns on Example 9 of this invention. It is a figure which shows the multi-chip line sensor unit which concerns on Example 9 of this invention. It is a figure showing the potential of the channel part of a normal MOS transistor and a transfer MOS transistor. It is a figure which shows the conventional solid-state imaging device of the structure which provided the bypass area | region of the same conductivity type as a charge storage layer in the area | region between a photodiode and a transfer MOS transistor.

Explanation of symbols

5 signal charge transfer region 6 transfer electrode 101, 601, 901, 1101 n-type substrate 102, 602, 902, 1102 p-type well 103 gate region 104, 604, 904, 1104 photodiode n-layer 105, 605, 905, 1105 photodiode P layer 106,606,906,1106 bypass region 107,607,907 diffusion region 200 timing generator 201 shift register 603,903,1103 control electrode 609,908,1008,1109,1203 photoresist 610,910,1110 gate oxide film 1107 Vertical transfer area 1111 Side spacer

Claims (15)

A photoelectric device having a second semiconductor region of a second conductivity type in the first semiconductor region of the first conductivity type and a third semiconductor region of the first conductivity type provided in the second semiconductor region. A conversion unit;
A fourth semiconductor region of the second conductivity type in the first semiconductor region;
The first semiconductor region between the photoelectric conversion unit and the fourth semiconductor region for transferring the signal charge accumulated in the photoelectric conversion unit to the fourth semiconductor region; and A charge transfer section having an insulating film formed on the semiconductor region and the fourth semiconductor region, and a control electrode provided on the insulating film;
In a solid-state imaging device having at least
The second semiconductor region is between the end of the third semiconductor region on the charge transfer portion side and the first semiconductor region of the charge transfer portion on the surface of the first and third semiconductor regions. A solid-state imaging device, wherein the solid-state imaging device is provided so as to be disposed under the control electrode and extends below the control electrode.   The solid-state imaging device according to claim 1, wherein the second semiconductor region is doped with arsenic ions.   The solid-state imaging device according to claim 1, further comprising a peripheral circuit including at least an nMOS transistor.   The solid-state imaging device according to claim 3, wherein the peripheral circuit includes an nMOS transistor and a pMOS transistor. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 4,
The step of forming the second semiconductor region includes at least a step of introducing an impurity having the second conductivity type by an ion implantation method using the control electrode of the charge transfer portion as a mask material. A method for manufacturing a solid-state imaging device. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 4,
The step of forming the second semiconductor region includes performing ion implantation at least twice using the control electrode as a mask material. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 4,
After performing ion implantation using at least the control electrode as a mask material to form the second semiconductor region, ions are formed using at least the control electrode as a mask material to form the third semiconductor region. A method for forming a solid-state imaging device, wherein injection is performed. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 4,
The method for forming a solid-state imaging device, wherein the second semiconductor region is formed by oblique ion implantation so that ions are implanted under the control electrode. The oblique ion implantation is performed a plurality of times,
The solid-state imaging device according to claim 8, wherein an ion implantation angle into a relatively shallow portion of the second semiconductor region is larger than an ion implantation angle into a relatively deep portion of the second semiconductor region. Method. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 4,
The method for forming a solid-state imaging device, wherein the third semiconductor region is formed by oblique ion implantation so that ions are implanted away from the control electrode. A method for manufacturing a solid-state imaging device according to any one of claims 1 to 4,
The solid-state imaging device includes a peripheral circuit having an LDD structure, and masks the photoelectric conversion unit to protect the photoelectric conversion unit from etching when the LDD structure is created. Production method. A line sensor having a plurality of solid-state imaging devices according to claim 1,
A line sensor comprising an output circuit including at least an nMOS transistor in an output stage. A line sensor having a plurality of solid-state imaging devices according to claim 1,
A line sensor comprising an output circuit including at least an nMOS transistor and a pMOS transistor in an output stage.   5. A solid-state imaging unit including a plurality of solid-state imaging devices according to claim 1.   The solid-state imaging unit according to claim 14, further comprising a control circuit that controls a timing between the solid-state imaging devices or an output value from the solid-state imaging devices.

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