KR20110000959A - Image sensor and fabricating method thereof - Google Patents

Abstract

PURPOSE: An image sensor and a manufacturing method thereof are provided to improve picture quality by discharging electrons, which are overcharged in a photo diode, into a floating diffusion region. CONSTITUTION: A gate electrode(111) is formed on a semiconductor substrate(101). A photodiode region is formed on the semiconductor substrate in one side of the gate electrode. A floating diffusion region is formed on the semiconductor substrate in the other side of the gate electrode. A buried channel layer(120) interlinks the photodiode region and the floating diffusion region. A diffusion blocking layer(121) and a lower part diffusion blocking layer(122) are formed to be spaced apart from the semiconductor substrate surface.

Description

Image sensor and fabrication method thereof

An embodiment provides an image sensor and a method of manufacturing the same.

CMOS image sensor uses CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits to make as many MOS transistors as the number of pixels and uses this to switch the outputs sequentially. It is an element employing a system. These CMOS image sensors can be easily driven, implemented in a variety of scanning methods, and can be integrated in a single chip, enabling miniaturization of products, and using compatible CMOS technology to reduce manufacturing costs. In addition, power consumption is significantly lower than that of CCDs, which are used in a wide range of products.

In general, the pixel unit of the CMOS image sensor is composed of one photo diode and four transistors, each of which transfers electrons accumulated in the photo diode to a floating diffusion region. Reset Transistors that transfer reset signals to the Transfer Transistor, Photodiode and Floating Diffusion areas, Driver Transistors acting as source follower amplifiers, switching and addressing roles. It consists of a select transistor. Transfer and reset transistors can also be fabricated as negative NMOS transistors, which typically have low threshold voltages, to maximize the transistor's voltage transfer efficiency. The driver transistor and the select transistor are made of a transistor having a normal threshold voltage. In general, all four transistors are manufactured in a surface channel. In the case of the transfer transistor, if a large amount of electrons are collected in the photodiode in the process of focusing photocharges before the turn-on state of the transfer transistor in which the surface channel is formed, some electrons flow into the substrate and neighbor unit pixels. In this case, a blooming phenomenon occurs that deteriorates the characteristics of the corresponding unit pixel.

The embodiment provides an image sensor and a method of manufacturing the same that can effectively control the blooming phenomenon.

An embodiment provides an image sensor and a method of manufacturing the same, in which a transfer transistor maintains a turn-off state while accumulating electrons in a photodiode, wherein electrons accumulated in the photodiode are removed through a reset transistor by drawing out the floating diffusion region. .

The image sensor may include a gate electrode formed on a semiconductor substrate, a photodiode region formed on the semiconductor substrate on one side of the gate electrode, a floating diffusion region formed on the semiconductor substrate on the other side of the gate electrode, and a lower portion of the gate electrode. A buried channel layer spaced apart from a semiconductor substrate surface, the buried channel layer connecting the photodiode region and the floating diffusion region, and formed to be spaced apart from the surface of the semiconductor substrate, an upper diffusion barrier layer and a lower diffusion layer formed above and below the buried channel layer. And a prevention layer.

According to an embodiment of the present disclosure, a method of manufacturing an image sensor may include forming a buried channel layer for blooming control in a semiconductor substrate, and forming an upper diffusion barrier layer and a lower diffusion barrier layer below the buried channel layer, respectively. Forming a gate electrode of a transfer transistor on the buried channel layer, the upper diffusion barrier layer, and the semiconductor substrate above the lower diffusion barrier layer, the buried channel layer on the semiconductor substrate on one side of the gate electrode; Forming a photodiode region to be connected to the upper diffusion barrier layer and the lower diffusion barrier layer and a floating diffusion region to be connected to the buried channel layer, the upper diffusion barrier layer and the lower diffusion barrier layer on the semiconductor substrate on the other side of the gate electrode Forming a step.

In the image sensor according to the embodiment, the transfer transistor is turned off while accumulating electrons in the photodiode, and the electrons accumulated in the photodiode are removed to the floating diffusion region to control blooming and improve image quality. There is.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

CMOS image sensors are classified into 3T type, 4T type, and 5T type according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors. In the following Examples, but described as 4T type, the present invention is not limited thereto.

1 is a circuit diagram illustrating another image sensor in an embodiment, and FIG. 2 is a cross-sectional view illustrating a part of the image sensor according to the circuit diagram of FIG. 1. 2 illustrates a photodiode PD, a transfer transistor Tx, and a floating diffusion region FD of an image sensor.

1 and 2, in the unit pixel of the image sensor according to the exemplary embodiment, an active area is defined in the semiconductor substrate 101, and a device isolation area is formed in portions except the active area.

The photodiode region PD formed in the region having the largest area in the active region, the transfer transistor Tx, the reset transistor Rx, and the drive transistor formed to overlap the active region other than the photodiode region PD. Dx) and select transistor Sx.

That is, gate electrodes of the transistors are disposed on the active region, and impurities are implanted into the semiconductor substrates on both sides of the gate electrodes to form a source region and a drain region.

The photodiode PD detects incident light and generates electric charges according to the amount of light.

The transfer transistor Tx serves to transport charges generated in the photodiode PD to the floating diffusion region FD during the turn-on operation. Before transport, the floating diffusion region FD is set to a predetermined low charge state by turning on the reset transistor Rx for electrons from the photodiode PD.

In the transfer transistor Tx, a PNP layer connecting the photodiode PD and the floating diffusion region FD is formed under the channel under the gate electrode 111, so that the photodiode FD is formed through the PNP layer. The generated excess electrons escape and are removed through the turn-on reset transistor Rx.

The PNP layer includes a buried channel layer 120 and a diffusion blocking layer 121 and 122 formed above and below the buried channel layer 120, respectively.

The buried channel layer 120 is formed by implanting N-type impurities and is connected to the photodiode PD and the floating diffusion region FD.

The diffusion barrier layers 121 and 122 are formed above and below the buried channel layer 120, respectively, and are formed by implanting P-type impurities. The diffusion barrier layers 121 and 122 inject impurities of the opposite type to the buried channel layer 120 so that the dopant of the buried channel layer 120 has a channel layer or epitaxial surface on the epitaxial layer 103. It serves to prevent the diffusion below the shir layer 103.

The channel layer is a region formed along an interface between the gate electrode 111 and the epitaxial layer 103 of the transfer transistor Tx. The photodiode PD is turned on when the transfer transistor Tx is turned on. The charge accumulated in the film moves to the floating diffusion region FD through the channel layer.

The reset transistor Rx serves to discharge charge stored in the floating diffusion region FD for signal detection.

The drive transistor Dx serves as a source follower for converting charges from the photodiode PD into a voltage signal.

Referring to the transfer transistor of the CMOS image sensor according to the embodiment with reference to Figure 2, the photodiode region PD and the P ++ type semiconductor substrate 101 defined as the active region and the device isolation region, and on the semiconductor substrate 101 A gate electrode 111 formed on the P-type epitaxial layer 103, the isolation layer 105 formed in the device isolation region, and the gate insulating layer 113 on the epitaxial layer 103. ), An N-type diffusion region 133 formed in the epitaxial layer 103 of the photodiode region PD, a gate spacer 115 formed on both sidewalls of the gate electrode 111, and the gate spacer N + type impurity ions are formed in the LDD region 131 formed in the active region between the transistors Tx, Rx, and Dx formed in the active region below the 115 and the epitaxial layer 103 of the floating diffusion region FD. And an n + type diffusion region 137 formed by implantation.

In the transfer transistor Tx, a PNP layer connecting the photodiode PD and the floating diffusion region FD is formed under the channel under the gate electrode 111, so that the photodiode FD is formed through the PNP layer. The generated excess electrons escape and are removed through the turn-on reset transistor Rx.

The PNP layer includes a buried channel layer 120 and a diffusion blocking layer 121 and 122 formed above and below the buried channel layer 120, respectively.

The buried channel layer 120 is formed by implanting N-type impurities and is connected to the photodiode PD and the floating diffusion region FD.

The diffusion barrier layers 121 and 122 are formed above and below the buried channel layer 120, respectively, and are formed by implanting P-type impurities. The diffusion barrier layers 121 and 122 inject impurities of a type opposite to the buried channel layer 120 so that the dopant of the buried channel layer 120 is below the channel layer or epitaxial layer on the surface of the epitaxial layer 103. It serves to prevent the spread.

As a result, the embodiment may effectively improve the blooming phenomenon while the electrons accumulate in the photodiode PD while the transfer transistor Tx connected to the photodiode PD in the image sensor is turned off.

3 is a flowchart illustrating a manufacturing method of an image sensor according to an exemplary embodiment.

First, an epitaxial process is performed on the P ++ type semiconductor substrate 101 to form a P-type epitaxial layer 103 (S100).

An isolation layer 105 is formed in the epitaxial layer 103 to define an active region and an isolation region (S110).

The device isolation layer 105 may be formed by forming a trench having a predetermined depth in the epitaxial layer 103 and filling an insulating layer in the trench.

A well region is formed in the epitaxial layer 103 on which the device isolation layer 105 is formed through an implant process (S120).

For example, a P-type implant process may be selectively performed to form well regions for the drive transistor Dx and the select transistor Sx.

Subsequently, a P-type implant process for removing a dark source on the surface of the silicon substrate may be performed in some regions under the photodiode region PD and the transfer transistor Tx.

In the P-type implant process, the gate insulating film 113 and the epitaxial layer below the gate electrode 111 are formed at the interface between the gate insulating film 113 and the epitaxial layer 103 under the gate electrode 111 of the transfer transistor Tx. P-type doped regions suitable for minimizing dark current may be formed at the interface between the tactic layers 103. The p-type doped region may be formed only in an area corresponding to a portion of the gate length, which is biased toward the photodiode. The P-type doped region allows most of the dark current generated at the interface between the epitaxial layer 103 and the gate insulating layer 113 to escape toward the floating diffusion region FD.

Thereafter, an N-type implant process is performed to form the buried channel layer 120 connecting the photodiode region PD and the floating diffusion region FD under the gate electrode 111 of the transfer transistor Tx ( S130).

The buried channel layer 120 is formed inside the epitaxial layer 103 at a predetermined distance from the surface of the epitaxial layer 103.

The buried channel layer 120 may be formed under the channel layer where the transfer transistor Tx is turned on and electrons accumulated in the photodiode PD are transferred to the floating diffusion region FD.

In the N-type implant process, ion implantation energy is 10 to 200 KeV.

The dopant used in the implant process for forming the buried channel layer 120 may be selected from Group 5 elements including P and As.

Subsequently, an upper diffusion barrier layer 121 and a lower diffusion barrier layer 122 may be formed on the buried channel layer 120 by using a dopant of a type opposite to that of the buried channel layer 120, respectively. (S140).

The buried channel layer 120 may be in contact with the upper diffusion barrier layer 121, and the buried channel layer 120 may be in contact with the lower diffusion barrier layer 122.

The upper diffusion barrier layer 121 prevents the N-type dopant injected into the buried channel layer 120 from being unnecessarily diffused toward the surface of the epitaxial layer 103.

The lower diffusion barrier layer 122 prevents the N-type dopant injected into the buried channel layer 120 from being unnecessarily diffused toward the bottom of the epitaxial layer 103.

The upper and lower diffusion barrier layers 121 and 122 are selected from Group III elements including B (Boron), and ion implantation energy is 10 to 200 KeV.

The upper diffusion barrier layer 121 and the lower diffusion barrier layer 122 may be connected to the photodiode region PD and the floating diffusion region FD.

That is, the upper diffusion barrier layer 121, the buried channel layer 120, and the lower diffusion barrier layer 122 are n + of the N-type diffusion region 133 of the photodiode region PD and the floating diffusion region FD. It may be connected to the type diffusion region 137.

The upper diffusion barrier layer 121, the buried channel layer 120, and the lower diffusion barrier layer 122 may be formed of a PNP layer.

The buried channel layer 120 serves to remove unnecessary excess electrons from the photodiode region PD to the floating diffusion region FD when the transfer transistor Tx is turned off. Excess electrons transferred to the floating diffusion region FD are removed through the reset transistor Rx.

When a predetermined gate voltage is applied to the gate of the transfer transistor Tx and turned on, electrons accumulated in the photodiode along the channel layer on the epitaxial layer 103 surface float from the photodiode region PD. It is transferred to the diffusion region FD.

In this case, electrons transferred to the floating diffusion region FD are transferred to the drive transistor Dx.

As such, after the implant process for forming the upper and lower diffusion barrier layers 121 and 122 is completed, a silicon oxide film and a polysilicon layer are formed and patterned on the epitaxial layer 103 to form gates of the respective transistors. It may be (S150).

Thereafter, an LDD region 131 is formed, and a gate spacer 115 is formed on sidewalls of the gate electrode 111.

An n-type dopant may be implanted into the epitaxial layer 103 to form a photodiode region PD and a floating diffusion region FD of each unit pixel, and form source and drain regions of the respective transistors (S160). .

In the transfer transistor Tx according to the embodiment, the buried channel layer 120 connecting the photodiode region PD and the floating diffusion region FD is formed under the channel under the gate electrode 111. Excess electrons generated in the photodiode region PD exit through the channel layer 120 and are removed through the turn-on reset transistor Rx.

The transfer transistor Tx according to the exemplary embodiment may use a negative charge pump to increase the full well of electrons while facilitating off current control. Such circuits are well known to those skilled in the art.

In describing the embodiments, what is referred to as N-type or P-type dopants may be different dopants according to semiconductor devices. For example, the PNP layer may be formed of an NPN layer, and instead of implanting an N-type dopant to form source and drain regions of the transistor, the PNP layer may be implanted to form a source and drain region of the transistor.

Although described above with reference to the embodiments are only examples and are not intended to limit the invention, those of ordinary skill in the art to which the present invention does not exemplify the above within the scope without departing from the essential characteristics of the present invention It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiments of the present invention can be modified and implemented. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a circuit diagram illustrating another image sensor in an embodiment.

FIG. 2 is a cross-sectional view illustrating a part of the image sensor according to the circuit diagram of FIG. 1.

3 is a flowchart illustrating a manufacturing method of an image sensor according to an exemplary embodiment.

Claims (10)

A gate electrode formed on the semiconductor substrate; A photodiode region formed on the semiconductor substrate on one side of the gate electrode; A floating diffusion region formed on the semiconductor substrate on the other side of the gate electrode; A buried channel layer formed below the gate electrode to be spaced apart from the surface of the semiconductor substrate and connecting the photodiode region and the floating diffusion region; And And an upper diffusion barrier layer and a lower diffusion barrier layer formed above and below the buried channel layer. The method of claim 1, And a channel formed on a surface of the semiconductor substrate under the gate electrode, and electrons integrated in the photodiode are transferred to the floating diffusion region through the channel. The method of claim 1, The buried channel layer is an image sensor, characterized in that the first conductive dopant is formed by ion implantation. The method of claim 1, The diffusion barrier layer is an image sensor, characterized in that the second conductive dopant is formed by ion implantation. The method according to claim 3 or 4, And the first conductive dopant is one of N-type and P-type, and the second conductive dopant is the other. Forming a buried channel layer for blooming control in the semiconductor substrate; Forming an upper diffusion barrier layer and a lower diffusion barrier layer on the buried channel layer and below the buried channel layer, respectively; Forming a gate electrode of a transfer transistor on the buried channel layer, the upper diffusion barrier layer, and the semiconductor substrate on the lower diffusion barrier layer; Forming a photodiode region on the semiconductor substrate at one side of the gate electrode to be connected to the buried channel layer, the upper diffusion barrier layer and the lower diffusion barrier layer; And And forming a floating diffusion region on the semiconductor substrate on the other side of the gate electrode so as to be connected to the buried channel layer, the upper diffusion barrier layer, and the lower diffusion barrier layer. The method of claim 6, In the step of forming the buried channel layer, The buried channel layer is a method of manufacturing an image sensor, characterized in that formed by ion implanting a first conductive dopant with 10 ~ 200 KeV energy on the semiconductor substrate. The method of claim 6, In the forming of the upper and lower diffusion barrier layer, The upper and lower diffusion barrier layers are formed by ion implanting a second conductive dopant into the semiconductor substrate with 10 to 200 KeV energy, respectively. The method of claim 6, And the first conductive dopant is one of N type and P type, and the second conductive dopant is the other. The method of claim 6, And the buried channel layer, the upper diffusion barrier layer and the lower diffusion barrier layer are formed spaced apart from the surface of the semiconductor substrate by a predetermined distance.

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