JP2008192813A - Ccd (charge coupled device) solid-state image sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a high S/N (signal to noise ratio) even when the pixel size of a CCD solid-state image sensor becomes minute. <P>SOLUTION: The frame interline transfer type CCD solid-state image sensor is provided with a sensor unit 2 having a plurality of photoelectric conversion elements 11 arrayed and formed so as to form a two-dimensional array and a plurality of first vertical charge transfer paths 12, a horizontal charge transfer path 4 and an accumulation unit 3 provided between the horizontal charge transfer path 4 and the sensor unit 2 while being provided with a plurality of second vertical charge transfer paths 15 continuous with the first vertical charge transfer path 12. In this case, the structure of the second vertical charge transfer path 15 is made so as to have a low dark current structure with respect to the structure of the first vertical charge transfer path 12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a CCD solid-state imaging device, and more particularly to a CCD solid-state imaging device with a low dark current and a high S / N.

  A CCD (Charge Coupled Device) solid-state imaging device has a large number of photodiodes formed in a two-dimensional array on the surface of a semiconductor substrate and receives signal charges (in many cases electrons) according to the amount of light received. Detect, the vertical charge transfer path transfers this signal charge to the horizontal charge transfer path, and then the horizontal charge transfer path transfers the signal charge to the output amplifier so that the output amplifier has a voltage value corresponding to each signal charge amount. The signal is output as a captured image signal.

When dark current is suppressed by such a CCD solid-state imaging device, the dark current generated by the photodiode forms a p-type high-concentration impurity layer on the surface of the photodiode, and the electrons that are dark current components are converted into p-type high-concentration impurities. In general, suppression by promoting rapid recombination with holes accumulated at the Si / SiO ₂ interface in the layer is performed.

  The dark current generated in the charge transfer path is formed as a double channel structure by forming a p-type channel on the n-type buried channel of the charge transfer path as described in Patent Document 1 below, for example. Next, it can be suppressed by forming a dark current drain structure that discards electrons trapped in the p-type channel.

Japanese Patent No. 2816824

  In recent years, the number of pixels mounted on a CCD solid-state imaging device has increased to millions of pixels, and the light receiving area of one pixel (photodiode) has been steadily decreasing and has become a pixel size of 2 μm □ or less. Yes. For this reason, the width of each vertical charge transfer path has also been reduced.

  Therefore, in order to reduce the dark current in the vertical charge transfer path, even if the double channel structure described in Patent Document 1 is adopted, there is no space for manufacturing the dark current drain structure beside each vertical charge transfer path, There is a problem that it is difficult to suppress the dark current in the vertical charge transfer path. In particular, the dark current in the CCD solid-state image sensor has a ratio of 90% generated in the vertical charge transfer path, and in order to further increase the number of pixels and increase the sensitivity of the CCD solid-state image sensor, Current generation has become an important issue.

  An object of the present invention is to provide a CCD solid-state imaging device having a low dark current and a high S / N.

  The CCD solid-state imaging device of the present invention includes a sensor unit having a plurality of photoelectric conversion elements and a plurality of first vertical charge transfer paths arranged in a two-dimensional array, a horizontal charge transfer path, and the horizontal charge transfer path. In the frame interline transfer type CCD solid-state imaging device, comprising a storage unit having a plurality of second vertical charge transfer paths that are provided between the sensor section and continuous with the first vertical charge transfer paths. The structure of the second vertical charge transfer path is a low dark current structure with respect to the structure of the charge transfer path.

  The CCD solid-state imaging device of the present invention is characterized in that the transfer speed of the first vertical charge transfer path is controlled to be 10 times or more and 20 times or less with respect to the transfer speed of the second vertical charge transfer path.

  The CCD solid-state imaging device of the present invention is characterized in that the width of the second vertical charge transfer path is wider than the first vertical charge transfer path.

  In the CCD solid-state imaging device of the present invention, the low dark current structure has a buried channel for transferring signal charges detected by the photoelectric conversion device, and a surface channel formed on the buried channel for transferring dark current. It is characterized by a dual channel structure.

  In the CCD solid-state imaging device according to the present invention, the charge transfer in the second vertical charge transfer path in which the buried channel is formed of an n-type region and the surface channel is formed of a p-type region is performed only by a plus voltage. It is characterized by being performed by pulses.

  The CCD solid-state imaging device of the present invention is characterized in that a drain for discarding the dark current of the surface channel is provided at the final stage position connected to the horizontal charge transfer path of the second vertical charge transfer path.

  The CCD solid-state imaging device according to the present invention is characterized in that the length of the final stage is increased by the width of the second vertical charge transfer path at the final stage position where the drain is provided.

  According to the present invention, since the charge transfer path of the storage unit has a low dark current structure, the S / N is improved even if the pixel size is reduced to increase the number of pixels, and this CCD solid-state imaging device is mounted. It is possible to achieve high sensitivity of a digital camera or the like.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic view of the surface of a CCD solid-state imaging device according to an embodiment of the present invention. The CCD solid-state imaging device of this embodiment is a frame interline transfer (FIT) type, and a sensor unit (light receiving region) 2, a storage unit 3, a horizontal charge transfer path 4, and a surface portion of a semiconductor substrate 1. An output amplifier 5 provided at the output end of the horizontal charge transfer path 4 is provided.

  The sensor unit 2 includes a plurality of photoelectric conversion elements (photodiodes PD) 11 arranged in a two-dimensional array, in the illustrated example, in a square lattice shape, and vertical charge transfer formed along each photoelectric conversion element array. A road (VCCD) 12.

  The storage unit 3 includes a vertical charge transfer path 15 provided continuously for each vertical charge transfer path 12 of the sensor unit 2, but is a transfer path wider than the vertical charge transfer path 12 of the sensor unit 2. . That is, the charge transfer path 15 of the storage unit 3 is wider by the amount that the photoelectric conversion element 11 of the sensor unit 2 is not in the storage unit 3.

  In the storage unit 3 of this embodiment, the drain control electrode 16 is provided between the adjacent charge transfer paths 15 at the transfer direction end of each charge transfer path 15.

  The horizontal charge transfer path (HCCD) 4 transfers the signal charge received from each vertical charge transfer path 15 of the storage unit 3 in the horizontal direction, and the output amplifier 5 sets the charge amount of the signal charge transferred in the horizontal direction. A corresponding voltage value signal is output as a captured image signal.

  The terms “horizontal” and “vertical” are used in the description, which means “one direction” along the surface of the semiconductor substrate and “a direction substantially perpendicular to the one direction”.

  FIG. 2 is a schematic cross-sectional view taken along the line II-II in FIG. 1, and is a schematic cross-sectional view of the photodiode 11 and the vertical charge transfer path 12 adjacent thereto in the sensor unit 2.

  In a p-well layer or p-type substrate 21 formed on an n-type substrate (not shown), an n region (hereinafter referred to as n region 11) constituting the photodiode 11 is formed, and a surface portion of the n region 11 is formed. In addition, a p-type high concentration impurity layer 22 for dark current suppression is formed.

  An n region 12a is formed on the surface portion of the p-type substrate 21 where the vertical charge transfer path 12 is formed, and a p region 23 having a slightly higher impurity concentration than the p-type substrate 21 is formed below the n-type region 12a. Provided.

  In addition, a high-concentration p-type impurity region 24 is provided between the n region 12a and the photodiode on the right side (not shown) for element isolation. A p region 25 having a slightly higher concentration than the p-type substrate 21 is provided between the n region 12a and the left region (the side where signal charges are read) n region 11.

  An insulating film 26 such as silicon oxide is formed on the outermost surface of the p-type substrate 21. A transfer electrode film 12b made of a polysilicon film is formed on the n region 12a via an insulating film 26, and the vertical charge transfer path 12 is formed by the n region 12a and the transfer electrode film 12b. Since the transfer electrode film 12b shown in the drawing also serves as a readout electrode, the end portion on the photodiode 11 side extends to the end portion position of the n region 11.

  The transfer electrode film 12b is covered with an insulating film 27, and the entire surface of the sensor unit 2 is covered with a light shielding film 28 such as a tungsten film. An opening 29 is provided above each photodiode 11 in the light shielding film 28, and incident light enters the n region 11 through the opening 29.

  Although not shown, a planarizing film, a color filter layer, a microlens layer, a protective film layer, and the like are laminated on the light shielding film 28.

  FIG. 3 is a schematic cross-sectional view taken along the line III-III in FIG. 1 and is a schematic cross-sectional view of the vertical charge transfer path 15 in the storage unit 3. An n region 15 a serving as a buried channel is formed on the surface portion of the p-well layer or the p-type substrate 21. The n region 15a is formed with a depth and concentration continuous with the n region 12a described in FIG. 2, and serves as a channel for transferring signal charges (electrons).

  Under the n region 15a, the p region 23 described with reference to FIG. 2 is formed at a depth and concentration that is continuous with the p region 23 of FIG.

  A thin p-type surface layer 15c is formed on the surface of n region 15a. The p-type surface layer 15 c serves as a channel for transferring dark current generated in the vertical charge transfer path 15 of the storage unit 3. That is, the present embodiment is characterized in that the vertical charge transfer path 15 of the storage unit 3 has a double channel structure, and the vertical charge transfer path 12 of the sensor unit 2 does not have a double channel structure.

  The insulating film 26 is formed on the outermost surface of the semiconductor substrate 21, and the transfer electrode film 15b made of polysilicon is formed thereon. The transfer electrode film 15b has a well-known two-layer structure, three-layer structure, or single-layer structure, similar to the transfer electrode film 12b. In the present embodiment, the vertical charge transfer path 15 is formed by the n region 15a, the p-type surface layer 15c, and the transfer electrode film 15b.

  A high-concentration p-type region 24 is provided as an element isolation region between the n region 15a and the p-type surface layer 15c and the adjacent vertical charge transfer path 15. An insulating film 27 is laminated on the transfer electrode film 15b, and a light shielding film 28 is laminated thereon.

  FIG. 4 is a potential diagram along line IV-IV in FIG. When the voltage applied to the transfer electrode film 15b is set to 0V, as indicated by the characteristic line A, a potential well is formed at the location of the n region 15a, and the potential at the location of the p-type surface layer 15c remains flat. is there.

  On the other hand, when a positive voltage is applied to the transfer electrode film 15b, the potential well at the location of the n region 15a becomes deeper as shown by the characteristic lines B and C, while the potential at the location of the p-type surface layer 15c becomes a mountain shape. It becomes.

  That is, by always setting the transfer pulse of the transfer electrode film 15b to a positive voltage, dark current is accumulated in the surface portion of the surface channel of the p-type surface layer 15c, and mixing of dark current into the n region 15a is prevented. .

  FIG. 5 is a schematic cross-sectional view taken along the line VV of FIG. 1, and is a schematic cross-sectional view of the transfer electrode stage provided with the drain control electrode 16. Since the structure of the portion of the vertical charge transfer path 15 is the same as the structure described with reference to FIG. 3, the same reference numerals are given to the same members and the description thereof is omitted.

  In the final stage of the vertical charge transfer path 15, a drain control electrode 16 is provided instead of the element isolation region 24 shown in FIG. Since the drain control electrode 16 and its lower structure are wider than the element isolation region 24, the channel width of the vertical charge transfer path 15 is reduced accordingly. Therefore, as shown in FIG. 1, with respect to each transfer electrode length d of the charge transfer path 15, the transfer electrode length D in the final stage is made longer, and the transfer charge capacity in the final stage is set to at least the same capacity as other transfer stages. ing.

  The lower structure of the drain control electrode 16 includes p regions 31 and 32 that are separated from the n-type channel 15a and the p-type surface channel 15c of the adjacent charge transfer path 15, and an n region 33 provided between the p regions 31 and 32. , And a high concentration n region 34 provided on the central surface portion of the n region 33. Then, an opening is formed in the insulating film 26 above the high concentration n region 34, and the drain control electrode film 16 connected to the high concentration n region 34 is contacted.

  By providing the drain only in the final stage as in this embodiment, the area of the storage unit 3 can be reduced, the solid-state imaging device 1 can be manufactured in a small size, and the chip unit price can be reduced.

  The drain structure shown in FIG. 5 has a structure in which control gates (portions where the drain control electrode film 16 extends above the left and right p regions 31 and 32) are provided on the left and right sides. The structure which provides a location may be sufficient.

  The material of the drain control electrode film 16 may be polysilicon, tungsten, molybdenum, or silicide thereof. Needless to say, the contact material for the high-concentration n region 34 may be separate from the control electrode film 16. Although the illustration of the light shielding film is omitted in FIG. 5, this portion is also covered with the light shielding film 28.

  Next, the operation of the FIT type solid-state imaging device according to this embodiment having the above-described configuration will be described.

  The sensor unit 2 receives incident light from the subject, and each photodiode 11 accumulates signal charges (electrons in this example) corresponding to the amount of received light. The signal charge of each photodiode 11 is read to the vertical charge transfer path 12 and transferred to the storage unit 3.

  In the example shown in FIG. 1, this transfer is performed by four-phase driving by transfer pulses V1 to V4 using a voltage of 0V to 30V. However, driving of the vertical charge transfer path 12 is not limited to four-phase driving.

  In the FIT type solid-state imaging device 1 of the present embodiment, the vertical charge transfer path 12 in the sensor unit 2 does not have a double channel structure. That is, it does not have a low dark current structure. The double channel structure has a small transfer charge capacity per unit area. Even in the case of solid-state imaging devices that have become smaller in size due to the increase in the number of pixels as in recent years, the design is made so that the accumulated charge amount is as large as possible by increasing the pixel size as much as possible, but the transfer charge capacity does not become a bottleneck. It is necessary to do so.

  Therefore, in this embodiment, the transfer charge capacity is secured without adopting the low dark current structure in the vertical charge transfer path 12 of the sensor unit 2. However, since the dark current has never been less, it is decided to transfer at high speed. The structure of the sensor unit 2 is the same as that of the interline transfer type, but the transfer rate of the vertical charge transfer path 12 of this embodiment is 10 times or more than the vertical transfer rate of the interline transfer type. When the magnification is 10 to 20 times, the dark current is reduced to 1/10 to 1/20 compared to the interline transfer type.

  The signal charge transferred at high speed to the vertical charge transfer path 15 of the storage unit 3 is transferred to the horizontal charge transfer path 4 at the transfer unit 3 at a transfer rate similar to the interline transfer type vertical transfer rate. That is, the transfer of the vertical charge transfer path 15 in the storage unit 3 is performed at a speed lower than the transfer speed of the vertical charge transfer path 12 (in the above example, a speed of 1/10 to 1/20).

  This transfer is performed by the four-phase drive of the transfer pulses S1 to S4, and the transfer voltage is a positive voltage transfer pulse not including 0V as described in FIG. For example, transfer pulses S1 to S4 of low level + 2V and high level + 8V are performed. This transfer need not be four-phase driving.

  Since the transfer on the vertical charge transfer path 15 is performed at a low speed, a dark current is generated. However, the generated dark current is transferred through the surface channel of the p-type surface layer 15c and does not enter the n-type layer 15a where the signal charge is transferred, thereby preventing the dark current from being mixed into the signal charge.

  As described above, the double channel structure has a problem that the transfer charge capacity cannot be sufficiently obtained. However, in the solid-state imaging device of this embodiment, the vertical charge transfer is performed with respect to the channel width of the vertical charge transfer path 12. Since the channel width of the path 15 can be several times, for example, 5 to 6 times, there is no transfer defect due to insufficient transfer capacity.

  When the signal charge is transferred through the buried channel of the n region 15a and the dark current is transferred through the surface channel of the p-type surface layer 15c and transferred to the final stage of the vertical charge transfer path 15 in the storage unit 3, FIG. When a voltage is applied to the drain control electrode film 16 so that a surface channel slightly deeper than the surface channel 15c of the storage portion 3 is formed on the surfaces of the p regions 31 and 32, the dark current transferred by the surface channel 15c (Electrons) flows into the drain (n region 33), which flows into the V drain terminal of FIG. 1 and is discarded outside the solid-state imaging device 1.

  The signal charge (electrons) transferred by the n-type buried channel 15b moves from the final stage of the vertical charge transfer path 15 to the horizontal charge transfer path 4, and is transferred through the horizontal charge transfer path 4, and the output amplifier 5 A voltage value signal corresponding to the amount is output as a captured image signal. Since the dark current is discarded at the final stage of the vertical charge transfer path 15, the obtained captured image signal has a very small dark current component, and a high S / N image signal is obtained.

  When a moving image is imaged using the solid-state imaging device 1, not only dark current but also smear can be greatly reduced. This is because smear charges that cause smear are trapped in the surface channel 15c of the vertical charge transfer path 15 and discarded at the drain.

  In the present embodiment, the horizontal charge transfer path 4 does not have a double channel structure. However, the horizontal charge transfer path has a double channel structure, and the dark current transferred by the surface channel of the vertical charge transfer path 15 is horizontal. It is also possible to adopt a configuration in which dark current is discarded with a drain structure that is transferred through the surface channel of the charge transfer path and provided at the final stage of the horizontal charge transfer path. However, since the horizontal charge transfer path is driven at a high speed, the dark current generated in the horizontal charge transfer path is extremely small. Therefore, as in the present embodiment, the structure for discarding the dark current at the final stage of the vertical charge transfer path 15 is used. Is preferred.

  The CCD solid-state imaging device according to the present invention is suitable for increasing the number of pixels of the CCD solid-state imaging device because S / N is improved.

It is a surface schematic diagram of the CCD solid-state image sensor concerning one embodiment of the present invention. It is the II-II sectional schematic drawing of FIG. FIG. 3 is a schematic sectional view taken along line III-III in FIG. 1. FIG. 4 is a potential diagram along line IV-IV in FIG. 3. FIG. 5 is a schematic cross-sectional view taken along line VV in FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 FIT type CCD solid-state imaging device 2 Sensor unit 3 Storage unit 4 Horizontal charge transfer path (HCCD)
5 Output amplifier 11 Photodiode (photoelectric conversion element)
12 First vertical charge transfer path (VCCD)
15 Second vertical charge transfer path (VCCD)
16 Drain control electrodes 12a, 15a n-type region (n-type layer: buried channel)
12b, 15b Transfer electrode film 15c p-type surface layer (surface channel)
26 insulating film 28 light shielding film 33 n region (drain)

Claims (7)

  A sensor unit having a plurality of photoelectric conversion elements and a plurality of first vertical charge transfer paths arranged in a two-dimensional array, a horizontal charge transfer path, and provided between the horizontal charge transfer path and the sensor unit. In a frame interline transfer type CCD solid-state imaging device comprising a storage unit having a plurality of second vertical charge transfer paths that are continuous with the first vertical charge transfer path, the structure of the first vertical charge transfer path is A CCD solid-state imaging device, wherein the second vertical charge transfer path has a low dark current structure.   2. The CCD solid-state imaging device according to claim 1, wherein a transfer speed of the first vertical charge transfer path is controlled to be 10 times or more and 20 times or less of a transfer speed of the second vertical charge transfer path.   3. The CCD solid-state imaging device according to claim 1, wherein the second vertical charge transfer path is wider than the first vertical charge transfer path. 4.   The low dark current structure is a dual channel structure having a buried channel for transferring a signal charge detected by the photoelectric conversion element and a surface channel formed on the buried channel for transferring dark current. The CCD solid-state imaging device according to any one of claims 1 to 3.   The charge transfer in the second vertical charge transfer path in which the buried channel is formed by an n-type region and the surface channel is formed by a p-type region is performed by a transfer pulse formed only by a plus voltage. Item 5. A CCD solid-state imaging device according to Item 4.   6. The CCD according to claim 4, wherein a drain for discarding the dark current of the surface channel is provided at a final stage position connected to the horizontal charge transfer path of the second vertical charge transfer path. Solid-state image sensor.   7. The CCD solid-state image pickup device according to claim 6, wherein the length of the final stage is increased by the amount by which the width of the second vertical charge transfer path at the final stage position where the drain is provided is reduced.

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