JP4742523B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

  The present invention relates to a solid-state imaging device and a driving method thereof.

  In general, in a CMOS image sensor, two to four wiring layers are provided depending on the number of signals and drive signals (see, for example, Patent Document 1).

As an example of a general CMOS image sensor, a circuit configuration diagram of a main part of a CMOS sensor having a three-transistor pixel cell is shown in FIG.
In the CMOS image sensor 50, one pixel cell 51 includes a PD (photodiode) that performs light reception / photoelectric conversion, a read transistor 52 that reads signal charges from the PD, and a reset transistor that resets the PD to the power supply potential prior to light reception / storage. 53, an amplifying transistor 54 for converting the current into a signal corresponding to the read signal charge, a vertical signal line 55 for reading the signal current, a selection power line 56 for transmitting the power and drive signals, a read selection line 57, and a reset line 58. ing.
A sample and hold circuit 59 and a load transistor 60 are connected to one end side of the vertical signal line 55. The sample and hold circuit 59 has a horizontal selection line 61 connected to the input side and a buffer amplifier 62 connected to the output side.

The CMOS image sensor 50 operates as follows.
By applying a power supply voltage Vd to the selected power supply line 56 and giving a high level signal to the read selection line 57 and the reset line 58, the read transistor 52 and the reset transistor 53 are turned on, and the photodiode PD is set to the Vd potential. Reset.
Next, by setting the read selection line 57 and the reset line 58 to a low level, the read transistor 52 and the reset transistor 53 are turned off, and the photodiode PD enters a floating state, and photoelectric conversion is performed according to the amount of light incident on the photodiode PD. The accumulated electrons are accumulated in the photodiode PD, and the potential of the photodiode PD becomes lower than Vd.
After the accumulation period ends, the read selection line 57 and the selection power supply line 56 are set to a high level, whereby a signal charge corresponding to the amount of light accumulated in the photodiode PD is applied to the gate of the amplification transistor 54, and according to the amount of light. A current flows to the load transistor 60 through the vertical signal line 55. The potential of the vertical signal line 55 is stored by the sample and hold circuit 59, and a signal is output for each column by the horizontal selection line 61, whereby the pixel signal is output as the signal output 63 through the buffer amplifier 62. .

FIG. 9 shows a cross-sectional structure of a conventional CMOS image sensor corresponding to this circuit configuration.
For example, a trench element isolation layer 67 that electrically isolates transistors and photodiodes PD is formed on a p-type silicon substrate 66, and between the trench element isolation layers 67 near the surface of the silicon substrate 66, the photodiodes PD and transistors are separated. Regions such as source and drain are formed.
Further, a plug layer 70 penetrating through the first insulating layer 69 covering the gate electrode 68 is connected to the gate electrode of the reading transistor 52 and the source or drain region of the transistor, and the plug layer 70 is formed on the insulating layer 69. Are connected to a first wiring layer (electrode layer) 71. Also, a part of the first wiring layer (electrode layer) 71 is connected to a plug layer 73 that penetrates the second insulating layer 72 covering the first wiring layer 71. The second wiring layer (electrode layer) 74 formed on the insulating layer 72 is connected. Each of the plug layers 70 and 73 has a two-layer structure of thin films 70A and 73A covering the outer wall and bottom surface of the contact hole and thick layers 70B and 73B therein.
For the first and second wiring layers (electrode layers) 71 and 74, for example, a metal such as aluminum or copper can be used as an electrode material.

The trench isolation layer 67 is formed by, for example, etching a trench (trench) in the silicon substrate 66 by etching and forming an insulating layer such as an oxide film so as to fill the trench, and then planarizing the surface by etching or CMP. It can be formed by removing the insulating layer remaining on the surface.
The plug layers 70 and 73 have, for example, a contact hole formed in the insulating layers 69 and 72 by etching, an electrode material such as tungsten W is formed so as to fill the contact hole, and the surface is flattened by etching or CMP. Can be formed.
As the wiring layer, necessary wiring layers (generally, two to four layers) are formed according to the number of signals transmitted by wiring such as an imaging signal and a driving signal.

However, in the cross-sectional structure described above, four or five wirings including the vertical signal line 55, the selection power supply line 56, the reading selection line 57, the reset line 58, and the ground line for applying a ground potential as necessary are provided on the silicon substrate. It must be formed not by the vicinity of 66 but by the upper wiring layers 71 and 74.
For this reason, a wide wiring space is required in the upper layer.

In a portion of the wiring layers 71 and 74, since light is incident on the wiring layers 71 and 74 and does not enter the silicon substrate 66, the area of the PD is constrained by that amount in order to secure a wide wiring space. End up.
Furthermore, it is necessary to dispose the trench element isolation layer 67, the read transistor 56, the reset transistor 66, and the amplification transistor 68 on the surface of the substrate 66.
Therefore, the area of the photodiode PD is restricted in order to secure a space for these wirings and circuit components.
Therefore, in the CMOS sensor, the area of the photodiode PD generally remains at 30% or less of the pixel cell area.

  If the area of the photodiode PD is reduced, the amount of charge that can be accumulated is reduced, and the sensitivity is lowered because the area on which light is incident is reduced. For this reason, there arises a problem that optical characteristics and electrical characteristics, which are important as basic characteristics of the image sensor, are deteriorated.

As an improvement measure, a back-illuminated image sensor in which light is incident from the back side of the substrate opposite to the front side on which the wiring layer is formed has been proposed, and has already been put into practical use for special applications (Patent Document 2). Or refer to Patent Document 3). In the proposed back-illuminated image sensor, the silicon substrate in the pixel portion is thinned to a thickness of several μm to several tens of μm by etching or the like.
Japanese Patent Laying-Open No. 2003-31785 (FIG. 9) JP-A-6-77461 (FIG. 3) JP-A-6-283702 (FIG. 2)

Here, FIG. 10 shows a schematic sectional view of a configuration in which the back-illuminated image sensor is applied to a CMOS image sensor.
As shown in FIG. 10, in contrast to the configuration of the conventional CMOS image sensor shown in FIG. 9, that is, the front-illuminated CMOS image sensor, an n ⁻ diffusion layer 82 that constitutes a photodiode is provided inside a silicon substrate 66 The diffusion layer 82 is continuously formed up to the surface side of the substrate 66, and the n ⁻ diffusion layer 82 is formed near the interface on the surface side of the substrate 66 through the n-type diffusion region 83. The storage diffusion layer 84 is connected.
Further, in order to prevent the signal electrons photoelectrically converted inside the substrate 66 from leaking into the photodiode of the adjacent pixel, the photodiode is separated for each pixel by the p-type element isolation diffusion layer 81.

Here, FIG. 11 shows a potential distribution in the AA ′ cross section of the CMOS image sensor shown in FIG.
Since the diffusion layer 82 of the photodiode is not formed to the vicinity of the interface on the back surface side of the substrate 66, the potential distribution becomes as shown by the solid line in FIG. 11, and the depletion layer does not reach the interface on the back surface side of the substrate 66. .
Thereby, the dark current component generated at the interface on the back surface side of the substrate 66 is rarely mixed as a signal.

By the way, also in such a back-illuminated image sensor, it is required to make the pixel cells finer in order to increase the number of pixels and reduce the size.
However, in the CMOS image sensor, since it is necessary to form a transistor for each pixel, a large number of transistors are formed on the substrate surface.
For this reason, it is difficult to miniaturize the pixel cell.

Even in the configuration shown in FIG. 10, a certain amount of dark current may actually be mixed due to the diffusion of impurities into the substrate 66 or the like.
Furthermore, in the configuration of FIG. 10, since there is no depletion layer in the vicinity of the interface on the back surface side of the substrate 66, the charge photoelectrically converted in the vicinity of the interface on the back surface side is recombined before entering the diffusion layer 82 of the photodiode. May end up.
In such a case, the sensitivity is significantly reduced with respect to light having a short wavelength that is difficult to enter the back of the substrate 66.

On the other hand, when the diffusion layer (semiconductor region) 82 of the photodiode shown in FIG. 10 is formed up to the interface on the back surface side of the substrate 66, the back surface side of the substrate 66 as shown in the potential distribution shown by the chain line in FIG. Since the depletion layer is formed up to the vicinity of the interface, it is possible to suppress a decrease in sensitivity that was noticeable with short-wavelength light.
However, in this configuration, dark currents generated by many interface states existing at the interface on the back surface side of the substrate 66 may be mixed into the signal charge and cause deterioration in image quality.

  Therefore, compared with the configuration shown in FIG. 10, a configuration of a solid-state imaging device that can further reduce the dark current from the interface on the back surface side is desired.

  The present invention provides a solid-state imaging device having good sensitivity, good optical characteristics and electrical characteristics, and capable of easily miniaturizing a pixel cell, and a driving method thereof.

The solid-state imaging device according to the present invention includes a second conductive type semiconductor layer in which a light receiving portion that performs photoelectric conversion is formed, a second conductive type element isolation diffusion layer for separating each pixel, and a semiconductor layer. At least a wiring layer formed on the front surface side, and has a structure in which light is incident from the back surface side opposite to the front surface side of the semiconductor layer, and from the region of the first conductivity type constituting the light receiving portion, A read transistor for selectively reading signal charges to the pixel formation circuit formed on the front surface side is formed inside the semiconductor layer, and the first conductivity type region constituting the light receiving portion is formed from the back surface side of the semiconductor layer. The first conductivity type diffusion layer, the second first conductivity type diffusion layer, and the third first conductivity type diffusion layer are separated, and the first conductivity type impurity concentration is 1 first conductivity type diffusion layer <second first conductivity type diffusion layer <third first conductivity type extension It has a layer, embedded in the semiconductor layer, a second conductivity type region formed parallel to the plane of the semiconductor layer constitutes the gate of the read transistor, the region of the second conductivity type, The pixel cell is connected to the second conductivity type element isolation diffusion layer at the outer edge of the pixel cell.

The solid-state imaging device driving method of the present invention includes a second conductivity type semiconductor layer in which a light receiving portion where photoelectric conversion is performed, a second conductivity type element isolation diffusion layer for separating each pixel, At least a wiring layer formed on the front surface side of the semiconductor layer, and has a structure in which light is incident from the back surface side opposite to the front surface side of the semiconductor layer, and from the first conductivity type region constituting the light receiving portion A read transistor for selectively reading signal charges to a pixel formation circuit formed on the surface side of the semiconductor layer is formed inside the semiconductor layer, and the first conductivity type region constituting the light receiving portion is formed on the semiconductor layer. The first conductivity type diffusion layer, the second first conductivity type diffusion layer, and the third first conductivity type diffusion layer are separated from the back surface side, and the first conductivity type impurity concentration is divided. The first first conductivity type diffusion layer <the second first conductivity type diffusion layer <the third first Has a conductivity type of the diffusion layer, is embedded in the semiconductor layer, a second conductivity type region formed parallel to the plane of the semiconductor layer constitutes the gate of the read transistor, the second conductivity type When the readout transistor is simultaneously turned on in all the pixels for the solid-state imaging device connected to the element isolation diffusion layer of the second conductivity type at the outer edge of the pixel cell, the light receiving / accumulating period of all the pixels Are aligned.

According to the configuration of the above-described solid-state imaging device of the present invention, the semiconductor layer includes at least a semiconductor layer in which a light receiving portion where photoelectric conversion is performed and a wiring layer formed on the surface side of the semiconductor layer. Since it has a structure that allows light to enter from the back side opposite to the front side, light is not shattered by the wiring layer, etc., and it is possible to increase the amount of light incident on the light receiving part, and a transistor is formed. The photodiode of the light receiving portion can be formed not at the surface side of the semiconductor layer, but at a deep position inside the semiconductor layer, and a large area of the photodiode can be ensured. As a result, the amount of charge that can be accumulated in the photodiode can be increased, and the sensitivity can be improved.
Further, a readout transistor for selectively reading out signal charges from the first conductivity type region constituting the light receiving portion to the pixel formation circuit formed on the surface side of the semiconductor layer is formed in the semiconductor layer. Accordingly, the number of transistors and the number of wirings formed on the surface side of the semiconductor layer can be reduced as compared with a structure in which the reading transistor is formed on the surface of the semiconductor layer.

  According to the above-described solid-state image sensor driving method of the present invention, the pixels are arranged in order to align the light receiving / accumulating periods of all the pixels by simultaneously turning on the readout transistors for all the pixels in the solid-state image sensor of the present invention. The accumulation time does not differ for each row, and the accumulation period of all the pixels can be set to the synchronization period.

In the solid-state imaging device of the present invention, the second conductivity type region may be formed in common for all pixels arranged in a matrix.
In this configuration, a high-level voltage is applied to the second conductivity type region that is commonly formed in all the pixels to turn on the readout transistors, thereby simultaneously turning on the readout transistors in all the pixels. Can be. This makes it possible to align the light reception / accumulation periods of all pixels.

In the solid-state imaging device of the present invention , the second conductivity type region may be formed at the interface of the semiconductor layer on the back surface side with respect to the first conductivity type region constituting the light receiving unit. it can.
In this configuration, the second conductivity type region suppresses the arrival of the depletion layer of the light receiving unit to the back side interface and suppresses the generation of dark current due to the interface state existing near the back side interface. Therefore, generation of dark current in the vicinity of the interface of the semiconductor layer on the back surface side can be reduced.

Also be a configuration that is formed in common in all the pixels Oite the driving method, a region of the second conductivity type are arranged in a matrix of solid-state imaging device of the present invention.
In this configuration, by applying a high level voltage to the second conductivity type region that is commonly formed in all pixels, the readout transistors are simultaneously turned on in all the pixels, and light reception / storage in all the pixels is performed. It becomes possible to arrange the period.

According to the present invention described above, since the number of transistors and wirings formed on the front surface side can be reduced by forming the read transistor and the read selection line inside the substrate, the pixel cell can be easily miniaturized. .
In addition, by having a structure in which light is incident from the back surface side, it is possible to increase the amount of charge that can be accumulated in the photodiode and to improve sensitivity.
Therefore, it is possible to realize a solid-state imaging device having a good sensitivity, excellent optical characteristics and electrical characteristics, and a structure in which pixel cells can be easily miniaturized.

In particular, when the second conductivity type region is formed in common for all the pixels arranged in a matrix, the light receiving and accumulation periods of all the pixels arranged in a matrix are aligned, With this, it becomes possible to perform imaging.

In particular, when the second conductivity type region is formed at the interface of the semiconductor layer on the back surface side with respect to the first conductivity type region constituting the light receiving portion, the interface of the semiconductor layer on the back surface side. Since the generation of dark current in the vicinity can be reduced, it is possible to achieve both low dark current and high sensitivity.

FIG. 1 shows a schematic configuration diagram (cross-sectional view) of a solid-state imaging device as one embodiment of the present invention. The cross-sectional view of FIG. 1 shows almost one pixel cell.
In the present embodiment, the present invention is applied to a back-illuminated CMOS sensor (CMOS solid-state imaging device).

  As shown in FIG. 1, for example, a trench element isolation layer 5 for electrically isolating transistors and photodiodes PD is formed on a p-type silicon substrate 1, and between the element isolation layers 5 near the surface of the silicon substrate 1. Regions such as the n-type accumulation diffusion layer 4 constituting the photodiode and the source / drain of the transistor are formed.

The photodiode is composed of an n ⁻ diffusion layer 3 on the back surface side, an n-type accumulation diffusion layer 4 on the front surface side, and an n-type diffusion layer 3A between them. The n-type diffusion layer 3 < ^/ b> A is formed in a smaller area than the n ⁻ diffusion layer 3.
In each of the photodiode layers 3, 3 A, 4, the n-type impurity concentration is set so that the back surface n ⁻ diffusion layer 3 <intermediate n-type in order to form a potential distribution (see FIG. 2) described later. The diffusion layer 3A <the surface n-type accumulation diffusion layer 4 is assumed.
Further, in order to prevent the signal electrons photoelectrically converted inside the substrate 1 from leaking into the photodiode of the adjacent pixel, the p-type element isolation diffusion layer 2 separates the photodiode for each pixel.

A plug layer 9 penetrating the first insulating layer 8 covering the gate electrode 7 is connected to the gate electrode 7 of the transistor and the source or drain region of the transistor. The plug layer 9 is connected to a first wiring layer (electrode layer) 10 formed on the insulating layer 8.
A plug layer 12 penetrating a second insulating layer 11 covering the first wiring layer 10 is connected to a part of the first wiring layer (electrode layer) 10. The plug layer 12 is connected to a second wiring layer (electrode layer) 13 formed on the insulating layer 11.
The second wiring layer (electrode layer) 13 is covered with an insulating layer 14.
The plug layers 9 and 12 have a two-layer structure of thin films 9A and 12A that cover the outer wall and bottom surface of the contact hole, respectively, and thick layers 9B and 12B inside thereof.
Furthermore, if necessary, components such as a color filter and an on-chip lens are provided on the upper layer to form a solid-state imaging device.

In the present embodiment, a p ⁺ diffusion layer 16 is added to the interface on the back surface side of the substrate 1 with respect to the structure of the conventional back-illuminated CMOS image sensor shown in FIG.
Since this p ⁺ diffusion layer 16 functions as a hole accumulation layer, holes generated near the interface on the back surface side of the substrate 1 can be accumulated.
The p ⁺ diffusion layer 16 is preferably formed to a thickness of 0.2 μm or less.
The p ⁺ diffusion layer 16 is set to the ground potential (ground potential).

By adding this p ⁺ diffusion layer 16, it is possible to suppress the depletion layer due to the photodiode from reaching the back side interface of the substrate 1, and to keep the hole concentration at the back side interface high. Since it becomes possible, generation | occurrence | production of the dark current resulting from the interface state which exists in the interface vicinity of the back surface side of the board | substrate 1 can be suppressed.

In the present embodiment, the p ⁺ buried diffusion layer 15A and the surrounding p are formed in the silicon substrate 1 between the n ⁻ diffusion layer 3 of the photodiode formed on the back surface side and the accumulation diffusion layer 4 on the front surface side. ^- forming a buried diffusion layer 15B, and forms of these buried diffusion layer 15 (15A, 15B) static induction transistor with a gate electrode.
This electrostatic induction transistor functions as a read transistor, so that the signal charge accumulated in the n ⁻ diffusion layer 3 of the photodiode formed on the back surface side flows into the storage diffusion layer 4 formed on the front surface side. Can be controlled.

The buried diffusion layer 15 is formed substantially parallel to the substrate surface, and is connected to the p-type element isolation diffusion layer 2 at the outer edge of the pixel cell.
Further, since the buried diffusion layer 15 is formed in common for pixels in each row as will be described later (see FIG. 4), the buried diffusion layer 15 is not shown in the sectional view of FIG. The buried diffusion layers 15 of adjacent pixel cells are connected.

As a configuration for applying a voltage to the buried diffusion layer 15, for example, p is connected to the portion outside the imaging region of the buried diffusion layer 15 formed for each row of pixels with a low resistance to the surface side. ^{A configuration in which a +} layer is formed, an electrode is formed on the surface side, and contact with the wiring is taken into consideration.
Further, for example, in some areas of the rear surface side interface, instead of forming the p ⁺ diffusion layer 16, with forming a p ⁺ layer for electrode extraction, to form an electrode connected thereto, the p ⁺ A configuration in which the layer is connected to the buried diffusion layer 15 through the element isolation diffusion layer 2 is also conceivable.

  The structure of the pixel cell shown in FIG. 1 can be manufactured by repeating the formation of a selective diffusion layer by a combination of photolithography and ion implantation and the epitaxial growth on the silicon substrate 1.

  Furthermore, FIG. 2 shows both the potential distribution of the AA ′ section and the potential distribution of the BB ′ section of FIG. 1, and FIG. 3 shows a circuit configuration diagram of the solid-state imaging device of FIG.

The circuit configuration diagram shown in FIG. 3 is the same as the circuit configuration diagram of the CMOS image sensor 50 shown in FIG.
That is, one pixel cell 30 receives light and photoelectric conversion PD (photodiode), read transistor 6 that reads signal charges from the photodiode PD, and reset transistor 17 that resets the photodiode PD to the power supply potential prior to light reception and accumulation. , An amplifying transistor 18 for converting the current into a signal corresponding to the read signal charge, a vertical signal line 19 for reading the signal current, a selection power line 22 for transmitting a power source and a drive signal, a read selection line 21 and a reset line 20. Yes.
A sample and hold circuit 25 and a load transistor 24 are connected to one end of the vertical signal line 19. The sample and hold circuit 25 has a horizontal selection line 28 connected to the input side and a buffer amplifier 26 connected to the output side.

The n ⁻ diffusion layer 3 of the photodiode is connected to the read transistor 6. As described above, the read transistor 6 uses the buried diffusion layer 15 as a gate electrode.
The n-type storage diffusion layer 4 is connected to one end of the read transistor 6 and the reset transistor 17 and the gate of the amplification transistor 18.

  Next, the operation of the solid-state imaging device of the present embodiment will be described with reference to the potential diagram of FIG. 2 and FIG.

First, during the accumulation period, the buried diffusion layer 15 is set to a low voltage state (low level state).
At this time, the potential distribution in the AA ′ section in FIG. 1 is as shown by the solid line in FIG. 2, and the potential distribution in the BB ′ section is as shown in the broken line in FIG. .
Therefore, the n ⁻ diffusion layer 3 of the photodiode is depleted, and light incident from the back side of the substrate 1 is photoelectrically converted in this region. The generated electrons are accumulated in the portion C of FIG. 2 in the photodiode.

Next, when reading the accumulated electrons, the buried diffusion layer 15 is set to a high voltage state (high level state). As a result, the potential distribution in the AA ′ section changes as indicated by the chain line in FIG. 2, and electrons corresponding to the amount of incident light accumulated in the C portion flow into the D portion, that is, the accumulation diffusion layer 4. .
As shown in the circuit configuration diagram of FIG. 3, the storage diffusion layer 4 is connected to the gate electrode of the amplification transistor 18 in the pixel cell 30 and is stored by applying a power supply voltage to the selected power supply line 22. A current controlled by the amplification transistor 18 flows to the load transistor 24 through the vertical signal line 19 in accordance with the amount of charge, and a potential corresponding to the signal charge is generated on the vertical signal line 19.
The higher the amount of incident light and the more accumulated charge, the lower the potential of the vertical signal line 19. This potential signal can be output as a signal output 27 through the sample and hold circuit 25 and the buffer amplifier 26.

The buried diffusion layer 15 in the structure of FIG. 1 corresponds to a portion in the pixel cell 30 of the read selection line 21 in the circuit configuration diagram of FIG. Therefore, it is necessary to form wirings separated for each row.
That is, as shown in the plan view of FIG. 4, the buried diffusion layer 15 is formed in common with the pixel cells 30 for each row.

  According to the above-described embodiment, the hole accumulation layer 16 is formed at the interface (back side) opposite to the front surface side where the wiring layers 10 and 13 of the substrate 1 are formed. The layer 16 can suppress dark current caused by interface states generated near the interface on the back surface side of the substrate 1.

Further, according to the present embodiment, the p-type buried diffusion layer 15 formed inside the substrate 1 sends a signal to the pixel formation circuit (storage diffusion layer 4 and the transistor in the pixel cell) formed on the surface side. Since the gate of the read transistor 6 for selectively reading out charges is configured, the read transistor 6 and the read selection line 21 are formed inside the silicon substrate 1.
As a result, the number of transistors and the number of wirings formed on the surface side of the substrate 1 can be reduced, so that the pixel cell 30 can be easily miniaturized.

And by having a backside illumination type structure, it is possible to increase the amount of light incident on the photodiode without being scattered by the wiring layer or the like, and at the front side of the substrate 1 on which the transistor is formed Since the photodiode is formed not in the vicinity of the interface, but in a deep position inside the substrate 1, a large area of the photodiode can be secured.
As a result, the amount of charge that can be accumulated in the photodiode can be increased, and the sensitivity can be improved.

  Therefore, according to the configuration of the solid-state imaging device of the present embodiment, both low dark current and high sensitivity can be achieved.

Furthermore, FIG. 5 shows a schematic cross-sectional view of a CMOS image sensor as another embodiment of the present invention. FIG. 6 shows a circuit configuration diagram of a pixel cell portion of the CMOS image sensor shown in FIG.
In FIG. 6, the portions other than the pixel cell are the same as those in the circuit configuration of the previous embodiment shown in FIG.

In the configuration of the conventional CMOS image sensor, since the reading operation is performed for each row, the accumulation period is different for each row of the pixel cells arranged in a two-dimensional array, and there is a focal plane operation having no synchronism on the two-dimensional screen. Had the disadvantage of becoming.
The present embodiment further improves this defect and realizes a simultaneous accumulation period in the entire two-dimensional screen as in the case of a CCD image sensor (CCD solid-state imaging device).

In this embodiment, in particular, as shown in the circuit configuration diagram of FIG. 6, a transfer transistor 29 is added to the conventional circuit configuration.
The transfer transistor 29 has its gate connected to the transfer selection line 23, one of its source / drain connected to the storage diffusion layer 4, and the other connected to the gate of the amplification transistor 18.

Furthermore, the embedded transfer electrode diffusion layer 15 of FIG. 5 (corresponding to the read selection line 21 in the pixel cell unit circuit of FIG. 6) is entirely arranged in a two-dimensional array as shown in a plan view of FIG. Form in common.
Thereby, the accumulation period can be made uniform in the whole pixel cell 31 arranged in a two-dimensional array.

  5 and 6, the other configurations are the same as those in the previous embodiment, and thus the same reference numerals are given and redundant description is omitted.

The solid-state image sensor according to the present embodiment operates as follows.
First, during the accumulation period, by setting the buried diffusion layer 15 in a low voltage state (low level state), the n ⁻ diffusion layer 3 of the photodiode is depleted, and light incident from the back side of the substrate 1 Photoelectric conversion is performed in the region. The generated electrons are accumulated in the n ⁻ diffusion layer 3 of the photodiode.

Next, in order to read out electric charges (electrons) accumulated in the n ⁻ diffusion layer 3 of the photodiode, the buried diffusion layer 15 is set to a high voltage state (high level state). Thereby, in the entire pixels arranged in the two-dimensional array, an amount of electrons corresponding to the amount of incident light accumulated in the n ⁻ diffusion layer 3 of the photodiode passes through the n-type diffusion layer 3A. Flow into.

Thereafter, the buried diffusion layer 15 is set to a low voltage state (low level state), whereby the next accumulation operation is started in the photodiode.
The signal charge stored in the storage diffusion layer 4 is connected to the gate electrode of the amplifying transistor 18 by turning on the transfer transistor 29 for each row when the transfer selection line 23 becomes a high level state for each row. By applying a power supply voltage to the line 22, a current controlled by the amplification transistor 18 flows to the load transistor 24 through the vertical signal line 19 in accordance with the accumulated charge amount, and the potential corresponding to the signal charge is a vertical signal. It occurs on line 19.

  As described above, in the present embodiment, the accumulation period of the electrons photoelectrically converted according to the incident light can be synchronized with the entire pixel cell 31 arranged in a two-dimensional array. Similarly, it is possible to perform imaging while maintaining simultaneity.

According to the above-described embodiment, the interface states generated near the interface on the back surface side of the substrate 1 by the hole accumulation layer 16 formed on the interface on the back surface side of the substrate 1 as in the previous embodiment. It is possible to suppress the dark current caused by.
Similarly to the previous embodiment, the gate of the read transistor 6 is constituted by the p-type buried diffusion layer 15 formed inside the substrate 1, and the number of transistors and wirings formed on the surface side of the substrate 1. Therefore, the pixel cell 30 can be easily miniaturized.
In addition, by having a back-illuminated structure, it is possible to secure a large area of the photodiode, increase the amount of charge that can be accumulated in the photodiode, and improve sensitivity.

Further, according to the present embodiment, in particular, the transfer transistor 29 is provided and the buried diffusion layer 15 is formed in common for the pixel cells 31 arranged in a two-dimensional array, so that the charge (electron) accumulation time is reduced to 2 The entire pixel cells 31 arranged in a dimensional array can be synchronized.
Thereby, it is possible to perform imaging while maintaining simultaneity.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (a cross-sectional view of one pixel cell) of a CMOS image sensor according to an embodiment of the present invention. It is a potential distribution map in AA 'and BB' of FIG. It is a circuit block diagram of the CMOS image sensor of FIG. FIG. 2 is a schematic plan view showing the entire two-dimensional array of the CMOS image sensor of FIG. 1. It is a schematic block diagram (sectional drawing for one pixel cell) of the CMOS image sensor of other embodiment of this invention. It is a circuit block diagram of the CMS image sensor of FIG. FIG. 6 is a schematic plan view showing the entire two-dimensional array of the CMOS image sensor of FIG. 5. It is a circuit block diagram of the principal part of the CMOS sensor which has a 3 transistor type pixel cell. It is a figure which shows the cross-section of the conventional CMOS image sensor corresponding to the circuit structure of FIG. It is a schematic sectional drawing of the structure which applied the back irradiation type image sensor to the CMOS image sensor. FIG. 11 is a potential distribution diagram along AA ′ in FIG. 10.

Explanation of symbols

1 substrate, 2 the element isolation diffusion layer, 3 n ^- diffusion layer, 3A n-type diffusion layer, 4 storage diffusion layer, 5 a trench isolation layer, 6 a read transistor, 7 gate electrode, 8, 11, 14 insulating layer, 9, 12 plug layers, 10 and 13 wiring layers, 15 buried diffusion layers, 16 hole storage layers, 17 reset transistors, 18 amplification transistors, 19 vertical signal lines, 20 reset lines, 21 readout selection lines, 22 selection power supply lines, 23 transfer selections Line, 24 load transistor, 25 sample and hold circuit, 27 signal output, 28 horizontal selection line, 29 transfer transistor, 30, 31 pixel cell

Claims (6)

A second-conductivity-type semiconductor layer in which a light-receiving portion that performs photoelectric conversion is formed;
A second conductivity type element isolation diffusion layer for isolation for each pixel;
And at least a wiring layer formed on the surface side of the semiconductor layer,
Having a structure in which light is incident from the back side opposite to the front side of the semiconductor layer;
A readout transistor for selectively reading out signal charges from a first conductivity type region constituting the light receiving portion to a pixel formation circuit formed on the surface side of the semiconductor layer is formed inside the semiconductor layer,
The region of the first conductivity type constituting the light receiving portion is formed from the back side of the semiconductor layer by a first first conductivity type diffusion layer, a second first conductivity type diffusion layer, and a third third type. The first conductivity type diffusion layer is divided into one conductivity type diffusion layer, and the first conductivity type diffusion layer <the second first conductivity type diffusion layer <the third first. It is a conductive diffusion layer,
A second conductivity type region embedded in the semiconductor layer and formed in parallel to the surface of the semiconductor layer constitutes the gate of the read transistor,
The solid-state imaging device, wherein the second conductivity type region is connected to the second conductivity type element isolation diffusion layer at an outer edge portion of the pixel cell.   2. The solid-state imaging device according to claim 1, wherein pixels are arranged in a matrix and the second conductivity type region is formed in common in the pixels of each row.   2. The solid-state imaging device according to claim 1, wherein pixels are arranged in a matrix, and the second conductivity type regions are formed in common in all the pixels arranged in a matrix. The second conductivity type region is formed at an interface of the semiconductor layer on the back surface side with respect to the first conductivity type region constituting the light receiving portion. The solid-state imaging device described. A second-conductivity-type semiconductor layer in which a light-receiving portion that performs photoelectric conversion is formed;
A second conductivity type element isolation diffusion layer for isolation for each pixel;
And at least a wiring layer formed on the surface side of the semiconductor layer,
Having a structure in which light is incident from the back side opposite to the front side of the semiconductor layer;
A readout transistor for selectively reading out signal charges from a first conductivity type region constituting the light receiving portion to a pixel formation circuit formed on the surface side of the semiconductor layer is formed inside the semiconductor layer,
The region of the first conductivity type constituting the light receiving portion is formed from the back side of the semiconductor layer by a first first conductivity type diffusion layer, a second first conductivity type diffusion layer, and a third third type. The first conductivity type diffusion layer is divided into one conductivity type diffusion layer, and the first conductivity type diffusion layer <the second first conductivity type diffusion layer <the third first. It is a conductive diffusion layer,
A second conductivity type region embedded in the semiconductor layer and formed in parallel to the surface of the semiconductor layer constitutes the gate of the read transistor,
For the solid-state imaging device in which the second conductivity type region is connected to the second conductivity type element isolation diffusion layer at the outer edge of the pixel cell.
A method for driving a solid-state imaging device, wherein the light receiving and accumulation periods of all the pixels are aligned by simultaneously turning on the readout transistors in all the pixels.   The solid-state imaging device driving method according to claim 5, wherein the second conductivity type region is formed in common for all pixels arranged in a matrix.

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