JP2011040536A - Solid-state image pickup element, and method for driving same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a backside illuminated solid-state imaging element which has a back surface as a receiving surface for incident light from forming an afterimage, causing crosstalk and so on. <P>SOLUTION: In a semiconductor substrate 10, a P-type light receiving top surface layer 12, an N-type photodiode 11 in which photoelectrically converted signal charges are stored, a P-type potential barrier layer 14, and an N-type charge storage layer 13 in which the signal charges transferred from the photodiode 11 are stored are provided in order from the back surface to the top surface. The light receiving top surface layer 12 is applied with a voltage of 0V by a back surface bias generating circuit 7 except when the signal charges are transferred from the photodiode 11 to the charge storage layer 13, and applied with a negative pulse signal when the signal charges are transferred. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a driving method thereof.

  Solid-state image sensors such as CCD image sensors and CMOS image sensors are widely used as solid-state image sensors for video cameras and digital still cameras. These solid-state imaging devices have unit cells arranged in a two-dimensional manner, but the unit cell size generally tends to be reduced in order to increase the resolution of the captured image or to reduce the size of the solid-state imaging device. The unit cell of the solid-state imaging device includes a photodiode that is a photoelectric conversion element, a signal readout circuit that reads out signal charges accumulated in the photodiode, and the like.

2. Description of the Related Art Conventional solid-state image sensors for video cameras and digital still cameras are so-called surface-illuminated solid-state image sensors in which devices such as photodiodes and signal readout circuits are formed on one surface of a semiconductor substrate and this device formation surface is used as a light-receiving surface Was the mainstream.
However, in recent years, in order to avoid the adverse effect of reducing the opening area (aperture ratio) of the photodiode with respect to the unit cell size due to the reduction of the unit cell, a so-called back surface in which the surface opposite to the device formation surface is the light receiving surface Irradiation-type solid-state imaging devices are beginning to be put into practical use.

FIG. 12 is a cross-sectional view showing the structure of a unit cell in a conventional back-illuminated solid-state imaging device (FIG. 1 of Patent Document 1).
As shown in the figure, a wiring layer is provided on the first surface (upper surface in the figure) of the semiconductor substrate 101, and transfer that becomes a signal readout circuit for each pixel on the side close to the first surface in the semiconductor substrate 101. A MOS transistor 110 and a signal charge transfer path 111 are provided, and a second surface (the lower side in the figure) opposite to the first surface is used as a light receiving surface, and a photo is formed on the side close to the second surface in the semiconductor substrate 101. A diode N layer 102 and a photodiode P layer 103 are provided. Adjacent pixels are partitioned by a P-type separation region 104.

  In this patent document 1, when reading the signal charge accumulated in the photodiode N layer 102, a positive voltage is applied to the control electrode 112 of the transfer MOS transistor 110 to turn on the transfer MOS transistor 110. The signal charge is transferred from the photodiode N layer 102 corresponding to the source of the transfer MOS transistor 110 to the diffusion floating region 113 corresponding to the drain.

  Further, in Patent Document 2, in a back-illuminated solid-state imaging device, photoelectrons incident from the light receiving surface are arranged on the light receiving surface side in order to guide the photoelectric electrons to a photoelectric conversion region provided on the opposite surface side of the light receiving surface. A technique for generating an electric field in the depth direction of a semiconductor substrate by applying a voltage to an electrode is disclosed.

JP-A-2005-150521 JP 2003-338615 A

However, the configuration of the solid-state imaging device of Patent Document 1 has a problem that so-called afterimages, random noise, and crosstalk occur.
That is, in order to accumulate more of the photoelectrically converted signal charge in the photodiode N layer 102, the potential well of the photodiode N layer 102 may be deepened. To deepen the potential well, the photodiode N layer The N-type impurity concentration of 102 may be increased.

  However, if the potential well is deepened by increasing the impurity concentration and the potential of the photodiode N layer 102 is raised to the same level as or higher than that of the same N-type signal charge transfer path 111, the photodiode N It becomes difficult for the signal charge accumulated in the layer 102 to be guided to the signal charge transfer path 111. Further, the width of the signal charge transfer path 111 is extremely narrow with respect to the photodiode N layer 102, and the signal charge hardly enters the signal charge transfer path 111.

Therefore, even if the transfer MOS transistor 110 is turned on, all the signal charges accumulated in the photodiode N layer 102 during the ON period can be transferred to the diffusion floating region 113 through the signal charge transmission path 111. Accordingly, a certain amount of signal charge remains in the photodiode N layer 102, which generates afterimages and random noise.
In order to prevent such signal charges from remaining, the N-type impurity concentration of the photodiode N layer 102 is lowered as much as possible, for example, to the same level as that of an intrinsic semiconductor, and the potential of the photodiode N layer 102 is lowered. It can also be taken.

  However, if this is done, the potential well of the photodiode N layer 102 becomes shallow, and the function of accumulating signal charges in the photodiode N layer 102 is practically lost. As a result, the photoelectrically converted signal charge overflows from the potential well, and the overflowed signal charge and the signal charge generated near the photodiode N layer 102 are likely to diffuse to adjacent pixels, This will cause crosstalk.

On the other hand, in the solid-state imaging device disclosed in Patent Document 2, since a negative DC bias voltage is applied to the electrode arranged on the light receiving surface side, the P-type on the opposite surface is always applied during the operation period of the solid-state imaging device. A current flows from the well to the electrode arranged on the light receiving surface side. As a result, there is a problem that power consumption increases and random noise due to a temperature rise associated therewith increases.
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a solid-state imaging device capable of preventing afterimages, random noise, crosstalk, and the like, and a driving method thereof.

  In order to achieve the above object, a solid-state image pickup device according to the present invention is a back-illuminated solid-state image pickup device in which a plurality of unit cells having a light receiving surface as a back surface, which is one main surface of a semiconductor substrate, are arranged in a matrix. Each unit cell includes a light receiving surface layer of a first conductivity type provided at a position closest to the back surface in the thickness direction in the semiconductor substrate, and the light receiving surface layer in the semiconductor substrate than the light receiving surface layer. The first conductivity type is provided on the side close to the surface which is the other main surface of the semiconductor substrate and accumulates signal charges obtained by photoelectrically converting the light incident on the light receiving surface layer. A second-conductivity-type photoelectric conversion region, and a second-conductivity-type charge storage layer that is provided closer to the surface than the photoelectric conversion region in the semiconductor substrate and accumulates signal charges transferred from the photoelectric conversion region And in the semiconductor substrate A potential barrier layer of a first conductivity type interposed between the photoelectric conversion region and the charge storage layer, and a signal charge stored in the photoelectric conversion region is transferred to the charge storage layer by the potential barrier of the potential barrier layer. And a first voltage for preventing the signal charge from being transferred to the charge storage layer via the potential barrier layer, and an electrode for selectively applying a second voltage for transferring the signal charge to the light receiving surface layer. It is characterized by.

In this way, a potential well is formed in the photoelectric conversion region by applying the first voltage to the electrode during the period in which the photoelectrically converted signal charge is accumulated in the photoelectric conversion region, thereby forming a potential barrier in the potential barrier layer. In the period in which the signal charge is stored in the photoelectric conversion region and the signal charge is transferred to the charge storage layer, the transfer can be performed by applying the second voltage for transfer to the electrode.
As a result, even if the potential well in the photoelectric conversion region is deepened to some extent, all accumulated signal charges can be transferred, and the occurrence of crosstalk, afterimages, and random noise caused by diffusion can be prevented.

  In addition, a bias circuit for supplying the voltage to the electrode is provided, and the bias circuit has a potential barrier formed in the potential barrier layer during the accumulation period in which signal charges are accumulated in the photoelectric conversion region as the first voltage. As the second voltage, during the signal charge transfer period, when the first conductivity type is P type and the second conductivity type is N type, the charge accumulation layer is supplied from the photoelectric conversion region. When the first conductivity type is N-type and the second conductivity type is P-type, the potential monotonously decreases from the photoelectric conversion region toward the charge storage layer. A voltage may be supplied.

The transfer period is a predetermined period in the vertical blanking period, and the accumulation period is a period excluding the predetermined period, and is at least one of a horizontal scanning period and a vertical scanning period including a horizontal blanking period. It may be a period including parts.
In such a configuration, a so-called global shutter can be realized by setting the transfer period to a predetermined period and setting the accumulation period to the same period for all unit cells.

Further, the transfer period may be a predetermined period in a horizontal blanking period, and the accumulation period may be a period excluding the predetermined period, and a period including at least a horizontal scanning period.
In this way, each unit cell transfers the signal charge accumulated in the photoelectric conversion region to the charge accumulation layer when it reaches a predetermined period in the horizontal blanking period for each horizontal blanking period to the charge accumulation layer. When the selected row outputs the accumulated signal charge while accumulating the signal charge, the signal charge accumulated in the charge accumulation layer can be output and the accumulation period becomes the selected row. By setting the period until the next selected row, it is possible to realize a so-called rolling shutter in which the accumulation period is shifted by one horizontal scanning cycle for each row.

Here, at least a part of the transfer period may overlap with a period in which signal charges are output from the charge storage layer, and the transfer period and the output period may be ended substantially simultaneously.
In this way, the transfer of the signal charge accumulated in the photoelectric conversion region to the charge accumulation layer and the output of the signal charge accumulated in the charge accumulation layer can be performed simultaneously in parallel.
In addition, a storage surface layer of a first conductivity type may be provided on the side closer to the surface than the charge storage layer in the semiconductor substrate.

In this way, it is possible to suppress the occurrence of dark current due to the interface state while stabilizing the potential of the surface side surface of the charge storage layer.
Furthermore, the electrode may be a transparent electrode provided on the back surface of the semiconductor substrate and electrically connected to the light receiving surface layer.
In this way, a voltage can be uniformly applied to the back surface of the semiconductor substrate in the surface direction.

The first voltage may be a ground potential.
In this way, power consumption can be reduced when the signal charge is not transferred.
In addition, the solid-state imaging device driving method according to the present invention drives a back-illuminated solid-state imaging device in which a plurality of unit cells having a light receiving surface on the back surface, which is one main surface of a semiconductor substrate, are arranged in a matrix. The unit cell includes a light receiving surface layer of a first conductivity type provided at a position closest to the back surface in the thickness direction in the semiconductor substrate, and a light receiving surface layer in the semiconductor substrate than the light receiving surface layer. Provided on the side close to the surface that is the other main surface of the semiconductor substrate, and accumulates signal charges obtained by photoelectrically converting light incident on the light receiving surface layer, and having a polarity opposite to that of the first conductivity type A second conductivity type photoelectric conversion region, and a second conductivity type charge storage that is provided closer to the surface than the photoelectric conversion region in the semiconductor substrate, and accumulates signal charges transferred from the photoelectric conversion region. Layer and said semiconductor substrate A potential barrier layer of a first conductivity type interposed between the photoelectric conversion region and the charge storage layer, and the driving method includes the photoelectric conversion during the storage period in which signal charges are stored in the photoelectric conversion region. A first step of applying a first voltage to the light receiving surface layer to prevent the signal charge accumulated in the conversion region from being transferred to the charge accumulation layer by the potential barrier of the potential barrier layer; and during the transfer period of the signal charge, As the second voltage for transferring the signal charge to the charge storage layer through the potential barrier layer, the photoelectric conversion region when the first conductivity type is P type and the second conductivity type is N type. When the first conductivity type is N-type and the second conductivity type is P-type, the potential increases monotonically from the photoelectric conversion region toward the charge storage layer. Is a monotonically decreasing voltage. And executes a step of including a second step for applying the surface layer.

According to this configuration, the first voltage is applied during the period in which the photoelectrically converted signal charges are accumulated in the photoelectric conversion region, the potential barrier is formed in the potential barrier layer, and the signal is supplied to the potential well formed in the photoelectric conversion region. When the period for transferring the signal charge from the photoelectric conversion region to the charge storage layer while accumulating the charge is reached, the transfer can be performed by applying the second voltage for the transfer.
As a result, even if the potential well in the photoelectric conversion region is deepened to some extent, all accumulated signal charges can be transferred, and the occurrence of crosstalk, afterimages, and random noise caused by diffusion can be prevented.

The transfer period is a predetermined period in the vertical blanking period, and the accumulation period is a period excluding the predetermined period, and is at least one of a horizontal scanning period and a vertical scanning period including a horizontal blanking period. It may be a period including parts.
In such a configuration, a so-called global shutter can be realized by setting the transfer period to a predetermined period and setting the accumulation period to the same period for all unit cells.

Further, the transfer period may be a predetermined period in a horizontal blanking period, and the accumulation period may be a period excluding the predetermined period, and a period including at least a horizontal scanning period.
In this way, each unit cell transfers the signal charge accumulated in the photoelectric conversion region to the charge accumulation layer when it reaches a predetermined period in the horizontal blanking period for each horizontal blanking period to the charge accumulation layer. When the selected row outputs the accumulated signal charge while accumulating the signal charge, the signal charge accumulated in the charge accumulation layer can be output and the accumulation period becomes the selected row. By setting the period until the next selected row, it is possible to realize a so-called rolling shutter in which the accumulation period is shifted by one horizontal scanning cycle for each row.

Here, at least a part of the transfer period may overlap with a period in which signal charges are output from the charge storage layer, and the transfer period and the output period may be ended substantially simultaneously.
In this way, the transfer of the signal charge accumulated in the photoelectric conversion region to the charge accumulation layer and the output of the signal charge accumulated in the charge accumulation layer can be performed simultaneously in parallel.
Furthermore, the first voltage may be a ground potential.

In this way, power consumption can be reduced when the signal charge is not transferred.
The solid-state imaging device driving method according to the present invention is incident on the light-receiving surface layer of the first conductivity type provided in the thickness direction in the semiconductor substrate at a position closest to the back surface which is one main surface of the semiconductor substrate. Opposite to the first conductivity type, which photoelectrically converts light and the photoelectrically converted signal charge is provided in the semiconductor substrate closer to the surface which is the other main surface of the semiconductor substrate than the light receiving surface layer. Accumulated in the accumulation region of the second conductivity type of polarity, the accumulated signal charge from the accumulation region by a readout circuit provided closer to the surface than the light receiving surface layer in the semiconductor substrate in the signal readout period A method of driving a back-illuminated solid-state imaging device in which a plurality of unit cells to be read are arranged in a matrix form, wherein the ground potential is received as a first voltage for signal charge accumulation during a signal charge accumulation period. surface The first voltage is applied to the first voltage and the second voltage is determined to be less than the first voltage during a predetermined period in the horizontal blanking period, when the first conductivity type is P type and the second conductivity type is N type. A second voltage having a lower potential than the first voltage is applied to the light receiving surface layer when the first conductivity type is N type and the second conductivity type is P type. It is applied to the light receiving surface layer.

In this way, the power consumption is suppressed compared to the conventional configuration in which the voltage for signal charge transfer is always applied to the semiconductor substrate including the signal charge accumulation period, and the temperature rise due to high power consumption. The generation of random noise due to can be prevented.
The accumulation period may be a period including at least a horizontal scanning period.
Furthermore, at least a part of the predetermined period may overlap with the signal readout period, and the predetermined period and the signal readout period may be ended almost simultaneously.

  In this way, it is possible to simultaneously read out the signal charges while forming an electric field for sending the signal charges accumulated in the accumulation region to the signal readout circuit, and to prevent the accumulated signal charges from remaining. Can be planned.

1 is a diagram illustrating an overall configuration of a solid-state imaging element according to Embodiment 1. FIG. It is principal part sectional drawing of the unit cell of a solid-state image sensor. It is an equivalent circuit diagram of a unit cell. It is a timing chart which shows the drive method of a solid-state image sensor. It is a timing chart which shows the drive method of a solid-state image sensor. It is an electric potential distribution diagram of a solid-state image sensor. FIG. 6 is a cross-sectional view of a main part of a unit cell of a solid-state imaging device according to a second embodiment. 10 is a timing chart illustrating a method for driving a solid-state imaging element according to Embodiment 3. 10 is a timing chart illustrating a method for driving a solid-state imaging element according to Embodiment 3. 6 is a timing chart illustrating a method for driving a solid-state imaging element according to Embodiment 4. 6 is a potential distribution diagram of a solid-state imaging element according to Embodiment 4. FIG. It is principal part sectional drawing of the unit cell of the conventional solid-state image sensor.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<Embodiment 1>
FIG. 1 is an overall configuration diagram illustrating an example of a solid-state imaging device according to the present embodiment.
As shown in the figure, the solid-state imaging device includes an imaging region 1, a vertical scanning circuit 2, a horizontal scanning circuit 3, a column readout circuit 4, an output circuit 5, a timing generator 6, and a back bias generating circuit 7. Etc.

The imaging region 1 is a pixel array in which a plurality of pixels (unit cells) 8 composed of CMOS sensors are arranged in a matrix in the row direction (left-right direction in the figure) and the column direction (up-down direction in the figure). For each unit cell, incident light is photoelectrically converted to generate a pixel signal.
The vertical scanning circuit 2 controls the horizontal signal lines L1 to Ln, sequentially selects each row, and reads the pixel signal of each unit cell 8 in the selected row. The read pixel signal of each unit cell 8 is sent to the column readout circuit 4 via the vertical signal lines VL1 to VLn. This reading is performed during the horizontal blanking period.

The column readout circuit 4 sequentially outputs pixel signals sent from the unit cells 8 in the selected row to the output circuit 5 in units of pixels based on the control of the horizontal scanning circuit 3. This signal output is performed during the horizontal scanning period.
The output circuit 5 outputs the pixel signal sent from the column readout circuit 3 to the subsequent stage.
The back surface bias generation circuit 7 outputs a back surface bias pulse φBB to each pixel 8. The contents of the back bias pulse φBB will be described later.

The timing generator 6 supplies signals for driving the vertical scanning circuit 2, the horizontal scanning circuit 3, the column readout circuit 4, and the backside bias generation circuit 7 to each circuit. Note that either or both of the timing generator 6 and the backside bias generation circuit 7 may be provided on the same semiconductor substrate as the imaging region, or may be provided on another semiconductor substrate.
FIG. 2 is a cross-sectional view of the main part of one unit cell 8.

As shown in the figure, the unit cell 8 has an upper surface that is one surface of the semiconductor substrate 10 as a first surface (front surface) and a lower surface that is the other surface as a second surface (back surface). The wiring layer 26 and the support substrate 28 are arranged on the first surface in this order, and the second surface is a back-illuminated type in which the second surface serves as a light-receiving surface that receives incident light. The configuration shown in FIG. 6 is the same for the other unit cells 8.
In the semiconductor substrate 10, a P-type light-receiving surface layer 12 that receives incident light is provided at a position closest to the second surface in the thickness direction, and is closer to the first surface than the P-type light-receiving surface layer 12. An N-type photoelectric conversion region 11 is provided on the near side.

The P-type light-receiving surface layer 12 fixes the potential of the surface on the second surface side in the N-type photoelectric conversion region 11 and fills the vicinity of the semiconductor interface on the second surface with holes, thereby dark current due to the interface state. Suppresses the occurrence of The light receiving surface layer 12 is provided in an internal region including the second surface of the semiconductor substrate 10 and is configured to form the second surface of the semiconductor substrate 10.
The N-type photoelectric conversion region 11 functions as a photodiode that photoelectrically converts received incident light and accumulates signal charges that have been photoelectrically converted. Hereinafter, the photoelectric conversion region 11 is referred to as a photodiode 11.

In the semiconductor substrate 10, an N-type charge accumulation layer 13 for accumulating signal charges transferred from the photodiode 11 is provided on the side closer to the first surface than the photodiode 11 in the thickness direction.
Between the N-type photodiode 11 and the N-type charge storage layer 13 in the semiconductor substrate 10, a potential barrier against the signal charge during a period other than when the signal charge is transferred from the photodiode 11 to the charge storage layer 13. A P-type potential barrier layer 14 is formed.

Further, in the semiconductor substrate 10, on the side closer to the first surface than the potential barrier layer 14, a MOS having an N-type charge storage layer 13 as a source, an N-type floating diffusion layer 15 as a drain, and a transfer gate 16 as a gate. A type read transistor M41 (FIG. 3) is provided.
The read transistor M41 reads the signal charge stored in the charge storage layer 13, and uses this as a pixel signal, and a vertical signal line through an amplification transistor M43 (FIG. 3) as a pixel amplifier and a selection transistor M44 (FIG. 3). The data is sent to the column readout circuit 4 by VL.

The read transistor M41 and the pixel amplifier are provided in a P-type well 18 provided in the semiconductor substrate 10 in the thickness direction on the side closer to the first surface than the potential barrier layer 14.
A P-type accumulation surface layer 17 is provided on the first surface side of the N-type charge accumulation layer 13, and the P-type accumulation surface layer 17 is a boundary between other adjacent unit cells. It is in contact with the P-type first separation region 19 having a function. The P-type isolation region 19 is grounded.

The P-type accumulation surface layer 17 is provided in an internal region including the first surface of the semiconductor substrate 10 and forms a part of the first surface of the semiconductor substrate 10.
Similarly to the P-type light-receiving surface layer 12, the P-type storage surface layer 17 fixes the potential of the surface on the first surface side of the N-type charge storage layer 13, and also opens a hole near the semiconductor interface on the first surface. To suppress the generation of dark current due to interface states.

Further, when the N-type photodiode 11 is viewed from the second surface side, the P-type second separation is performed so as to surround the periphery of the portion of the photodiode 11 located on the second surface side in the semiconductor substrate 10. Region 20 is provided. The P-type second isolation region 20 has a function of partitioning the photodiode 11 of another adjacent unit cell.
Further, in the region surrounding the periphery of the photodiode 11 in the semiconductor substrate 10, the third isolation region 21 is connected so as to connect the P-type well 18 close to the first surface and the second isolation region 20 close to the second surface. Is provided. The third separation region 21 also has a function of a boundary with other adjacent unit cells. Further, a P-type high concentration layer 22 is provided in the deep part of the P-type well 18 so that signal charges are not mixed into the readout circuit formed in the P-type well 18.

  The P-type light receiving surface layer 12 is connected to the back surface bias generation circuit 7 through a metal light shielding film 23 for shielding light between unit cells (pixels) in the semiconductor substrate 10. The metal light-shielding film 23 has a function as an electrode for electrically connecting the P-type light-receiving surface layer 12 to the backside bias generation circuit 7. In addition, since the member which functions as an electrode should just exist, it is not restricted to the metal light shielding film 23, Another member may be used.

  As will be described later, a negative bias voltage is applied to the light-receiving surface layer 12 by the back surface bias generation circuit 7 when the signal charge is transferred. At this time, a current flows from the grounded first isolation region 19 to the light receiving surface layer 12 via the third isolation region 21. In order to reduce this current and further reduce power consumption, It is desirable that the P-type impurity concentration in the third isolation region 21 is lower than the impurity concentration in the light receiving surface layer 12 and the second isolation region 20.

Further, a color filter layer 24 and a microlens 25 are provided on the light receiving surface layer 12, a wiring 27 is provided in the wiring layer 26, and a support substrate 28 is bonded on the wiring layer 26.
In the driving method described later (described with reference to FIGS. 4 and 5), in particular, in the case of moving image imaging in which vertical scanning is continuously performed, the photodiode 11 is transmitted when incident light is received, and charge accumulation is performed. The charge that is photoelectrically converted in the vicinity of the layer 13 and accumulated in the charge accumulation layer 13 may be read out at a timing earlier than the signal charge accumulated in the photodiode 11 and may become a false signal. Further, in the case of still image imaging in which vertical scanning is performed only once, the false signal can be prevented by discharging the charge accumulated in the charge accumulation layer 13 before reading out the signal charge accumulated in the photodiode 11. In this case, however, the charges accumulated in the charge accumulation layer 13 are not used as signal charges.

  Therefore, in order to prevent the generation of the false signal and to increase the quantum efficiency defined by the ratio of the number of electrons of the signal charge generated with respect to the number of photons of the incident light and increase the sensitivity, the photodiode 11 It is preferable that the thickness of the layer is somewhat thick. As a solid-state imaging device for receiving visible light, the layer thickness of the photodiode 11 is preferably 2 to 10 micrometers.

FIG. 3 is a diagram showing an equivalent circuit of the unit cell 8.
In the figure, nodes corresponding to an N-type photodiode 11, a P-type light-receiving surface layer 12, an N-type charge storage layer 13, an N-type floating diffusion layer 15, a P-type storage surface layer 17 and a transfer gate 16. Are given the same number.
As shown in the figure, the P-type light receiving surface layer 12 and the N-type photodiode 11, and the P-type storage surface layer 17 and the N-type charge storage layer 13 constitute PN diodes D41 and D42, respectively. The third isolation region 21, the P-type well 18, the first isolation region 19 and the second isolation region 20 that connect the P-type light-receiving surface layer 12 and the storage surface layer 17 have equivalent resistances R41 and R42. It is shown in

  The N-type photodiode 11, the P-type potential barrier layer 14, and the N-type charge storage layer 13 are represented by an NPN-type bipolar transistor Q41. As will be described later, the P-type potential barrier layer 14 corresponding to the base of the bipolar transistor Q41 functions as a potential barrier against the signal charge by depletion except when the signal charge passes in the operating state of the solid-state imaging device. . The base resistance of the bipolar transistor Q41 is indicated by R43.

  Further, the unit cell 8 includes a MOS read transistor M41 having a transfer gate 16 to which a transfer pulse ΦTG is applied as a gate, and a MOS to which a reset pulse ΦRS for resetting the potential of the N-type floating diffusion layer 15 is applied. A reset transistor M42 of the type, an amplification transistor M43 having a floating diffusion layer 15 connected to the gate, and a selection transistor M44 to which a row selection pulse ΦSEL is applied are provided as a signal readout circuit.

The transfer pulse ΦTG, the reset pulse ΦRS, and the row selection pulse ΦSEL are supplied from the vertical scanning circuit 2 to the unit cell 8 through the horizontal signal line L.
The drain of the reset transistor M42 and the drain of the amplification transistor M43 are both connected to the power supply VDD, the source of the amplification transistor M43 is connected to the drain of the selection transistor M44, and the source of the selection transistor M44 is connected via the vertical signal line VL. Connected to the column readout circuit 4.

4 and 5 are timing charts showing an example of a driving method of the solid-state imaging device. FIG. 4 shows a driving method in the vertical blanking period, and FIG. 5 shows a driving method in the horizontal blanking period. is there.
FIG. 4 shows the back surface bias pulse ΦBB applied to the P-type light receiving surface layer 12 in the vertical blanking period, and the potential of the photodiode 11 (photodiode potential) and the charge storage layer 13 accompanying the application of the back surface bias pulse ΦBB. The respective fluctuations of the potential (charge storage layer potential) are shown.

  The backside bias pulse ΦBB is at a high level (VBB-high) during the vertical scanning period (before time T1 and after time T4), before time T2 within the vertical blanking period, and after time T3, and the time within the vertical blanking period. In the period from T2 to T3, a low level (VBB-low) voltage value is taken. As described later, the high level of the back bias pulse ΦBB is 0 volt (ground potential), and the low level is a negative voltage.

This period from time T2 to T3 corresponds to a first charge transfer period in which signal charges are transferred from the photodiode 11 to the charge storage layer 13. That is, transfer of signal charges from the photodiode 11 to the charge storage layer 13 is executed when the back bias pulse ΦBB is at a low level. The mechanism of this transfer will be described later.
In the case of moving image capturing in which vertical scanning is continuously performed, the photodiode accumulation period in which the received incident light is photoelectrically converted and the photoelectrically converted signal charge is accumulated in the photodiode 11 is from the above time T2 to T3. This period is included in a period from time T3 in any vertical blanking period to time T2 in the next vertical blanking period.

  In particular, when a means for separately controlling the exposure period or the accumulation period is not used, the photodiode accumulation period starts from the time T3 in an arbitrary vertical blanking period to the time T2 in the next vertical blanking period. It corresponds to the period until. On the other hand, in the case of still image capturing in which vertical scanning is performed only once, the photodiode accumulation period is set to a period before the period from time T2 to T3. In this sense, the photodiode accumulation period is a period including at least one part of the horizontal scanning period and the vertical scanning period including the horizontal blanking period in each row, except for the first charge transfer period in the vertical blanking period. be able to. However, when incident light is received during the transfer period, the signal charge photoelectrically converted during the transfer period is transferred from the photodiode 11 to the charge storage layer 13 during the same transfer period. This is a period that contributes to photoelectric conversion.

FIG. 5 shows a row selection pulse ΦSEL, a reset pulse ΦRS, a transfer pulse ΦTG, a backside bias pulse ΦBB, and a charge storage layer applied to each unit cell (each pixel) in a row selected for reading in the horizontal blanking period. 13 shows fluctuations in the potential of 13 (charge storage layer potential) and the potential of the floating diffusion layer 15 (floating diffusion layer potential).
As shown in the figure, during the period from time T5 to T10 when the row selection pulse ΦSEL becomes high level, the reset pulse ΦRS becomes high level during the period from time T6 to T7, so that the floating diffusion layer potential becomes the reference potential. Reset. Then, the transfer pulse ΦTG becomes high level during the period from time T8 to T9. As a result, the signal charge accumulated in the charge accumulation layer 13 is transferred (output) to the floating diffusion layer 15 and sent to the column readout circuit 4 via the amplification transistor M43 and the selection transistor M44.

This period from time T8 to T9 corresponds to a second charge transfer period in which signal charges are transferred (output) from the charge storage layer 13 to the floating diffusion layer 15. Note that the back surface bias pulse ΦBB is maintained at a high level throughout the horizontal blanking period.
As shown in FIG. 4 and FIG. 5, the back side bias pulse ΦBB becomes a low level at the same timing only in a specific period within the vertical blanking period and becomes a high level throughout the horizontal blanking period for all unit cells. ing. Although not shown, the back surface bias pulse ΦBB is at a high level even during the horizontal scanning period.

In the configuration of the solid-state imaging device having such a potential level, the state of signal charge transfer in one unit cell 8 will be described first with reference to FIG. 6, and then the specific potential levels shown in FIG. 4 and FIG. Explain the contents.
FIG. 6 is a diagram showing a potential distribution along the AA ′ line and the CC ′ line in FIG. 2.
In this figure, the horizontal axis indicates the position of each region from the accumulation surface layer 17 on the first surface side to the light-receiving surface layer 12 on the second surface side, and the vertical axis indicates the potential (downward is positive). The example of potential distribution when the high level VBB-high of the backside bias pulse ΦBB is 0 V and the low level VBB-low is a negative voltage value is shown. 6A shows the potential distribution at time t1 in FIG. 4, FIG. 6B shows the potential distribution at time t2, and FIG. 6C shows the potential distribution at time t3.

  As shown in FIG. 6A, at time t1 (one point in the photodiode accumulation period), the P-type light-receiving surface layer 12 has a high-level signal of the back surface bias pulse ΦBB, here 0 V (first bias). Voltage) is applied, and the potential of the P-type light-receiving surface layer 12 is equal to the ground potential of the P-type accumulation surface layer 17 that is grounded via the P-type first isolation region 19. . As indicated by a solid line (potential distribution along the line AA ′) in the figure, the photodiode 11 has a potential well (in which a signal charge obtained by photoelectric conversion of received incident light is accumulated ( The potential barrier (the peak portion of the graph) is formed in the potential barrier layer 14 so that the signal charge accumulated in the potential well does not flow out to the charge storage layer 13. In this sense, the first bias voltage can be said to be a first voltage for preventing signal charges from being transferred to the charge storage layer 13 through the potential barrier.

The potential barrier is such that the N-type photodiode 11, the P-type potential barrier layer 14, and the N-type charge storage layer 13 are sequentially arranged along the direction from the second surface to the first surface of the semiconductor substrate 10. The P-type potential barrier layer 14 is provided between the N-type photodiode 11 and the N-type charge storage layer 13 and is depleted.
Further, as indicated by a broken line (potential distribution along the line CC ′) in the figure, a P-type well close to the first surface in the semiconductor substrate 10 in the element isolation region with the adjacent unit cell (pixel). In the third isolation region 21 provided so as to connect 18 and the second isolation region 20 close to the second surface, the signal charge accumulated in the potential well is about 0 V so as not to flow out to the potential well of the adjacent unit cell. Potential barrier is formed. The state of the potential distribution shown in FIG. 6A is continuously maintained during the photodiode accumulation period.

  Since the light receiving surface layer 12 to the storage surface layer 17 are provided in the semiconductor substrate 10 so that the polarities of adjacent ones differ from the second surface to the first surface in the thickness direction, At the N-type photodiode 11 in the graph, a valley portion (potential well) is formed with respect to the peak-shaped portions of the P-type light-receiving surface layer 12 and the potential barrier layer 14 located on both sides. Since the potential barrier (crest portion) between the photodiode 11 and the charge storage layer 13 continues to exist during the photodiode storage period, the signal charges photoelectrically converted in the semiconductor substrate 10 exist in the photodiode 11. Of course, not only those that exist in the vicinity of the photodiode 11 but also those that exist in the vicinity of the photodiode 11 are likely to gather at the potential well formed in the photodiode 11.

As shown in FIG. 6B, at time t2 (one point in the first charge transfer period), the back side bias pulse ΦBB is at a low level, that is, the potential is monotonic from the photodiode 11 toward the charge storage layer 13. A negative voltage value (second bias voltage) that increases is applied.
As a result, the potential barrier of the potential barrier layer 14 disappears, and an electric field for transferring signal charges from the photodiode 11 to the charge storage layer 13 is formed. The electric field is stored in the photodiode 11 during the photodiode storage period up to time t2. The signal charge is transferred to the charge storage layer 13. Since the potential monotonously increases from the photodiode 11 toward the charge storage layer 13, the signal charge stored in the photodiode 11 can be completely transferred, and an afterimage caused by a part of the photodiode 11 remaining. Generation of random noise is prevented. In this sense, the second bias voltage can be said to be a second voltage for transferring the signal charge to the charge storage layer 13 via the potential barrier layer 14. The transfer of signal charges from the photodiode 11 to the charge storage layer 13 is performed simultaneously for all unit cells.

  In the first charge transfer period, a second bias voltage lower than the voltage applied to the first isolation region 19 provided on the first surface of the semiconductor substrate 10 is applied to the light receiving surface layer 12. For this reason, a current flows from the first isolation region 19 toward the light-receiving surface layer 12 mainly via the P-type isolation region 21 that partitions and separates adjacent photodiodes, but the second bias voltage The period during which is applied is limited to a predetermined period within the vertical blanking period, and while suppressing power consumption, it is possible to prevent an increase in random noise or the like due to a temperature rise accompanying an increase in power consumption. This is the same in other embodiments described later.

  As shown in FIG. 6C, at time t3 (time after the end of the first charge transfer period), the transfer of the signal charge from the photodiode 11 to the charge storage layer 13 is completed. Depending on the setting of the start time of the photodiode accumulation period, there may be a case where the next accumulation period has already been entered at time t3, or it may be started after that. Further, depending on the setting of the exposure period or the like, the accumulation of the next signal charge may already be started at time t3, or may be started thereafter.

The state of potential fluctuations in the photodiode 11 and the charge storage layer 13 during the vertical blanking period accompanying the above-described transfer of signal charges will be specifically described with reference to FIG.
In FIG. 4, the photodiode potential is negative by ΔVPD1 due to capacitive coupling with the light receiving surface layer 12 due to the potential change of the light receiving surface layer 12 due to the potential change to the low level of the back surface bias pulse ΦBB at time T2. Since the signal charge accumulated in the photodiode 11 flows out from the photodiode 11 immediately after that, the potential rises by the amount of outflow of signal charge (ΔVPD2).

At time T3, the potential shifts in the positive direction by ΔVPD1 due to capacitive coupling with the light receiving surface layer 12 due to the potential change of the light receiving surface layer 12 due to the potential change from the low level to the high level of the back surface bias pulse ΦBB. As a result, the photodiode potential rises by ΔVPD2 before and after the transfer.
On the other hand, at time T2, the potential of the charge storage layer shifts in the negative direction by ΔVST1 due to capacitive coupling with the light receiving surface layer 12 due to the potential change of the light receiving surface layer 12. Since the signal charge sent through the barrier layer 14 flows in, the potential drops by an amount corresponding to the inflow of the signal charge (ΔVST2). At time T 3, the potential is shifted in the positive direction by ΔVST 1 due to capacitive coupling with the light receiving surface layer 12 in accordance with the potential change of the light receiving surface layer 12. As a result, the charge storage layer potential drops by ΔVST2 before and after the transfer.

Next, potential fluctuations of the charge storage layer 13 and the floating diffusion layer 15 during the horizontal blanking period accompanying the above-described transfer of signal charges will be described with reference to FIG. Here, the potential fluctuation shown in FIG. 5 is in a pixel corresponding to a selected row in which the row selection pulse ΦSEL is at a high level in the imaging region.
The charge storage layer potential is transferred (read) from the charge storage layer 13 to the floating diffusion layer 15 when the transfer pulse ΦTG becomes a high level at time T8. The potential increases by the amount of transfer (ΔVST2).

  On the other hand, since the signal charge accumulated in the floating diffusion layer 15 is discharged from the floating diffusion layer 15 until the reset pulse ΦRS becomes a high level at time T6, the floating diffusion layer potential is discharged from the floating diffusion layer 15. The potential rises by the amount (ΔVFD1). At time T8, the transfer pulse ΦTG becomes high level, so that the signal charge is transferred from the charge storage layer 13 and enters the floating diffusion layer 15, so that the potential drops by the amount of transfer of the signal charge (ΔVFD2). .

  In FIG. 5, the reference potential output period is set within the period from the previous signal charge being discharged from the floating diffusion layer 15 until the next signal charge is transferred from the charge storage layer 13, and the transfer of the signal charge is completed. The signal output period is set within the period. The signal charge corresponding to the potential difference ΔVFD2 of the floating diffusion layer 15 between the reference potential output period and the signal output period can be output to the column readout circuit 4 by sequentially reading out through the pixel amplifier such as the amplification transistor M43.

  4 and 5, the signal charges of all the photodiodes 11 that contribute to the image signal for one screen are transferred from the photodiodes 11 to the charge storage layer 13 at the same timing in the first charge transfer period. Transferred. As a result, the photodiode accumulation period for accumulating the photoelectrically converted signal charges in the photodiode 11 is the same for all the photodiodes 11 that contribute to the image signal for one screen, and a so-called global shutter can be realized. .

  As described above, the P-type, N-type, P-type, N-type, and P-type layers (light-receiving surface layer 12, photodiode 11, potential barrier) are formed in the semiconductor substrate 10 from the second surface toward the first surface in the thickness direction. By providing the layer 14, the charge storage layer 13, and the storage surface layer 17) in this order, the potential distribution graph extends from the second surface to the first surface in the case of other than signal charge transfer. This is a graph in which the signal charges are formed, and the photoelectrically converted signal charges are easily collected in the valley portions (potential wells) formed in the photodiode 11. The electric field strength guided to the potential well can be further increased, and even if the potential well of the photodiode 11 is deepened to some extent, it is possible to transfer all signal charges and to prevent crosstalk failure caused by diffusion. .

  At the time of transferring the signal charge, an electric field for transferring the signal charge is formed by applying a voltage whose potential increases monotonously from the second surface side to the first surface side. The signal charges accumulated in the potential well formed in (1) can be transferred to the charge accumulation layer 13 via the potential barrier layer 14. As a result, the photodiode and the signal charge transfer path have the same polarity as in the prior art, and an electric field for sending the signal charge from the photodiode toward the signal charge transfer path cannot be formed. It is possible to prevent afterimages and random noise from occurring.

Further, since an electric field for transferring a signal charge is formed by applying a voltage during the first charge transfer period, in order to form an electric field for guiding the signal charge accumulated in the conventional configuration to the signal charge transfer path, By making the semiconductor substrate close to intrinsic, for example, it is possible to prevent the potential well from becoming shallow and causing crosstalk.
Further, the signal charges photoelectrically converted are collected in a potential well formed at the photodiode 11 at times other than the transfer, and a signal stored in the photodiode 11 is applied by applying a voltage for transfer only at the time of transfer. Since electric charges can be output, it is not necessary to always apply a voltage for transfer as in the conventional case, and it is possible to prevent the occurrence of random noise accompanying temperature rise while realizing low power consumption. . In the above description, the first bias voltage and the second bias voltage lower than the first bias voltage are selectively applied from the electrode (metal light shielding film 23) to the light receiving surface layer 12, and the first bias voltage is used. However, the voltage value is not limited to this, and a suitable value can be set within a range where the above-described effects can be obtained. .

<Embodiment 2>
In the above embodiment, the example in which the metal light-shielding film 23 is used as an electrode for supplying a voltage for transferring a signal charge to the light receiving surface layer 12 has been described. However, in this embodiment, a transparent electrode is provided. This point is different from the first embodiment. Hereinafter, in order to avoid duplication of description, the description of the same contents as those of Embodiment 1 is omitted, and the same components are denoted by the same reference numerals.

FIG. 7 is a cross-sectional view of a main part of a unit cell constituting an imaging region of the solid-state imaging device according to the second embodiment.
As shown in the figure, the structures in the semiconductor substrate 10 and on the first surface side are the same as those in the first embodiment. The difference from the first embodiment is that an electron injection preventing layer 31 and a transparent electrode 32 are provided on the light receiving surface layer 12.

  The transparent electrode 32 is connected to the back surface bias generation circuit 7, and the bias voltage from the back surface bias generation circuit 7 is applied to the light receiving surface layer 12 through the transparent electrode 32 and the electron injection prevention layer 31. By providing the electron injection prevention layer 31, it is possible to prevent injection of electrons from the transparent electrode 32 into the semiconductor substrate 10 when the back surface bias pulse ΦBB is applied by the back surface bias generation circuit 7.

Then, by providing the transparent electrode 32 in place of the metal light shielding film 23, the entire light receiving surface of the unit cell 8 becomes an open region where light is not shielded, that is, the aperture ratio is 100%, and the sensitivity is further improved and the light receiving surface layer 12 is provided. A bias voltage can be applied uniformly throughout.
For example, in the configuration in which the applied voltage value is different between the position near and away from the electrode in the surface direction of the light receiving surface layer 12, when the light receiving surface layer 12 is P-type, the light receiving surface layer is located away from the electrode. The potential of 12 becomes high, and the vicinity of the semiconductor interface cannot be filled with holes, and the dark current may increase. However, the voltage is applied uniformly in the plane direction as in this embodiment. Thus, it is possible to reliably suppress the occurrence of dark current without causing a place where the potential of the light receiving surface layer 12 becomes high.

  Similarly, when the light-receiving surface layer 12 is P-type, in the configuration in which a difference occurs in the value of the applied voltage between the position in the vicinity of the electrode and the position away from the electrode in the plane direction of the light-receiving surface layer 12, during the signal charge transfer period Although the potential of the light-receiving surface layer 12 becomes higher than the low level VBB-low at a position away from, and the electric field from the photodiode 11 toward the charge storage layer 13 is weakened, there is a possibility that the transfer is deteriorated. By adopting a configuration in which the voltage is uniformly applied in the surface direction as described above, the potential of the light receiving surface layer 12 can be uniformly set to the low level VBB-low, and transfer deterioration can be prevented.

<Embodiment 3>
In the above embodiment, the signal charge stored in the photodiode 11 is transferred to the charge storage layer 13 only for a certain period within the vertical blanking period. Each ranking period is transferred within the period, and this is different.

  In summary, each unit cell 8 transfers the signal charge accumulated in the photodiode 11 to the charge accumulation layer 13 for each horizontal blanking period until the row to which the unit cell belongs is selected, and the charge accumulation layer 13 13 will be accumulated. When a row is selected in the horizontal blanking period, in each unit cell 8 belonging to the selected row, the signal charge accumulated so far in the charge accumulation layer 13 is selected from the floating diffusion layer 15 to the amplification transistor M43. The signal is output to the vertical signal line VL via the transistor M44.

8 and 9 are timing charts showing a method of driving the solid-state imaging device according to the present embodiment. FIG. 8 is for the unit cell 8 belonging to an unselected row (non-selected row). Reference numeral 9 denotes the unit cell 8 belonging to the selected row (selected row).
As shown in FIG. 8, for the non-selected rows, the row selection pulse ΦSEL, the reset pulse ΦRS, and the transfer pulse ΦTG remain at a low level within the horizontal blanking period, but the back surface bias pulse ΦBB is at the time T31. To the low level only during the period from T32 to T32.

  During the period when the backside bias pulse ΦBB is at a low level (first charge transfer period), the signal charge accumulated in the photodiode 11 is accumulated from the photodiode 11 by the mechanism described with reference to FIG. Transferred to layer 13. Similar to the above-described embodiment, the negative back bias pulse ΦBB (low level signal) is simultaneously applied in common to all the unit cells (pixels) 8 constituting the imaging region.

  For this reason, regardless of the selected row and the non-selected row, the signal charges of all the photodiodes 11 accumulated in one horizontal scanning period are transferred to the charge accumulation layer 13 every horizontal blanking period. As the signal charges are transferred, the potential of the photodiode increases by the amount of signal charge flowing out (ΔVPD2), and the potential of the charge storage layer potential decreases by the amount of flowing in signal charge (ΔVST2). Note that the phenomenon that the photodiode potential and the charge storage layer potential shift by ΔVPD1 or ΔVST1 at time T31 and time T32 when the backside bias pulse ΦBB changes is as described above with reference to FIG.

The signal charge transfer shown in FIG. 8 is repeatedly executed in a non-selected row every horizontal blanking period.
On the other hand, in the selected row, as shown in FIG. 9, in the period from time T11 to T18 when the row selection pulse ΦSEL in the horizontal blanking period becomes high level, the reset pulse ΦRS becomes high level in the period from time T12 to T13. In the period from time T16 to T17, the transfer pulse ΦTG becomes high level. Further, the back surface bias pulse ΦBB becomes low level during the period from time T14 to T15 after the high level period of the reset pulse ΦRS and before the high level period of the transfer pulse ΦTG.

  As a result, the signal charge actually stored in the photodiode 11 is transferred from the photodiode 11 to the charge storage layer 13. In the figure, the photodiode potential is ΔVPD2 ′, which is distinguished from that in FIG. 8, but this is because the signal charge accumulated in the photodiode 11 by photoelectric conversion is applied to the charge accumulation layer 13 every horizontal blanking period. This is because the signal charges accumulated in the photodiode 11 are not the same every horizontal blanking period because they are transferred. The same applies to ΔVST2.

At time T16, application of the transfer pulse ΦTG causes all signal charges currently stored in the charge storage layer 13 to be transferred to the floating diffusion layer 15. After application of the transfer pulse ΦTG, signal charges in the charge storage layer 13 are transferred. Becomes empty. Accordingly, the charge storage layer potential increases by ΔVST3, and the floating diffusion layer potential decreases by ΔVFD3.
In the case of moving image capturing in which vertical scanning is continuously performed, the charge storage layer 13 is selected at the next timing after the transfer pulse ΦTG at the timing of the selected row is applied, and the transfer pulse ΦTG is applied again. The signal charge is accumulated little by little for each horizontal blanking period.

  The photodiode accumulation period in which the photoelectrically converted signal charges are accumulated in the photodiode 11 is selected at the next timing from the application end time T15 of the negative back bias pulse ΦBB during the horizontal blanking period that is the selected line. The time until the application end time T14 of the negative back bias pulse ΦBB during the horizontal blanking period is reached. In this sense, the photodiode accumulation period is a period excluding the first charge transfer period, and can be a period including at least a horizontal scanning period.

That is, the photodiode accumulation period is a so-called rolling shutter that is shifted by one horizontal scanning period for each row.
As described above, the signal charge accumulated in the photodiode 11 is transferred and accumulated in the charge accumulation layer 13 in the non-selected row every horizontal blanking period, and is stored in the charge accumulation layer 13 in the selected row. It is also possible to take a configuration in which the signal charges accumulated until then are output, thereby realizing a rolling shutter.

<Embodiment 4>
In the third embodiment, the timing is shifted so that the negative backside bias pulse ΦBB and the positive transfer pulse ΦTG do not overlap in the selected row. However, in this embodiment, the negative backside bias pulse ΦBB The application timing of the positive transfer pulse ΦTG overlaps, specifically, the negative back surface bias pulse ΦBB is first applied, then the application of the positive transfer pulse ΦTG is started, and then the application of both ends simultaneously. This point is different.

FIG. 10 is a timing chart illustrating a driving method of the solid-state imaging device according to the fourth embodiment. In the figure, both the selected row and the non-selected row are shown together.
In the non-selected row, although not shown in the figure, the row selection pulse ΦSEL, the reset pulse ΦRS, and the transfer pulse ΦTG are not applied during the horizontal blanking period, as in the non-selected row of the third embodiment. Only the back bias pulse ΦBB is applied. The change in potential between the photodiode potential and the charge storage layer potential (non-selected row) is the same as in FIG.

On the other hand, in the selected row, as shown in FIG. 10, the row selection pulse ΦSEL, the reset pulse ΦRS, the transfer pulse ΦTG, and the back bias pulse ΦBB are applied within the horizontal blanking period. At this time, the period in which the transfer pulse ΦTG is at a high level overlaps the period in which the back surface bias pulse ΦBB is at a low level.
That is, the back surface bias pulse ΦBB falls at time T22, and then the transfer pulse ΦTG rises at time T23. Then, at time T24, the back surface bias pulse ΦBB rises and the transfer pulse ΦTG falls.

  As described above, the application of the back surface bias pulse ΦBB is started first when the selected row is selected, and the application of the transfer pulse ΦTG is started immediately thereafter, so that the unit cell 8 accumulates the photodiode 11. The operation of transferring the signal charge from the charge storage layer 13 to the outside of the unit cell via the floating diffusion layer 15 and the pixel amplifier can be performed at a time while transferring the signal charge to the charge storage layer 13. This operation will be described with reference to FIG.

11 is a diagram showing potential distributions along the lines AA ′ and CC ′ in FIG. 2, and FIGS. 11A, 11B, and 11C are respectively shown in FIG. FIG. 6 is a potential distribution diagram at time t4, time t5, and time t6. In this example, the high level (VBB-high) of the back bias pulse ΦBB is 0 V and the low level (VBB-low) is a negative voltage value.
As shown in FIG. 11A, at time t4 (one point in the period for accumulating signal charges generated by photoelectric conversion), the high level (0 V) of the back surface bias pulse ΦBB is applied to the P-type light receiving surface layer 12. The potential of the P-type light-receiving surface layer 12 that is applied is equal to the potential of the P-type accumulation surface layer 17 that is grounded via the P-type first isolation region 19. As shown by the solid line in the figure, the photodiode 11 and the charge storage layer 13 have potential wells for storing signal charges, and the signal charges are stored in both the photodiode 11 and the charge storage layer 13. The state of being done is shown.

The unit cell of the present embodiment is basically the same as the configuration of the unit cell 8 shown in FIG. 2, but the signal charge generated by photoelectric conversion during light reception is stored in both the photodiode 11 and the charge storage layer 13. As possible, the thickness and concentration of each layer of the semiconductor substrate 10 are devised.
If the signal charge can be stored separately for both the photodiode 11 and the charge storage layer 13 in this way, the maximum stored charge amount of the signal charge is the maximum stored charge amount of the photodiode 11 and the maximum storage charge of the charge storage layer 13. Since this is the sum of the charge amount, it is not necessary to make the maximum accumulated charge amount so large for each of the photodiode 11 and the charge accumulation layer 13.

Therefore, the N-type impurity concentration of the photodiode 11 and the charge storage layer 13 is compared with a structure in which the signal charge is once stored in the photodiode 11 and all the stored signal charges are transferred and stored in the charge storage layer 13. And the potential well depth and the maximum accumulated charge amount can be designed to be small for each region.
In the element isolation region along the line CC ′, a third isolation region 21 provided so as to connect the P-type well 18 and the second isolation region 20 has a potential distribution indicated by a wavy line in the figure. A potential barrier of about 0 V is formed so that the signal charge accumulated in the potential well does not flow out to the potential well of the adjacent pixel.

Thus, in the signal charge accumulation period, potential wells are formed in both the photodiode 11 and the charge storage layer 13, and a potential barrier of about 0 V is formed in the element isolation region between adjacent pixels surrounding each layer. 11 and the electric charge intensity which guides the signal charge generated in the vicinity of the charge storage layer 13 to the potential well can be increased, and the crosstalk failure caused by the diffusion can be prevented.
As shown in FIG. 11B, at time t5 (at one point in the overlapping period in which the backside bias pulse ΦBB is at the low level and the transfer pulse ΦTG is at the high level), the potential from the photodiode 11 toward the charge storage layer 13 is increased. While being monotonously increasing, the transfer pulse ΦTG is at a high level, and although not shown, an electric field for transferring charges from the charge storage layer 13 toward the floating diffusion layer 15 is formed. ing.

  That is, a potential gradient for transferring the signal charge from the photodiode 11 to the floating diffusion layer 15 via the charge storage layer 13 is formed, whereby the photodiode 11 and the charge are charged during the period. The signal charges stored in both storage layers 13 are simultaneously transferred to the floating diffusion layer 215. Also by this transfer method, signal charges can be completely transferred in the same manner as in the above embodiment, so that random noise and the like can be prevented.

As shown in FIG. 11C, since the time t6 is the time after the end of the above-described charge transfer period, the transfer of the signal charge to the floating diffusion layer 15 is completed, and the photodiode 11 and the charge storage layer 13 are completed. Both potential wells are empty (no signal charge is accumulated), and the next signal charge accumulation period is started.
Returning to FIG. 10, the rise of the backside bias pulse ΦBB defines the end time of the signal charge accumulation period in the photodiode 11, and the fall of the transfer pulse ΦTG ends the signal charge accumulation period in the charge storage layer 13. The time is defined, and both times are set to the same time T24, so that the signal charge storage period is completely synchronized between the photodiode 11 and the charge storage layer 13.

  As described above, in the present embodiment, when the selected row is selected, the low level period of the back surface bias pulse ΦBB and the high level period of the transfer pulse ΦTG overlap each other in the horizontal blanking period. Both the photodiode 11 and the charge storage layer 13 are designed such that the N-type impurity concentration is lowered to reduce the depth of the potential well and the maximum stored charge amount. The signal charges accumulated in both can be transferred to the floating diffusion layer 15 without leaving them in the respective regions, and the occurrence of random noise or the like can be prevented.

Further, by decreasing the N-type impurity concentration and reducing the depth of the potential well, the negative applied to the light-receiving surface layer 12 necessary for the potential to monotonously increase from the photodiode 11 toward the charge storage layer 13. The absolute value of the applied voltage can be reduced.
Further, even if incident light passes through the photodiode 11 and is absorbed in the vicinity of the charge storage layer 13 by reducing the thickness of the semiconductor substrate 10, the charge photoelectrically converted in the vicinity of the charge storage layer 13 is also absorbed. 13 potential wells can be used as signal charges. Therefore, the thickness of the semiconductor substrate 10 can be made thinner than the structure in which signal charges are once stored in the photodiode 11 alone. Furthermore, since the potential wells of the photodiode 11 and the charge storage layer 13 are shallow as compared with the structure in which the signal charge is once stored in the photodiode 11 alone, the backside bias pulse ΦBB is simply applied with a voltage having a smaller amplitude. It becomes possible to transfer the signal charge, and there is an effect that power saving can be achieved.

  The period in which the low-level period of the back bias pulse ΦBB overlaps the high-level period of the transfer pulse ΦTG is not limited to the above. However, in order to make the period (exposure period) in which the signal charges accumulated in the photodiode 11 and the charge storage layer 13 occur the same in the photodiode 11 and the charge storage layer 13, the rise of the back bias pulse ΦBB It must be the same as or slower than the falling edge of the pulse ΦTG. If the rise of the back bias pulse ΦBB is earlier than the fall of the transfer pulse ΦTG, a part of the signal charge in the charge storage layer 13 is output in advance, and the signal charge accumulation period is the photodiode 11 and the charge. The storage layer 13 does not match.

In the present embodiment, the configuration of the unit cell 8 is the same as that of FIG. The present invention can also be applied to the second embodiment.
Furthermore, when the driving method shown in FIG. 10 according to the present embodiment is adopted, the present invention can be applied without forming a potential barrier between the photodiode 11 and the charge storage layer 13, and a P-type potential barrier layer can be applied. For example, a low-concentration P-type layer, an I-type layer, or an N-type layer may be used instead of 14. In the configuration in which the potential barrier is not formed, both the photodiode and the charge storage layer may form a storage region, or these may be configured as an integrated storage region. When the above driving method is used, an electric field for sending the signal charge accumulated in the accumulation region to the signal readout circuit is formed, and at the same time, the signal charge is read from the accumulation region, and a part of the accumulated signal charge is obtained. It is possible to efficiently read out the signal charge by preventing the remaining.

In addition, the driving method can be applied even in a structure without the second separation region 20 and the third separation region 21 that partition and separate pixels. This is because charges can be stored in both the photodiode 11 and the charge storage layer 13, so that charges around the charge storage layer 13 can also be used as signal charges and crosstalk hardly occurs.
In each of the above embodiments, the configuration example in the case where the solid-state imaging device according to the present invention is applied to a C-MOS image sensor has been described. However, the present invention is not limited to this, and may be applied to a CCD image sensor, for example. it can.

Further, the driving method is not limited to the solid-state imaging device, and may be a driving method in the solid-state imaging device. Furthermore, the light-receiving surface layer 12 and the potential barrier layer 14 of the first conductivity type provided on the semiconductor substrate 10 are P-type, and the photodiode 11 and charge storage layer of the second conductivity type having the opposite polarity to the first conductivity type. Although the configuration example in which 13 is an N type has been described, the present invention is not limited to this.
For example, the present invention can be applied to a configuration in which the N type and the P type are interchanged, specifically, a configuration in which the first conductivity type is the N type and the second conductivity type is the P type. In this case, the polarity of the bias voltage is also opposite to that described above. For example, during the signal charge transfer period from the photodiode 11 to the charge storage layer 13, the potential is monotonic from the photodiode 11 toward the charge storage layer 13. A decreasing potential distribution is formed.

  The present invention can be used for a solid-state imaging device used in a video camera, a digital still camera, or the like where low noise and low power consumption are desired.

7 Backside bias generation circuit 8 Unit cell 10 Semiconductor substrate 11 Photodiode 12 Light receiving surface layer 13 Charge storage layer 14 Potential barrier layer 15 Floating diffusion layer 16 Transfer gate 17 Storage surface layer 19 First separation region 20 Second separation region 21 Third separation region 26 Wiring layer 31 Electron injection preventing layer 32 Transparent electrode

Claims (16)

A back-illuminated solid-state imaging device in which a plurality of unit cells each having a light receiving surface on the back surface, which is one main surface of a semiconductor substrate, are arranged in a matrix,
Each unit cell is
A light receiving surface layer of a first conductivity type provided at a position closest to the back surface in the thickness direction in the semiconductor substrate;
The signal charges obtained by photoelectrically converting light incident on the light-receiving surface layer are stored in the semiconductor substrate closer to the surface that is the other main surface of the semiconductor substrate than the light-receiving surface layer. A second conductivity type photoelectric conversion region having a polarity opposite to that of the first conductivity type;
A charge storage layer of a second conductivity type that is provided on the side closer to the surface than the photoelectric conversion region in the semiconductor substrate and stores the signal charge transferred from the photoelectric conversion region;
A potential barrier layer of a first conductivity type interposed between the photoelectric conversion region and the charge storage layer in the semiconductor substrate;
A first voltage for preventing signal charges accumulated in the photoelectric conversion region from being transferred to the charge accumulation layer by a potential barrier of the potential barrier layer, and transferring the signal charges to the charge accumulation layer through the potential barrier layer. An electrode for selectively applying a second voltage to the light receiving surface layer,
A solid-state imaging device comprising: A bias circuit for supplying the voltage to the electrode;
The bias circuit includes:
As the first voltage,
Supplying a voltage at which a potential barrier is formed in the potential barrier layer during an accumulation period in which signal charges are accumulated in the photoelectric conversion region;
As the second voltage,
In the signal charge transfer period, when the first conductivity type is P type and the second conductivity type is N type, a voltage whose potential increases monotonously from the photoelectric conversion region toward the charge storage layer is supplied. 2. A voltage whose potential decreases monotonously from the photoelectric conversion region toward the charge storage layer when the first conductivity type is N-type and the second conductivity type is P-type. The solid-state image sensor described in 1. The transfer period is
A predetermined period during the vertical blanking period,
The accumulation period is
3. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is a period excluding the predetermined period and including at least a part of a vertical scanning period including a horizontal scanning period and a horizontal blanking period. The transfer period is
A predetermined period during the horizontal blanking period,
The accumulation period is
The solid-state imaging device according to claim 2, wherein the solid-state imaging element is a period excluding the predetermined period and a period including at least a horizontal scanning period.   5. The solid-state imaging device according to claim 4, wherein at least a part of the transfer period overlaps with a period in which signal charges are output from the charge storage layer, and the transfer period and the output period end substantially at the same time.   6. The solid-state imaging according to claim 1, wherein a storage surface layer of a first conductivity type is provided in a side closer to the surface than the charge storage layer in the semiconductor substrate. element. The electrode is
7. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is a transparent electrode provided on a back surface of the semiconductor substrate and electrically connected to the light receiving surface layer.   The solid-state imaging device according to claim 1, wherein the first voltage is a ground potential. A driving method of a backside illumination type solid-state imaging device in which a plurality of unit cells having a light receiving surface as a back surface which is one main surface of a semiconductor substrate are arranged in a matrix,
Each unit cell is
A light receiving surface layer of a first conductivity type provided at a position closest to the back surface in the thickness direction in the semiconductor substrate;
The signal charges obtained by photoelectrically converting light incident on the light-receiving surface layer are stored in the semiconductor substrate closer to the surface that is the other main surface of the semiconductor substrate than the light-receiving surface layer. A second conductivity type photoelectric conversion region having a polarity opposite to that of the first conductivity type;
A charge storage layer of a second conductivity type that is provided on the side closer to the surface than the photoelectric conversion region in the semiconductor substrate and stores the signal charge transferred from the photoelectric conversion region;
A potential barrier layer of a first conductivity type interposed between the photoelectric conversion region and the charge storage layer in the semiconductor substrate,
The driving method is
In the accumulation period in which the signal charge is accumulated in the photoelectric conversion region, a first voltage for preventing the signal charge accumulated in the photoelectric conversion region from being transferred to the charge accumulation layer by the potential barrier of the potential barrier layer is the light receiving surface layer. A first step applied to
As the second voltage for transferring the signal charge to the charge storage layer through the potential barrier layer during the signal charge transfer period, the first conductivity type is P type, and the second conductivity type is N type. In the case of the above, when the first conductivity type is N-type and the second conductivity type is P-type, the voltage at which the potential monotonously increases from the photoelectric conversion region toward the charge storage layer. A second step of applying to the light receiving surface layer a voltage whose potential monotonously decreases toward the charge storage layer;
A method for driving a solid-state imaging device, comprising: The transfer period is
A predetermined period during the vertical blanking period,
The accumulation period is
The solid-state imaging device driving method according to claim 9, wherein the driving period is a period excluding the predetermined period and includes at least a part of a vertical scanning period including a horizontal scanning period and a horizontal blanking period. The transfer period is
A predetermined period during the horizontal blanking period,
The accumulation period is
The method for driving a solid-state imaging device according to claim 9, wherein the driving period is a period excluding the predetermined period and includes at least a horizontal scanning period.   12. The solid-state imaging device according to claim 11, wherein at least a part of the transfer period overlaps with a period in which signal charges are output from the charge storage layer, and the transfer period and the output period end substantially simultaneously. Driving method.   The solid-state imaging device driving method according to claim 9, wherein the first voltage is a ground potential. In the semiconductor substrate, the light incident on the light receiving surface layer of the first conductivity type provided at the position closest to the back surface which is one main surface of the semiconductor substrate in the thickness direction is photoelectrically converted, and the photoelectrically converted signal charge Is stored in a second conductivity type accumulation region having a polarity opposite to that of the first conductivity type, which is provided in the semiconductor substrate closer to the surface which is the other main surface of the semiconductor substrate than the light receiving surface layer. In the signal readout period, a plurality of unit cells are read out from the accumulation region by a readout circuit provided closer to the surface than the light receiving surface layer in the signal readout period. A back-illuminated solid-state image sensor driving method comprising:
During the signal charge accumulation period,
Applying a ground potential to the light receiving surface layer as a first voltage for accumulation of signal charge;
It is a period excluding the accumulation period, and in a predetermined period in the horizontal blanking period,
When the first conductivity type is P type and the second conductivity type is N type, a second voltage having a lower potential than the first voltage is applied to the light receiving surface layer,
When the first conductivity type is N-type and the second conductivity type is P-type, a second voltage having a higher potential than the first voltage is applied to the light-receiving surface layer. Driving method. The accumulation period is
The method for driving a solid-state imaging device according to claim 14, wherein the period includes at least a horizontal scanning period.   16. The method for driving a solid-state imaging device according to claim 14, wherein at least a part of the predetermined period overlaps with the signal readout period, and the predetermined period and the signal readout period end substantially at the same time.

Images