JP5245267B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device.

  A solid-state imaging substrate obtained by arranging pixels including a solid-state imaging device in a matrix is mounted on, for example, a mobile phone. Examples of the solid-state imaging substrate include a solid-state imaging substrate including a CCD (carrier coupling element) type solid-state imaging device and a solid-state imaging substrate including a MOS type solid-state imaging device. The CCD type solid-state imaging substrate has excellent image quality, and the MOS type solid-state imaging substrate has low power consumption and low process cost. In recent years, a MOS type solid-state imaging substrate of a threshold voltage modulation method that has both high image quality and low power consumption has been proposed. A threshold voltage modulation type MOS solid-state imaging substrate is disclosed in, for example, Patent Document 1.

  The solid-state imaging substrate obtains an image output by arranging pixels in a matrix and repeating a state in which each pixel includes clear, accumulation, and readout. The solid-state imaging substrate disclosed in Patent Document 1 is hereinafter referred to as modulation because each pixel indicates a photodiode for accumulation and readout (operation indicating extraction of threshold modulation by light-generated carriers). ).

FIG. 8 is a schematic wiring diagram of the solid-state imaging substrate 100 in which the pixels 3 including the VMIS type solid-state imaging device 120 in which the photodiode PD and the modulation transistor TM disclosed in Patent Document 1 are integrated are arranged in a matrix. (It is also used as an equivalent circuit diagram showing a state when strong light SL is incident on a structure that does not use a transfer transistor TS described later.) Outputs from the source section 7 of the pixels 3 arranged in the same column are taken out through a common source line 66. By supplying an ON signal to one of the gate lines 67, a signal from the source unit 7 of one pixel 3 connected to the gate line 67 to which the ON signal is supplied among the pixels 3 connected to the common source line 66. It is possible to read only. In this case, a potential higher than that of the non-selection ring gate electrode 6a of the non-selection modulation transistor TMa of the non-selection pixel 3a is applied to the ring gate electrode 6 of the modulation transistor TM of the pixel 3 to be read (selected). The pixel 3 is selected.
As an ON signal, the output of the source part 7 of the modulation transistor TM to which a high gate potential is applied becomes higher than the output of the non-selection source part 7a of the non-selection modulation transistor TMa to which a low gate potential is applied. The output from the source section 7 of the selected pixel 3 corresponding to the gate line 67 selected by the ON signal can be obtained from the source line 66x.
Here, as a signal extraction procedure in FIG. 8, attention is paid to the source line 66x, for example. Dominated by the potential of the source line 66x governed by the potential supplied from the source portion 7 of the selected pixel 3 after accumulating photogenerated carriers and the potential output by the source portion 7 of the pixel 3 after clearing. The difference from the potential of the source line 66x to be extracted is extracted. By extracting the difference between the potential of the source line 66x after the accumulation and the potential of the source line 66x after the clearing, it is possible to cancel the variation caused by the characteristic distribution such as the threshold value of each pixel 3. Therefore, it is possible to extract an image signal having a higher SN ratio.

Japanese Patent No. 3313683 Japanese Patent No. 372002014

  When performing the difference extraction, in the configuration presented in Patent Document 1, the pixel 3 is selected by the selected gate line 67 as shown in FIG. 8, and the potential from the source unit 7 of the selected pixel 3 is set. By transmitting to each source line 66, the potential from the source portion 7 of the selected pixel 3 is detected. Here, when strong light SL is incident on the non-selected photodiode PDa of the non-selected pixel 3a connected to the source line 66x, a potential larger than the potential from the source portion 7 of the selected pixel 3 may be generated. . This is because the potential of the non-selected source portion 7a of the non-selected modulation transistor TMa rises and exceeds the source potential of the modulation transistor TM selected by shifting the source potential by applying the potential to the ring gate electrode 6. It is thought to occur.

In this case, the potential of the non-selected source unit 7a belonging to the non-selected pixel 3a to which the strong light SL is incident becomes higher than the potential of the source unit 7 after clearing. That is, the potential of the source line 66x of the selected pixel 3 is higher than the potential of the source portion 7 of the selected pixel 3 after clearing, and reaches the potential of the unselected source portion 7a of the unselected pixel 3a. It will only drop. Therefore, in this case, the difference between the potential of the source unit 7 after accumulating the photogenerated carriers output from the source unit 7 of the selected pixel 3 and the potential of the source unit 7 after clearing is I can't get it.
Instead, since the difference between the potential of the source unit 7 after accumulating the photogenerated carriers and the potential of the non-selected source unit 7a of the non-selected pixel 3a irradiated with the strong light SL is output, the light intensity is increased. The output appears to be small, and a phenomenon called black smear occurs.
In order to prevent this black smear, a technique for forming a pixel using three transistors as shown in Patent Document 2 has been proposed. However, since the number of transistors per pixel increases to three, the aperture ratio decreases. There is a problem that the photosensitivity is lowered.
Accordingly, an object of the present invention is to provide a solid-state imaging device capable of suppressing an increase in the number of transistors per pixel and preventing the occurrence of black smear.

  In the present application, “upper” is defined as a direction away from an object constituting the substrate through the first surface of the substrate. And “down” is defined as pointing in the opposite direction to “up”. The “aperture ratio” is defined as the ratio of the area of a region capable of generating photogenerated carriers to the area of a pixel.

In order to solve the above problems, a solid-state imaging device according to the present invention includes a first conductivity type substrate, a second conductivity type PD well portion disposed on the first surface side of the substrate, and a first conductivity type. A junction well having a second conductivity type and connected to the PD well portion, the junction depth being shallower than the junction depth of the PD well portion. A TR well portion having a depth; a modulation well portion having a first conductivity type; connected to the collection well portion; positioned in the TR well portion; and disposed in the modulation well portion in plan view; A source part including a region having two conductivity types and in contact with the first surface of the substrate; a gate electrode disposed in a region covering at least a part of the modulation well part in plan view; and surrounding the source part; The gate electrode and the first surface of the substrate; A gate insulating layer disposed at a position sandwiched therebetween, and disposed in at least a part of a position facing the source portion with the gate electrode interposed therebetween in plan view, and having a second conductivity type, A modulation transistor including a drain portion including a region in contact with the first surface, and a pair of the electrically connected source portion and the source, the two modulation transistors arranged in adjacent pixels as a set A transmission transistor is connected between the lines, and is connected to each other, and controls a conduction state between the source unit and the source line by a selection signal.
In order to solve the above problems, a solid-state imaging device according to the present invention includes a first conductivity type substrate, a second conductivity type PD well portion disposed on the first surface side of the substrate, and a first conductivity type. A junction well having a second conductivity type and connected to the PD well portion, the junction depth being shallower than the junction depth of the PD well portion. A TR well portion having a depth; a modulation well portion having a first conductivity type; connected to the collection well portion; positioned in the TR well portion; and disposed in the modulation well portion in plan view; A source part having a two-conductivity type and including a region in contact with the first surface of the substrate and a region covering at least a part of the modulation well part in a plan view and surrounding a part of the source part In cooperation with the gate electrode in plan view. And an element isolation layer surrounding the source portion, a gate insulating layer disposed at a position sandwiched between the gate electrode and the first surface of the substrate, and sandwiching the gate electrode in plan view, A modulation transistor including at least a portion disposed at a position facing the source portion and having a second conductivity type and a drain portion including a region in contact with the first surface of the substrate; and disposed in an adjacent pixel. A pair of the two modulation transistors as a set, the set of electrically connected source units, and one set connected between the source lines, and conduction between the source unit and the source line by a selection signal And a transmission transistor for controlling the state.
In the solid-state imaging device, the layout of the modulation transistor and the photodiode of the pixel is arranged by mirror-inverting in a direction intersecting the source line for each column, and the modulation transistor is arranged in an adjacent region. A transmission transistor is preferably arranged.
In the solid-state imaging device, the modulation transistor and the photodiode layout of the pixel are mirror-inverted in a direction intersecting the source line for each column, and the modulation transistor at a position sandwiching the source line and the It is preferable that the layout of the photodiodes is arranged by mirror-inverting each row in a direction aligned with the source line, and the transmission transistors are arranged in a region where the modulation transistors are arranged close to each other.
In the solid-state imaging device, the region where the photodiode is located includes the interface between the substrate surface including the substrate surface and the collection well portion and / or the interface between the gate insulating layer and the substrate. Preferably, a pinning layer having a second conductivity type is further included between the gate insulating layer and the modulation well.
In the solid-state imaging device, in the modulation well portion, in a region overlapping with at least a part of the gate electrode in plan view, a carrier pocket portion having an impurity concentration of the first conductivity type higher than that of the surrounding modulation well portion It is preferable that it is further included.
In order to solve the above problems, a solid-state imaging device according to the present invention includes a first conductivity type substrate, a second conductivity type PD well portion disposed on the first surface side of the substrate, and a first conductivity type. A junction well having a second conductivity type and connected to the PD well portion, the junction depth being shallower than the junction depth of the PD well portion. A TR well portion having a depth; a modulation well portion having a first conductivity type; connected to the collection well portion; positioned in the TR well portion; and disposed in the modulation well portion in plan view; A source part including a region having two conductivity types and in contact with the first surface of the substrate; a gate electrode disposed in a region covering at least a part of the modulation well part in plan view; and surrounding the source part; The gate electrode and the first surface of the substrate; A gate insulating layer disposed at a position sandwiched therebetween, and disposed in at least a part of a position facing the source portion with the gate electrode interposed therebetween in plan view, and having a second conductivity type, A modulation transistor including a drain portion including a region in contact with the first surface, and a pair of the electrically connected source portion and the source, the two modulation transistors arranged in adjacent pixels as a set A transmission transistor is connected between the lines, and is connected to each other, and controls a conduction state between the source unit and the source line by a selection signal.

According to this configuration, since only one and a half of the transistors are arranged in each pixel (one transmission transistor is arranged for two modulation transistors in addition to one modulation transistor), a high aperture ratio is secured. can do.
In addition, since the two adjacent source parts are paired to have one transmission transistor and connected to the source line via the transmission transistor, the black smear generated in one source part is the other of the other pair. It can be limited only to propagation to the source part of the transistor. Black smear propagation to the source line is suppressed by the transfer transistor interposed between the source part of the paired transistor and the source line, so that the black smear propagation can be suppressed with the aperture ratio secured. .

  The solid-state imaging device according to the present invention includes a first conductivity type substrate, a second conductivity type PD well portion disposed on the first surface side of the substrate, and a first conductivity type. A TR well portion having a photodiode and a second conductivity type including a collection well portion located in the well portion and having a junction depth shallower than a junction depth of the PD well portion connected to the PD well portion A modulation well portion connected to the collection well portion and located in the TR well portion, and disposed in the modulation well portion in plan view, and having a second conductivity type A source part including a region in contact with the first surface of the substrate; and a gate electrode disposed in a region covering at least a part of the modulation well part in a plan view; Enclosing the source part in cooperation with the gate electrode. An element isolation layer, a gate insulating layer disposed at a position sandwiched between the gate electrode and the first surface of the substrate, and a position facing the source portion across the gate electrode in plan view A modulation transistor including at least a portion, a drain portion having a second conductivity type and including a region in contact with the first surface of the substrate, and two modulation transistors disposed in adjacent pixels. As a set, a pair of electrically connected source units, and a transmission transistor connected between source lines, one per set, and controlling a conduction state between the source unit and the source line by a selection signal; , Including.

According to this configuration, since only one and a half of the transistors are arranged in each pixel (one transmission transistor is arranged for two modulation transistors in addition to one modulation transistor), a high aperture ratio is secured. can do.
In addition, since a pair of adjacent two source portions has one transfer transistor and is connected to the source line via the transfer transistor, the black smear generated in one source portion is the other that forms the pair. It is possible to limit the propagation to the source part of the transistor. Black smear propagation to the source line is suppressed by the transfer transistor interposed between the source part of the paired transistor and the source line, so that the black smear propagation can be suppressed with the aperture ratio secured. .
In addition, the source portion is enclosed so as to be electrically independent by using the gate electrode and the element isolation layer in combination. By using the element isolation layer in combination to make the source part electrically independent, the degree of freedom in pattern layout is increased. Therefore, when performing pattern layout including a transfer transistor, the degree of freedom of the shape of the photodiode is also improved, so that it can be laid out in a shape with higher light receiving efficiency, and a solid-state imaging device constituting a highly sensitive solid-state imaging device Can be provided.

  In the solid-state imaging device according to the present invention, the layout of the pixels having a common source line is arranged in a mirror image inverted in a direction intersecting the source line for each column, and the modulation transistors are arranged close to each other. A transmission transistor is arranged in the region.

  According to this configuration, since the source is arranged in a region where the modulation transistors are arranged close to each other, the wiring length connecting the two source portions can be suppressed. Therefore, the wiring area can be reduced and the opening can be made large.

  In addition, the electro-optic substrate according to the present invention is in a position to sandwich the source line in addition to an arrangement in which the layout of the pixels having the common source line is mirror-inverted in a direction intersecting the source line for each column. The layout of the pixels is arranged by mirror-inverting in a direction aligned with the source line for each row, and a transmission transistor is arranged in a region where the modulation transistors are arranged close to each other.

  According to this configuration, since the gate contact of the transmission transistor can be shared, the area of the transmission transistor can be further reduced, and the opening can be further increased.

  Further, in the solid-state imaging device according to the present invention, in the region where the photodiode is located, between the substrate surface including the substrate surface and the collection well portion, and / or the gate insulating layer and the substrate, A pinning layer having a second conductivity type is further included between the gate insulating layer including the interface and the modulation well.

  According to this configuration, generation / recombination centers that are present in a large amount on the surface of the substrate compared with the inside of the substrate are filled with the pinning layer having the second conductivity type, thereby suppressing generation of noise carriers and higher image quality. A solid-state imaging device constituting a solid-state imaging substrate can be provided.

  In the solid-state imaging device according to the present invention, an impurity concentration of the first conductivity type higher than that of the surrounding modulation well portion is formed in a region overlapping with at least a part of the gate electrode in plan view in the modulation well portion. It further includes a carrier pocket portion having the same.

  According to this configuration, the carrier pocket having the first conductivity type impurity concentration higher than that of the peripheral modulation well portion is formed in a region overlapping with at least a part of the gate electrode in plan view. When the modulation well portion of the modulation transistor is depleted using this structure, a larger potential well is formed in a region having a high impurity concentration and a function of drawing photogenerated carriers is provided. Therefore, it is possible to provide a solid-state imaging device that constitutes a solid-state imaging device having higher image quality when light-generated carriers generated by the photodiode are efficiently collected in the carrier pocket of the modulation transistor and particularly when the light intensity is weak.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. As an explanation procedure, a basic structure of a VMIS type solid-state imaging device having a ring gate electrode structure (having a source part surrounded by a gate electrode) will be described first. Next, the basic structure of a substrate modulation MOS type (having a source part surrounded by a gate electrode and an element isolation layer) solid-state imaging device will be described. Then, the reason for the occurrence of black smear will be described, and the operation of the solid-state imaging device provided with a transfer transistor to suppress this black smear will be described. Here, an example in which an NMOS structure is used for the VMIS type and the substrate modulation MOS type solid-state imaging device will be described. Here, a PMOS structure may be used instead of the NMOS structure. In this case, the same operation can be performed by inverting the polarity of the impurity and the polarity of the driving potential.

<Basic structure of VMIS type solid-state imaging device>
Hereinafter, the basic structure of the VMIS type solid-state imaging device will be described with reference to FIGS. FIG. 1A is a partial plan view of a solid-state imaging substrate 100 in which pixels 3 including a VMIS type solid-state imaging device 120 are arranged in an array. FIG. 1B is a cross-sectional view showing a cross-sectional structure of the VMIS type solid-state imaging device 120 obtained by cutting FIG. 1A along the line AA ′. Hereinafter, the basic structure of the VMIS type solid-state imaging device will be described with reference to FIGS.

  As shown in FIG. 1A, the photodiode PD and the modulation transistor TM are provided adjacent to each other in the pixel 3. As the modulation transistor TM, for example, an N-channel depletion MOS transistor is used. Further, a VMIS type solid-state imaging device 120 and a transfer transistor TS are arranged in the pixel 3. The transfer transistor TS can use, for example, a PMOS structure. The role of the transfer transistor TS will be described later. Note that the metal wiring 60 shown in FIG. 1A is omitted in the cross-sectional view shown in FIG.

  In the photodiode PD region which is a photoelectric conversion element, an opening region 2 is disposed on the surface of the substrate 1, and a collection well portion 4 that collects photogenerated carriers generated by the photoelectric conversion element at a relatively shallow position on the surface of the substrate 1. Is arranged. An N-type diffusion layer is disposed as a pinning layer 32 between the collection well 4 and the surface of the substrate 1.

The modulation well portion 5 is disposed adjacent to the collection well portion 4. Then, the light generation carriers stored in the collection well portion 4 are transferred to the modulation well portion 5 located in the modulation transistor TM region. By storing photogenerated carriers in the modulation well section 5, the threshold value of the modulation transistor TM changes, and the threshold value of the modulation transistor TM depends on the amount of accumulated photogenerated carriers (the amount of light incident on the photodiode PD region). Take the corresponding value.
On the modulation well portion 5, a ring gate electrode 6, which is a ring-shaped gate electrode, is disposed on the surface of the substrate 1 through a gate insulating layer 11. An N-type diffusion layer 27 constituting a channel is disposed in the vicinity of the surface of the substrate 1 covered with the gate insulating layer 11. The N-type diffusion layer 27 also functions as the pinning layer 32 at the same time. The N type diffusion layer 27 constituting the channel is connected to the source part 7 and the drain part 8. Each VMIS type solid-state imaging device 120 is separated by an N-type element isolation region 115.

  In a region surrounded by the ring gate electrode 6, a source portion 7 that is a high concentration N-type region is disposed. An N-type drain portion 8 is disposed so as to surround at least a part of the ring gate electrode 6. A drain contact region 12, which is a high concentration N-type region, is disposed at a predetermined position of the drain portion 8.

  The modulation well section 5 controls the threshold voltage of the modulation transistor TM. In the modulation well portion 5, a carrier pocket 10 constituting a P-type high concentration region is disposed below the ring gate electrode 6. The modulation transistor TM includes a modulation well portion 5, a carrier pocket 10, a ring gate electrode 6, a source portion 7 and a drain portion 8. Then, the threshold voltage of the channel changes according to the photogenerated carriers accumulated in the modulation well portion 5 (carrier pocket 10).

  When the drain portion 8 and the pinning layer 32 are biased to a positive potential by applying a drain potential, a depletion layer is formed from the boundary surface between the pinning layer 32 and the collection well portion 4 below the opening region 2 of the photodiode PD. It spreads over the entire collection well 4 and reaches the PD well 21. On the other hand, a depletion layer extends from the boundary surface between the substrate 1 and the PD well portion 21 to the entire PD well portion 21 and reaches the collection well portion 4. In the depletion layer, photogenerated carriers are generated by the light incident through the opening region 2. As described above, the generated light generation carriers are collected in the collection well section 4. The photogenerated carriers collected in the collection well portion 4 are transferred to the modulation well portion 5 and held in the carrier pocket 10. As a result, the source potential of the modulation transistor TM is in accordance with the amount of photogenerated carriers transferred to the modulation well portion 5, that is, the incident light to the photodiode PD.

  The PD well portion 21 is disposed at a relatively deep position on the substrate 1. A P-type collection well portion 4 is disposed in the PD well portion 21. The PD well portion 21 is disposed up to a relatively deep position of the substrate 1 so that light having a long wavelength (for example, red) having a large penetration depth in the substrate 1 can be photoelectrically converted.

  On the other hand, a P-type buried layer 23 is disposed in the modulation transistor TM region. The depth occupied by the TR well portion 50 by the P-type buried layer 23 is limited to a relatively shallow position of the substrate 1. Since the TR well portion 50 is formed at a relatively shallow position, the electric field strength in the modulation well portion 5 can be increased when a potential is applied to the ring gate electrode 6, and the potential is applied to the ring gate electrode 6. As a result, the photogenerated carriers accumulated in the modulation well portion 5 can be emitted to the substrate 1.

  Here, the pinning layer 32 can be omitted as a basic structure of the VMIS type solid-state imaging device 120. The carrier pocket 10 can also be omitted. When the carrier pocket 10 is omitted, charges are accumulated in the modulation well portion 5, and the threshold voltage is controlled by the charges. By omitting the pinning layer 32 and / or the carrier pocket 10, the manufacturing process can be shortened. In particular, image noise is not a big problem for applications that handle subjects with relatively high illuminance. By omitting these configurations, it is possible to provide a VMIS type solid-state imaging device 120 which is shortened in TAT by shortening the manufacturing process, reduced in defective rate, and cost is reduced accordingly.

<Basic structure of substrate modulation MOS type solid-state imaging device>
The basic structure of the substrate modulation MOS type solid-state imaging device will be described below with reference to FIGS. 2 (a) and 2 (b). FIG. 2A is a partial plan view of the solid-state imaging substrate 100 in which the pixels 3 including the substrate modulation MOS type solid-state imaging device 120b are arranged in an array. FIG. 2B is a cross-sectional view showing a cross-sectional structure of the substrate modulation MOS type solid-state imaging device 120b obtained by cutting FIG. 2A along the line AA ′. The basic structure of the substrate modulation MOS type solid-state imaging device will be described below with reference to FIGS. 2 (a) and 2 (b).

  As shown in FIG. 2A, the photodiode PD and the modulation transistor TM are provided adjacent to each other in the pixel 3. As the modulation transistor TM, for example, an N-channel depletion MOS transistor is used. Further, a substrate modulation MOS type solid-state imaging device 120b and a transfer transistor TS are disposed in the pixel 3. The transfer transistor TS can use, for example, a PMOS structure. The role of the transfer transistor TS will be described later. Note that the metal wiring 60 shown in FIG. 2A is omitted in the cross-sectional view shown in FIG.

  In the photodiode PD region which is a photoelectric conversion element, an opening region 2 is disposed on the surface of the substrate 1, and a collection well portion 4 that collects photogenerated carriers generated by the photoelectric conversion element at a relatively shallow position on the surface of the substrate 1. Is arranged. An N-type diffusion layer is disposed as the pinning layer 32 between the collection well portion 4 and the surface of the substrate 1.

The modulation well portion 5 is disposed adjacent to the collection well portion 4. Then, the light generation carriers stored in the collection well portion 4 are transferred to the modulation well portion 5 located in the modulation transistor TM region. By storing photogenerated carriers in the modulation well portion 5, the threshold value of the modulation transistor TM is controlled, and the threshold value of the modulation transistor TM depends on the amount of accumulated photogenerated carriers (the amount of light incident on the photodiode PD region). Take the corresponding value.
On the modulation well portion 5, an L-shaped gate electrode 6 b is disposed on the surface side of the substrate 1 via a gate insulating layer 11, and in a region surrounded by the gate electrode 6 b and the element isolation layer 52 by LOCOS. Is provided with a source portion 7 which is a high concentration N-type region. Here, the element isolation layer 52 is not limited to LOCOS, and may have, for example, an STI structure.

  An N-type diffusion layer 27 constituting a channel is disposed in the vicinity of the surface of the substrate 1 covered with the gate insulating layer 11. At the same time, the N-type diffusion layer 27 also functions as the pinning layer 32. The N type diffusion layer 27 constituting the channel is connected to the source part 7 and the drain part 8. Each substrate modulation MOS type solid-state imaging element 120 b is separated by an N-type element isolation region 115 and an element isolation layer 52.

An N-type drain portion 8 is disposed at a position facing the source portion 7 through the gate electrode 6b. A drain contact region 12, which is a high concentration N-type region, is disposed at a predetermined position of the drain portion 8.
The modulation well section 5 controls the threshold voltage of the modulation transistor TM. In the modulation well portion 5, a carrier pocket 10 constituting a P-type high concentration region is disposed below the gate electrode 6b. The modulation transistor TM includes a modulation well portion 5, a carrier pocket 10, an element isolation layer 52, a gate electrode 6b, a source portion 7 and a drain portion 8. Then, the threshold voltage of the channel changes according to the photogenerated carriers accumulated in the modulation well portion 5 (carrier pocket 10).

  When the drain portion 8 and the pinning layer 32 are biased to a positive potential by applying a drain potential, a depletion layer is formed from the boundary surface between the pinning layer 32 and the collection well portion 4 below the opening region 2 of the photodiode PD. It spreads over the entire collection well 4 and reaches the PD well 21. On the other hand, a depletion layer extends from the boundary surface between the substrate 1 and the PD well portion 21 to the entire PD well portion 21 and reaches the collection well portion 4. In the depletion layer, photogenerated carriers are generated by the light incident through the opening region 2. As described above, the generated light generation carriers are collected in the collection well section 4. The photogenerated carriers collected in the collection well portion 4 are transferred to the modulation well portion 5 and held in the carrier pocket 10. As a result, the source potential of the modulation transistor TM is in accordance with the amount of photogenerated carriers transferred to the modulation well portion 5, that is, the incident light to the photodiode PD.

  The PD well portion 21 is disposed at a relatively deep position on the substrate 1. A P-type collection well section 4 is disposed on the PD well section 21. A pinning layer 32 including an N type diffusion layer is disposed on the substrate surface side on the collection well portion 4. The PD well portion 21 is disposed up to a relatively deep position of the substrate 1 so that light having a long wavelength (for example, red) having a large penetration depth in the substrate 1 can be photoelectrically converted.

  On the other hand, a P-type buried layer 23 is disposed in the modulation transistor TM region. The TR well portion 50 is limited to a relatively shallow position of the substrate 1 by the P-type buried layer 23. Since the TR well portion 50 is formed at a relatively shallow position, the electric field strength in the modulation well portion 5 can be increased when a potential is applied to the gate electrode 6b, and the potential is applied to the gate electrode 6b. It is possible to discharge the photogenerated carriers accumulated in the modulation well portion 5 to the substrate 1.

  Here, the pinning layer 32 can be omitted as a basic structure of the substrate modulation MOS type solid-state imaging device 120b. The carrier pocket 10 can also be omitted. When the carrier pocket 10 is omitted, charges are accumulated in the modulation well portion 5, and the threshold voltage is controlled by the charges. By omitting the pinning layer 32 and / or the carrier pocket 10, the manufacturing process can be shortened. In particular, image noise is not a big problem for applications that handle subjects with relatively high illuminance. By omitting these configurations, it is possible to provide a substrate modulation MOS type solid-state imaging device that reduces TAT by shortening the manufacturing process, reduces the defect rate, and lowers the cost.

<Configuration of solid-state imaging device>
Next, the configuration of the solid-state imaging device according to the present embodiment will be described with reference to FIGS. The description here is for the case of using a VMIS type solid-state image pickup device. However, in the case of using a substrate modulation MOS type solid-state image pickup device, the VMIS type solid-state image pickup device and the substrate modulation MOS type solid-state image pickup device are replaced. Can respond. For example, the structure shown in FIG. 2A can be used as the planar layout diagram when the substrate modulation MOS type solid-state imaging device is used.

  The solid-state imaging substrate 100 is configured by arranging pixels 3 including a VMIS type solid-state imaging device 120 in a matrix. The solid-state imaging substrate 100 includes, for example, a 640 × 480 pixel 3 and a region (OB region) for optical black (OB). Including the OB region, the solid-state imaging substrate 100 includes, for example, 712 × 500 pixels 3.

The solid-state imaging device 130 is disposed in the pixel 3 and includes a photodiode PD that performs photoelectric conversion, a modulation transistor TM for detecting and reading an optical signal, and a transmission transistor TS. The photodiode PD generates photogenerated carriers corresponding to incident light and collects them in the collection well section 4. The photogenerated carriers collected in the collection well portion 4 are transferred to the carrier pocket 10 in the modulation well portion 5 for threshold modulation of the modulation transistor TM.
In the modulation transistor TM, the back gate potential is changed by accumulating photogenerated carriers in the carrier pocket 10, and the threshold voltage of the modulation transistor TM is changed in accordance with the amount of photo generated carriers in the carrier pocket 10. As a result, the source potential of the modulation transistor TM corresponds to the photogenerated carrier in the carrier pocket 10, that is, corresponds to the incident light amount of the photodiode PD.
The transmission transistor TS includes a transmission TR gate electrode 70, a transmission TR source part 71, and a transmission TR drain part 72 (see FIG. 3). By controlling the gate potential of the transmission TR gate electrode 70, conduction / cutoff of the transmission TR source part 71 and the transmission TR drain part 72 is controlled. Therefore, the connection state between the source part 7 of the modulation transistor TM connected to the transmission TR drain part 72 and the source line 66 connected to the transmission TR source part 71 can be controlled.
As described above, in the pixel 3, the drive signal is applied to the transmission TR gate electrode 70 of the transmission transistor TS, the ring gate electrode 6 of the modulation transistor TM, the source unit 7, and the drain unit 8, thereby storing, transferring, modulating, and An operation such as clearing is performed.

  Next, a black smear generation mechanism and a mechanism for preventing the generation will be described with reference to FIG. FIG. 3 is an equivalent circuit diagram of the solid-state imaging substrate 100 shown in FIG. Here, for convenience, the directions such as horizontal and vertical are shown together with the positional relationship in FIG.

  The pixel 3 in which the solid-state imaging device 130 including the VMIS type solid-state imaging device 120 and the transfer transistor TS is arranged includes a plurality of source lines 66 arranged in the vertical direction and a plurality of gate lines 67 arranged in the horizontal direction. It is provided corresponding to the intersection. Further, the ring gate electrodes 6 of the modulation transistors TM included in the pixels 3 arranged in the horizontal direction are each connected to a gate line 67. The common drain lines 68 are arranged in the vertical direction, and are arranged so that all the potentials of the drain portions 8 (see FIG. 1B) included in the pixels 3 arranged in a matrix have a common potential. The source part 7 of the modulation transistor TM included in the pixel 3 is connected to the source line 66 via the transmission TR gate electrode 70 of the transmission transistor TS. In this case, the modulation transistor TM operates as a source follower. Here, the transmission transistor TS uses a PMOS structure, and the transmission transistor TS is turned on by lowering the potential of the transmission TR gate line 69.

  By supplying an ON signal to one of the gate lines 67 and further supplying an ON signal (low potential signal due to the PMOS structure) to the transmission TR gate line 69 of the transmission transistor TS, the gate line to which the ON signal is supplied The pixels 3 commonly connected to 67 are simultaneously selected. A pixel signal is output from each source section 7 of these selected pixels 3 via the transfer transistor TS. Then, by supplying an ON signal to the gate line 67 while sequentially shifting, the pixel signal from the pixel 3 to which the ON signal is supplied is simultaneously read from the source line 66 for one row of the gate line 67.

  In order to remove variations and various noises of each pixel 3, in the read operation, following the read operation of the optical signal of the selected row, the potential application state to the pixel 3 of the non-selected row is left as it is and the selection is performed. Clear pixel 3 in the row. Subsequently, the threshold voltage in the cleared state is read out. Then, a difference signal between the threshold voltage corresponding to the light generation carrier amount and the threshold voltage in the cleared state is calculated, and output as a video signal, thereby canceling variations caused by the distribution of thresholds of each pixel 3 and the like. This processing enables extraction of an image signal having a high S / N ratio.

  FIG. 4 is a graph showing the output potential according to the light intensity. Points a and b indicate the output potential Vsa and Vnb of the pixel 3 due to the noise component after clearing the output potential of the pixel 3 in the selected row (see FIG. 3; the same applies hereinafter) to which a normal amount of incident light is incident. Yes. Point c indicates the output potential Vsc based on the non-selected pixel 3a on which the normal amount of incident light is incident. Point d indicates the output potential Vsd based on the non-selected pixel 3a when the strong light SL is incident. When a normal amount of incident light is incident on the pixels 3 in the selected row, a signal having a potential difference of (Vsa−Vnb) (range of arrows) is obtained as the pixel signal of the pixel 3 in the selected row. As described above, when light of normal intensity is irradiated to the pixels 3 in the non-selected row, the output potential Vsc at the point c becomes lower than the output potential Vnb at the point b, which affects the operation of the selected row. Not give.

  Here, a generation mechanism of black smear that occurs when the transmission transistor TS is not used will be described. First, in a predetermined column, when a normal amount of incident light is incident on the pixels 3 in the selected row and strong light SL is incident on one of the non-selected pixels 3a, the pre-clearing based on the pixels 3 in the selected row is performed. In the state, the output potential Vsa is output. On the other hand, the output potential Vnb after clearing the selected row is lower than the output potential Vsd based on the non-selected pixel 3a when the strong light SL is incident. Since the source sections are commonly connected in the same column, a higher output potential Vsd is obtained as a pixel signal after clearing when modulation (reading) after clearing is performed. Therefore, a signal (Vsa−Vsd) is output as the pixel signal of the pixel 3 in the selected row. (Vsa−Vsd) is a smaller value than (Vsa−Vnb), and the display based on this pixel signal output is black.

  FIG. 8 is an equivalent circuit diagram showing a state when strong light SL is incident on a structure that does not use the transfer transistor TS. When strong light is incident on the non-selected pixel 3a, all the differential signals from the pixel 3 connected to the source line 66x are from the original (Vsa−Vnb) until the non-selected pixel 3a is cleared. Since the value of (Vsa−Vsd), which is also a small value, takes a black smear in the vertical direction on the screen display.

  On the other hand, in the present embodiment, as shown in FIG. 3, the source part 7 of the modulation transistor TM has only the potential of the source part 7 of the two modulation transistors TM selected by the transmission transistor TS as the source line 66. Is transmitted to. For this reason, strong light SL is incident on the non-selected photodiode PDa, and the output signal from the non-selected source unit 7a of the non-selected modulation transistor TMa is higher than the source unit 7 after clearing the selected modulation transistor TM. Even in the case, transmission to the source line 66x can be prevented by the non-selective transmission transistor TSa. Therefore, it is possible to prevent the occurrence of black smear that affects the entire screen.

<Example layout>
FIG. 1A shows a layout example when a VMIS type solid-state imaging device is used. In this layout, the layout of the pixels 3 having the common source line 66 is arranged so as to be mirror-inverted for each column with respect to the direction intersecting the source line 66 (in this case, orthogonal). The source portions 7 of the modulation transistors TM that are close to each other as the mirror image is inverted are connected to each other by a metal wiring 60 containing, for example, aluminum. The connected metal wiring 60 and the source line 66 are connected via the transmission transistor TS. In this case, the metal wiring 60 can be disposed avoiding the opening of the photodiode PD, and the transfer transistor TS can be disposed while suppressing a reduction in the area of the opening of the photodiode PD.

  FIG. 2A shows a layout example in the case of using a substrate modulation MOS type solid-state imaging device. In this layout, the layout of the pixels 3 having the common source line 66 is arranged so as to be mirror-inverted for each column with respect to the direction intersecting the source line 66 (in this case, orthogonal). The source portions 7 of the two modulation transistors TM that are close to each other as the mirror image is inverted are connected to each other by a metal wiring 60 using a metal including aluminum, for example. The connected metal wiring 60 and the source line 66 are connected via the transmission transistor TS. Similarly, in this layout example, the reduction in the area of the opening of the photodiode PD can be suppressed. Further, since the source part 7 and the drain part 8 are separated by using the gate electrode 6b and the element isolation layer 52, the degree of freedom in layout becomes high. By using the ring gate electrode 6 shown in FIG. A higher aperture ratio can be obtained compared to the case where the portion 8 is separated.

FIG. 7 shows another layout example in the case of using the VMIS type solid-state imaging device. In this layout, the layout of the pixels 3 having the common source line 66 is mirror-inverted for each column with respect to the direction intersecting the source line 66 (in this case, orthogonal), and the adjacent source lines 66 are further inverted. The layout of the pixels 3 to be used is arranged in such a manner that the pixels 3 at positions sandwiching the source line 66 are mirror-inverted for each row. The source portions 7 of the four modulation transistors TM that are close to each other as the mirror image is inverted are connected to each other by a metal wiring 60 using a metal containing aluminum, for example. The connected metal wiring 60 and the source line 66 are connected via the transmission transistor TS. In this layout example, similarly to the layout shown in FIG. 1A, it is possible to dispose the photodiode PD while reducing the area of the opening.
Furthermore, since the contact of the transmission TR gate electrode 70 is shared by the four modulation transistors TM to the transmission transistor TS, the aperture ratio can be improved. In addition, by using this layout, the transmission TR gate line 69 for driving the gate of the transmission transistor TS can be arranged for each row, so that the aperture ratio can be further improved.

FIG. 5 shows another layout example in the case of using the substrate modulation MOS type solid-state imaging device. In this layout, in addition to an arrangement in which the layout of the pixels 3 having a common source line is mirror-inverted for each column, the layout of the pixels 3 at positions sandwiching the source lines is inverted for each row. The source portions 7 of the four modulation transistors TM that are close to each other as the mirror image is inverted are connected to each other by a metal wiring 60 using a metal containing aluminum, for example. The connected metal wiring 60 and the source line 66 are connected via the transmission transistor TS. In this layout example, similarly to the layout shown in FIG. 2A, the reduction in the area of the opening of the photodiode PD can be suppressed.
Furthermore, since the contact of the transmission TR gate electrode 70 (see FIG. 3) of the transmission transistor TS is shared by the four modulation transistors TM, the aperture ratio can be improved. In addition, by using this layout, the transmission TR gate line 69 for driving the gate of the transmission transistor TS can be arranged for each row, so that the aperture ratio can be further improved.

  As described above, the layout that realizes a higher aperture ratio by performing mirror image inversion with FIGS. 1A, 2A, 7, and 5 has been described. However, mirror image inversion is not an essential process. A layout using repetition may be used.

<Drive sequence>
Next, with reference to FIG. 1B and FIG. 3, the light detection and light generation carrier collection operation of the photodiode PD of the pixel 3 and the operation of the modulation transistor TM will be described as a drive sequence. First, the accumulation operation of photogenerated carriers will be described. Subsequently, a signal modulation operation for detecting the amount of light-generated carriers and a clear (discharge of light-generated carriers) operation will be described, and finally a noise modulation operation will be described. The description here will be made in the case of using the VMIS type solid-state image pickup device, but this can be similarly applied to the case of using the substrate modulation MOS type solid-state image pickup device.

First, the accumulation operation of photogenerated carriers will be described. In this case, a low gate potential is applied to the ring gate electrode 6 of the modulation transistor TM via the gate line 67, and a potential of about 2 to 4 V, for example, is applied to the drain portion 8 via the common drain line 68. Thereby, the PD well portion 21 is depleted. An electric field is generated between the drain portion 8 and the source portion 7.
The light incident through the opening region 2 of the photodiode PD is incident on the depleted PD well portion 21 to generate electron-hole pairs (photogenerated carriers). The P-type collection well section 4 has a low potential due to the introduction of high-concentration P-type impurities, and holes among the photogenerated carriers generated in the PD well section 21 are collected in the collection well section 4. Further, the photogenerated carriers are transferred from the collection well portion 4 to the modulation well portion 5 in the modulation transistor TM region and accumulated in the carrier pocket 10. FIG. 6 shows an example of the drive sequence. This operation corresponds to the operation of the accumulation period in the drive sequence shown in FIG.

  Next, a signal modulation operation for detecting the optical carrier amount will be described. The threshold voltage of the modulation transistor TM is changed by the photogenerated carriers accumulated in the carrier pocket 10. In this state, a selection gate potential of about 2 to 4 V, for example, is applied to the ring gate electrode 6 of the selected pixel 3 via the gate line 67, and a potential of about 2 to 4 V, for example, is applied to the drain portion 8. A potential lower than the potential applied to the selected ring gate electrode 6 is supplied to the non-selected pixel 3a via the non-selected gate line 67a. Then, the pixel 3 is selected by lowering the potential of the non-selected source portion 7a that changes in conjunction with the gate potential to be lower than the potential of the source portion 7 of the selected pixel 3, and a signal from the pixel 3 is detected. .

Further, a transfer transistor TS using, for example, a PMOS structure is disposed between the source portion 7 of the selected pixel 3 and the source line 66. The transmission transistor TS is supplied with a control signal via a transmission TR gate line 69 so that the source line 66 and the source unit 7 can be connected / disconnected. When the gate potential of the transmission transistor TS performs signal modulation and noise modulation, the transmission transistor TS is kept at a low potential (PMOS structure is on), and is otherwise kept off.
In this case, for the non-selected non-selected pixel 3a, the gate potential of the non-selected transmission transistor TSa is kept at a high potential (PMOS structure off), and only the potential of the source section 7 of the selected modulation transistor TM is selected. Is transmitted to the source line 66. Therefore, when strong light is incident on the non-selected photodiode PDa and the output signal from the non-selected source part 7a of the non-selected modulation transistor TMa is higher than the source part 7 after clearing the selected modulation transistor TM. However, transmission to the source line 66 can be prevented by the transmission transistor TS.
Therefore, generation of black smear can be prevented. The source part 7 of the selected modulation transistor TM is connected to the source line 66 via the transmission transistor TS. A constant current source (not shown) is disposed in the source line 66 and allows a constant current to flow. A source follower circuit is formed by the constant current source and the modulation transistor TM. The source potential changes following the change in the threshold voltage of the modulation transistor TM due to the photogenerated carrier, and an output potential corresponding to the incident light is obtained. This operation corresponds to the signal modulation of the drive sequence shown in FIG.

Next, a clear (discharge of light-generating carrier) operation will be described. Clearing clears the photogenerated carriers remaining in the carrier pocket 10 and the modulation well portion 5. For example, a high potential of about 5 to 7 V is applied to the ring gate electrode 6 of the modulation transistor TM. The TR well portion 50 is thin, and a high-concentration P-type buried layer 23 is formed below the TR well portion 50.
Therefore, a sudden potential change occurs in the modulation well portion 5, and a strong electric field that sweeps out the photogenerated carriers to the substrate 1 side is mainly applied to the modulation well portion 5, and the remaining photogenerated carriers are more at a low reset potential. Clear to the substrate 1 without fail. As a method of increasing the potential of the ring gate electrode 6, a positive potential is once applied to the ring gate electrode 6 of the modulation transistor TM, and then the ring gate electrode 6 is operated in a floating manner. Then, a positive potential is applied to the drain portion 8 and / or the source portion 7 to perform a bootstrap operation in which the voltage is boosted by capacitive coupling, and clearing can be performed without directly applying a high potential. This operation corresponds to clearing of the drive sequence shown in FIG.

Next, the noise modulation operation will be described. In the noise modulation, after clearing, a signal modulation operation is performed in a state in which light-generating carriers are not yet accumulated. Performs equivalent to the signal modulation operation, such as bias conditions. This operation corresponds to the noise modulation of FIG.
By performing this noise modulation operation, it is possible to obtain a variation in threshold value of each pixel 3 as a noise signal. By subtracting the noise modulation signal obtained here from the signal modulation signal obtained in the above sequence, a net light-generating carrier signal can be extracted. After the noise modulation operation is completed, the accumulation operation is performed again, and an image signal is output by repeating this cycle.

(A) is a partial plan view of a solid-state imaging substrate in which pixels including a VMIS type solid-state imaging device are arranged in an array, and (b) is a cross section of the VMIS type solid-state imaging device obtained by cutting (a) along the line AA ′. Figure. (A) is a partial plan view of a solid-state imaging substrate in which pixels including a substrate-modulation MOS type solid-state imaging device are arranged in an array, and (b) is a substrate-modulation MOS type solid obtained by cutting (a) along the line AA ′. Sectional drawing of an image pick-up element. FIG. 2 is an equivalent circuit diagram of the solid-state imaging substrate shown in FIG. The graph which shows the output electric potential according to light intensity. The layout example in the case of using a substrate modulation MOS type solid-state image sensor. An example of a drive sequence. 6 is a layout example when a VMIS type solid-state imaging device is used. The equivalent circuit diagram which shows the state when strong light injects into the structure which does not use a transmission transistor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Opening area, 3 ... Pixel, 3a ... Non-selection pixel, 4 ... Collection well part, 5 ... Modulation well part, 6 ... Ring gate electrode, 6a ... Non-selection ring gate electrode, 6b ... Gate electrode, 7 ... Source part, 7a ... Unselected source part, 8 ... Drain part, 10 ... Carrier pocket, 11 ... Gate insulating layer, 12 ... Drain contact region, 21 ... PD well part, 23 ... P-type buried layer, 27 ... N-type diffusion layer, 32 ... pinning layer, 50 ... TR well portion, 52 ... element isolation layer, 60 ... metal wiring, 66 ... source line, 66x ... source line, 67 ... gate line, 68 ... common drain line, 69 ... Transmission TR gate line, 70 ... Transmission TR gate electrode, 71 ... Transmission TR source part, 72 ... Transmission TR drain part, 100 ... Solid-state imaging substrate, 115 ... Element isolation region, 120 ... VMIS type Body imaging element, 120b ... substrate modulation MOS type solid-state imaging element, 130 ... solid-state imaging device, PD ... photodiode, PDa ... non-selection photodiode, TM ... modulation transistor, TMa ... non-selection modulation transistor, TS ... transmission transistor, TSa ... non-selective transmission transistor, SL ... strong light.

Claims (6)

A first conductivity type substrate;
A PD well portion of a second conductivity type disposed on the first surface side of the substrate;
A collection well portion having a first conductivity type and located in the PD well portion;
A photodiode including:
A TR well portion having a second conductivity type and connected to the PD well portion and having a junction depth shallower than that of the PD well portion;
A modulation well portion having a first conductivity type, connected to the collection well portion and located in the TR well portion;
A source part disposed in the modulation well part in plan view and having a second conductivity type and a region in contact with the first surface of the substrate;
A gate electrode disposed in a region covering at least a part of the modulation well portion in plan view and surrounding the source portion;
A gate insulating layer disposed at a position sandwiched between the gate electrode and the first surface of the substrate;
A drain part including a region having a second conductivity type and in contact with the first surface of the substrate, disposed in at least a part of a position facing the source part across the gate electrode in plan view;
A modulation transistor comprising:
A set of two modulation transistors arranged in adjacent pixels as a set, the set of electrically connected source units, and one set connected between source lines, and the source unit by a selection signal And a transmission transistor for controlling a conduction state between the source line and the source line,
A solid-state imaging device comprising: A first conductivity type substrate;
A PD well portion of a second conductivity type disposed on the first surface side of the substrate;
A collection well portion having a first conductivity type and located in the PD well portion;
A photodiode including:
A TR well portion having a second conductivity type and connected to the PD well portion and having a junction depth shallower than that of the PD well portion;
A modulation well portion having a first conductivity type, connected to the collection well portion and located in the TR well portion;
A source part disposed in the modulation well part in plan view and having a second conductivity type and a region in contact with the first surface of the substrate;
A gate electrode that is disposed in a region covering at least a part of the modulation well part in a plan view and surrounds a part of the source part;
An element isolation layer surrounding the source part in cooperation with the gate electrode in plan view;
A gate insulating layer disposed at a position sandwiched between the gate electrode and the first surface of the substrate;
A drain part including a region having a second conductivity type and being in contact with the first surface of the substrate, at least partially disposed at a position facing the source part across the gate electrode in plan view;
A modulation transistor comprising:
A set of two modulation transistors arranged in adjacent pixels as a set, the set of electrically connected source units, and one set connected between source lines, and the source unit by a selection signal And a transmission transistor for controlling a conduction state between the source line and the source line,
A solid-state imaging device comprising: The layout of the modulation transistor and the photodiode of the pixel is arranged by inverting the mirror image in a direction intersecting the source line for each column, and the transmission transistor is arranged in a region where the modulation transistor is arranged in proximity. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is characterized.
Is mirror-reversing the direction intersecting with the source line layout of the modulation transistor and the photodiode of the pixel for each one row, further, the layout of the modulation transistor and the photodiode in a position sandwiching the source lines, one line 3. The solid-state imaging device according to claim 1, wherein a mirror image is inverted in a direction aligned with the source line every time, and a transmission transistor is arranged in a region where the modulation transistor is arranged close to the source line.
  In the region where the photodiode is located, between the substrate surface including the substrate surface and the collection well portion, and / or including the interface between the gate insulating layer and the substrate, and the modulation 5. The solid-state imaging device according to claim 1, further comprising a pinning layer having a second conductivity type between the well and the well.   In the modulation well portion, a region overlapping with at least a part of the gate electrode in plan view further includes a carrier pocket portion having an impurity concentration of the first conductivity type higher than that of the surrounding modulation well portion. The solid-state imaging device according to any one of claims 1 to 5.

Images