JPH0520892A - Ccd element - Google Patents

Abstract

PURPOSE:To enhance sensitivity by suppressing influence of a parasitic capacity existing between a floating diffusion region of an output unit and a reset gate in a CCD element. CONSTITUTION:In a CCD element in which a floating diffusion region 7 is connected to a final stage of a charge transfer register 1 having a CCD structure through a horizontal output gate 5 and a reset gate 11 is provided between the region 7 and a reset drain region 10, an output gate pulse phi having a reverse phase to that of a reset pulse phiRG to be applied to the gate 11, is applied to the gate 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a CCD area sensor,
The present invention relates to a CCD image sensor such as a CCD linear sensor and a CCD device such as another device using a CCD.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration of a final stage portion of a horizontal transfer register of a conventional CCD image pickup device and its output portion. In the figure, 1 indicates a horizontal transfer register. In the horizontal transfer register 1, a plurality of transfer electrodes 4 each having a transfer electrode, that is, a storage electrode 3S and a transfer electrode 3T are arranged on the main surface of the semiconductor substrate 2 via an insulating film, and a two-phase drive pulse φH is provided. ₁ and φH ₂ (see FIGS. 5A and 5B) are formed so as to transfer the signal charge in the horizontal direction. The transfer unit 4 at the final stage of the horizontal transfer register 1 has a fixed gate voltage V
It is connected to the floating diffusion region 7 through the horizontal output gate unit 5 to which the _HOG is applied, and the signal charges from the horizontal transfer register 1 are transferred to the floating diffusion region 7, and the charge-voltage conversion is performed on the output amplifier 8. Will be output through. In the output section 9, in order to sweep out the signal charges transferred to the floating diffusion region 7 to the reset drain region 10 to which the predetermined voltage V _RD is applied, a reset pulse φRG (FIG. 5C) is provided between the regions 7 and 10. The reset gate portion 11 to which the reference voltage is applied is formed.

[0003]

In the output section 9 of FIG.
As shown in FIG. 5D, the floating diffusion area 7
As shown in the potential waveform of
When (when the reset pulse φRG is at a high level),
Floating diffusion region 7 potential V _FDIs
Set drain region 10 potential V_RDIs equal to (immediately
Chi V_FD= V_RD), Floating diffusion area
7 and the reset gate 11 between the parasitic capacitance C₁exist
In order to do so, after the reset gate unit 11 is turned off,
Potential of the contact diffusion region 7_FDIs parasitic
Quantity C₁Of the reset drain region 10 by capacitive coupling of
Potential V_RDNot lower than that (ie V_FD<
V_RD). Looking at this with the CCD output waveform of FIG. 5E, the reset
After the gate 11 is turned off, the reference potential (that is, reset
Potential lower than (a) (that is, feedthrough potential) b
become. The difference between this reference potential a and the feedthrough potential b
Parasitic capacitance C₁So-called coupling amount A due to₁Tona
It

As the sensitivity of the CCD image pickup device increases, the capacitance C ₁ may be reduced in proportion to the capacitance related to the floating diffusion region 7. However, if it does not decrease, the coupling amount A ₁ becomes relatively large, and the signal A ₁ The dynamic range of the components is reduced. That is, as shown in the potential diagram of FIG. 6, the potential of the floating diffusion region 7 after turning off the reset gate portion 11 becomes shallower than V _RD (broken line position) (solid line position), and FD
It makes transfer to other parts difficult and reduces the amount of charge handled. The potential difference B _{1 in} FIG. 6 corresponds to the coupling amount A ₁ in the CCD output waveform.

In view of the above points, the present invention has a capacitance C between the reset gate portion and the floating diffusion region.
_The purpose is to reduce the coupling amount A _{1 due} to ₁ .

[0006]

According to the present invention, a floating diffusion region 7 is connected to a final stage of a charge transfer register 1 having a CCD structure via an output gate unit 5, and the floating diffusion region 7 and a reset drain are connected to each other. C in which the reset gate portion 11 is provided between the regions 10
In the CD element, an output gate pulse φHOG having a phase opposite to that of the reset pulse φRG applied to the reset gate unit 11 is applied to the output gate unit 5.

[0007]

In the present invention, the output gate section 5 is supplied with the output gate pulse φHOG having a phase opposite to that of the reset pulse φRG. Therefore, after turning off the reset gate unit 11,
The potential V _FD of the floating diffusion region 7 is
Although the potential V _RD of the reset drain region 10 can be lowered by the capacitive coupling of the parasitic capacitance C ₁ between the reset gate region 11 and the floating diffusion region 7, conversely, the floating diffusion region 7 and the output gate region 5 are reversed.
Since the parasitic capacitance C ₂ also exists between and, the parasitic capacitance C _2
It is pulled up by capacitive coupling of ₂ . As a result, the coupling amount due to the parasitic capacitance C ₁ is suppressed and the coupling amount A is reduced.

[0008]

Embodiments of the CCD device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of the final stage portion of the horizontal transfer register of the CCD device according to the present embodiment and its output portion, and the portions corresponding to those in FIG. Also in this example, as in the case of FIG. 4, a plurality of transfer portions 4 having storage electrodes 3S and transfer electrodes 3T are arranged on the main surface of the semiconductor substrate 2 with an insulating film interposed therebetween, and a two-phase drive pulse φH is generated.
C which sequentially transfers the signal charges in the horizontal direction at ₁ and φH ₂
CD structure horizontal transfer register 1 and horizontal transfer register 1
The horizontal output gate unit 5 and the floating diffusion region 7 connected to the transfer unit 4 at the final stage, the output amplifier 8 connected to the floating diffusion region 7, the reset drain region 10, and the floating drain region 7.
Reset gate unit 11 for sweeping out signal charges transferred to diffusion region 7 to reset drain region 10
And have. A predetermined voltage V _RD is applied to the reset drain region 10, and a reset pulse φ is applied to the reset gate unit 11.
RG is applied respectively.

In this example, however, FIGS.
As shown in, the horizontal output gate section 5 is applied with an output gate pulse φHOG having a phase opposite to that of the reset pulse φRG instead of the conventional fixed potential.

A parasitic capacitance C ₁ exists between the floating diffusion region 7 and the reset gate portion 11, and at the same time, a parasitic capacitance C ₂ exists between the floating diffusion region 7 and the horizontal output gate portion 5. Therefore, by applying an output gate pulse φHOG having a phase opposite to that of the reset pulse φRG to the horizontal output gate unit 5, the potential drop in the floating diffusion region 7 after turning off the reset gate unit 11 is suppressed. The coupling amount A in the so-called CCD output waveform can be
₂ can be suppressed.

That is, when a high level (eg, 5 V) of the reset pulse φRG is applied to the reset gate section 11 and the reset gate section 11 is turned on, the potential V _FD of the floating diffusion region 7 is the potential of the reset drain region 10. It becomes equal to V _RD . At this time, a low level (for example, 0V) of the output gate pulse φHOG is applied to the horizontal output gate unit 5. Next, the potential V _FD of the floating diffusion region 7 after the low level (for example, 0 V) of the reset pulse φRG is applied and the reset gate unit 11 is turned off is lowered by the capacitive coupling of the parasitic capacitance C _1. At the same time, the horizontal output gate unit 5
Then, the high level of the output gate pulse φHOG (for example, 5
V) is applied, the potential of the floating diffusion region 7 is raised by the capacitive coupling of the parasitic capacitance C ₂ . As a result, the potential drop in the floating diffusion region after turning off the reset gate unit 11 is suppressed, and the coupling amount A _{2 in} the CCD output waveform of FIG. 2E is reduced.

Here, the parasitic capacitance C₁And parasitic capacitance C₂Is all
The same value (C₁= C₂), Reset pulse φRG
If the force gate pulse φHOG is in the opposite phase,
Coupling amount becomes O and CCD output waveform P shown by the chain line
₁Becomes Also, the parasitic capacitance C ₁And parasitic capacitance C₂Are equal
What can reduce the amount of coupling without
And, for example, C₁> C₂If present, the coupling of Figure 2E
Quantity A₂CCD output waveform P shown by the solid line₂Becomes Illustrated
Colander C₁<C₂In some cases, P₃Is for comparison
The conventional CCD output waveform shown in Fig. 4
is there. In the above example, the output gate pulse φHOG and reset
Although the output pulses φRG have the same amplitude,
Coupling amount A by changing the amplitude of loose φHOG₂
Can be suppressed.

Next, charge transfer in the above embodiment will be described with reference to the applied pulse waveforms of FIGS. 2A to 2D and the potential diagram of FIG. Two-phase drive pulses φH ₁ and φH are sent to the transfer unit 4 of the horizontal transfer register 1 at the timing shown in FIG.
₂ output gate pulse φHOG to the horizontal output gate unit 5
However, the reset pulse φRG is applied to the reset gate unit 11, respectively.

At time t ₁ when the reset gate portion 11 is turned on, the potential of each portion becomes the state shown in FIG. 3A, the signal charge e ₁ of the floating diffusion region 7 is swept out to the reset drain region 10, and Of the signal charge e ₂ of the storage electrode 3S of the transfer unit 4 at the final stage.
Transferred to below.

Next, the drive pulse .phi.H ₁ At time t ₂ the reset gate portion 11 is turned off is high, the output gate pulse φHOG goes high, become potential state shown in FIG. 3B, the signal charges e ₂ is Transfer unit 4 at the final stage
Remains below the storage electrode 3S.

Next, at time t ₃ , the driving pulse φH ₁ becomes low level, and the potential state shown in FIG.
The signal charge e ₂ of the transfer section 4 is transferred to the floating diffusion region 7, and the signal component is output through the output amplifier 8.

Next, at the time point t ₄ , the driving pulse φH ₁ becomes high level, and the potential state of FIG. 3D is brought about, and the next signal charge e ₃ is transferred to below the storage electrode 3S of the transfer section 4 at the final stage. It In this way, the charges are sequentially transferred to the floating diffusion region 7 and output.

According to the above-described embodiment, the reset pulse φR is applied to the horizontal output gate section 5 at the next stage of the horizontal transfer register 1.
By applying the output gate pulse φHOG having a phase opposite to that of G, the influence of the parasitic capacitance C ₁ between the reset gate portion 11 and the floating diffusion region 7 can be reduced and the coupling can be reduced. This allows the CCD
It is possible to overcome the reduction in the amount of charge handled in the floating diffusion region 7 and the reduction in the electric field transferred to the floating diffusion region 7 due to the increased coupling amount due to the increased sensitivity of CCD image pickup devices such as area sensors and CCD linear sensors. it can.

[0020]

According to the present invention, the influence of the parasitic capacitance between the floating diffusion region and the reset gate portion can be suppressed, and the amount of coupling between the reference potential and the feedthrough potential in the output waveform can be reduced. -The amount of charges handled in the diffusion region can be secured. Therefore, CCD area sensor, CC
It is possible to promote higher sensitivity of a CCD image sensor such as a D linear sensor.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part of a CCD device of the present invention.

FIG. 2 is a waveform diagram showing an applied pulse waveform and a CCD output waveform according to the present invention.

FIG. 3 is a potential diagram during charge transfer according to the present invention.

FIG. 4 is a configuration diagram of a main part of a conventional CCD device.

FIG. 5 is a waveform diagram showing a conventional applied pulse waveform and a CCD output waveform.

FIG. 6 is a potential diagram of a conventional output unit.

[Explanation of symbols]

 1 Horizontal Transfer Register 2 Semiconductor Substrate 3S, 3T Transfer Electrode 4 Transfer Section 5 Horizontal Output Gate Section 7 Floating Diffusion Area 8 Output Amplifier 9 Output Section 10 Reset Drain Area 11 Reset Gate Section

Claims (1)

Claim: What is claimed is: 1. A floating diffusion region is connected to the final stage of a charge transfer register having a CCD structure via an output gate portion, and a reset gate is provided between the floating diffusion region and the reset drain region. A CCD device having a section, wherein an output gate pulse having a phase opposite to that of a reset pulse applied to the reset gate unit is applied to the output gate unit.