JP3137808B2 - Charge detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge detecting device for a solid-state imaging device.

[0002]

2. Description of the Related Art A charge detection device of an interline type two-dimensional CCD solid-state imaging device will be described as an example. FIG. 7 is an example of a schematic diagram of a conventional charge detection device, in which an N-type transfer path 1,
Horizontal transfer gates 2a, 2b, output gate 3, floating diffusion layer 4, reset gate 5, reset drain 6,
It is composed of an aluminum wiring 8 connected to the floating diffusion layer 4. Reference numeral 7 denotes a contact portion between the floating diffusion layer 4 and the aluminum wiring 8. In this example, the horizontal transfer gates 2a and 2b function as a source portion, and the floating diffusion layer 4 functions as a charge storage portion. Although a voltage amplifier circuit exists after the aluminum wiring 8, it is not shown.

The operation of the above-described charge detection device will be described below with reference to the signal charge as electrons. In the interline type CCD image pickup device, signal charges generated in the image pickup section are transferred to the horizontal transfer section by vertical scanning, and then transferred to the charge detection section by horizontal scanning. The charge transferred to the charge detection unit is accumulated in the floating diffusion layer 4 through the output gate 3. The floating diffusion layer 4 has a capacitance and has a function of accumulating charges. This capacitance is called a sense capacitance.

A voltage change occurs in the floating diffusion layer 4 in accordance with the amount of accumulated charges. The magnitude of the voltage is determined by the sense capacitance of the floating diffusion layer 4 according to the law of (voltage) = (charge) / (capacity). The voltage change generated in the floating diffusion layer 4 is transmitted through the aluminum wiring 8 and output through the voltage amplifier circuit.

FIG. 8A is a schematic sectional view taken along the line XX 'of FIG. FIGS. 8B to 8E are operation explanatory diagrams showing the potential states when voltages are applied to the respective gates over time. A pulse voltage is applied to the reset gate 5 and the horizontal transfer gates 2a and 2b, a DC voltage V _RD of, for example, 15 V is applied to the reset drain 6, and a DC voltage V _OG of, for example, about 6 V is applied to the output gate 3. In FIG. 8A, reference numeral 10 denotes a diffusion layer for adjusting potential.

[0006] Figure 9 shows a reset pulse φR applied to the reset gate 5, and the horizontal transfer pulses H ₂ applied to the horizontal transfer gate 2b, and the signal voltage output in response thereto. Times T = t ₀ , t in FIGS.
₁ , t ₂ and t ₃ correspond to the respective times in FIG.

Hereinafter, the operation of the charge detection unit will be described with reference to FIGS. At time t ₀ the reset pulse .phi.R, a horizontal transfer pulse H ₂ both HIGH (H) level, the charge is present under the horizontal transfer gate 2b. The floating diffusion layer 4 becomes equal to the DC voltage V _RD , and the signal output is also at the H level. Time t ₁ the reset pulse φR is LOW
(L) level, and the reset gate 5 closes. A coupling capacitance _CG exists between the floating diffusion layer 4 and the reset gate 5. Therefore this time the floating diffusion layer 4 is affected by the coupling capacitance C _G, the signal output MIDDLE
(M) level.

At time t ₂ , signal charges flow from the horizontal transfer gate ₂ b into the floating diffusion layer 4. The signal charge flowing into the floating diffusion layer 4 is converted into a voltage according to the sense capacitance of the floating diffusion layer 4. The aluminum wiring 8 connected to the floating diffusion layer 4 has a voltage converted by the floating diffusion layer 4. The signal output also changes to L level.

At time t ₃ , the reset pulse φR and the horizontal transfer pulse H ₂ go high again. At this time, the reset gate 5 is opened, and the charges in the floating diffusion layer 4 are discharged to the reset drain 6. This operation is called reset.
The next signal charge flows below the horizontal transfer gate 2b.
By the reset operation, the voltage of the floating diffusion layer 4 becomes equal to the DC voltage V _RD again, and the signal output becomes H level.

Here, the difference between the H level and the M level of the signal output is referred to as a φR peak value. This is the dive noise caused by the reset pulse, and its generation principle is as follows. FIG. 10 shows an equivalent circuit diagram of the charge detection device. C is the sense capacitance of the floating diffusion layer 4, and C _G is the coupling capacitance existing between the floating diffusion layer 4 and the reset gate 5. When a pulse signal is applied to the reset gate 5 to perform a reset operation, the coupling capacitance C
Because of the presence of _G , a pulse signal is added to the output, and is output as a noise component. This is the φR peak value.

[0011]

However, the above configuration has a problem that a peak value of a required magnitude cannot be obtained when a noise component due to a reset pulse is positively used for a synchronization signal or the like. Had a point. As a device that positively utilizes the φR peak value, for example, there is a television camera device as disclosed in JP-A-1-132280.

[0012] While determining the φR peak value is determined by the coupling capacitance C _G of the reset gate 5 and the floating diffusion layer 4, it is difficult to adjust the capacitance in the configuration shown in FIG. 7 . Coupling capacitance C _G of the reset gate 5 and the floating diffusion layer 4, when the capacitance of the floating diffusion layer 4 is constant, because determined by the capacitance of the gate insulating film of the reset gate 5, the area of the reset gate 5 Does not increase the coupling capacitance C _G with the floating diffusion layer 4.
Changing the capacitance of the gate insulating film leads to changes in other characteristics of the transfer gate, and the range of change is limited.

Further, with the recent miniaturization of the image pickup device and the increase in the number of pixels, the size of the pixel has been reduced and the amount of individual signal charges has been reduced. Efforts have been made to increase it. As one of the methods, the sense capacitance C of the floating diffusion layer 4 is reduced. According decreasing the capacitance of the floating diffusion layer 4, the coupling capacitance C _G of the reset gate 5 and the floating diffusion layer 4 so decreases, also decreases φR peak value.

[0014] As described above, as in the conventional structure can not be arbitrarily adjusted coupling capacitance C _G between the reset gate 5 and the floating diffusion layer 4, it is impossible to obtain a desired φR peak value Had problems. SUMMARY OF THE INVENTION It is an object of the present invention to provide a charge detection device capable of arbitrarily adjusting the peak value of φR irrespective of the magnitude of the sense capacitance of a floating diffusion layer and being able to positively use the noise of a reset pulse. .

[0015]

A charge detection device according to the present invention includes a source portion, a drain portion, and a charge storage portion formed between the source and drain portions and having both sides separated by gate electrodes. The gate electrode between the charge storage portion and the drain portion has a portion overlapping with a metal wiring connected to the charge storage portion via an insulating film.

[0016]

According to the present invention, since the wiring connected to the charge storage portion and the reset gate have a portion that overlaps, a new coupling capacitance between the reset gate and the wiring can be obtained. An arbitrary coupling capacity can be obtained by adjusting the area of the wrap. An arbitrary φR peak value can be obtained by the arbitrarily obtained coupling capacitance.

[0017]

1 (a) and 1 (b) are plan views of a charge detecting device according to a first embodiment of the present invention and its YY 'line.
1 is a sectional view of FIG. In FIG. 1, reference numeral 3 denotes an output gate, 4 denotes a floating diffusion layer serving as a charge storage portion, 5 denotes a reset gate, and 6 denotes a reset drain. Reference numeral 8 denotes an aluminum wiring connected to the floating diffusion layer 4. 2a,
2b is a horizontal transfer gate, which corresponds to a source section. The horizontal transfer gate applies the same voltage to the two gates,
It is driven by phase transfer pulses. The reset gate 5 and the wiring 8 partially overlap each other to form a coupling capacitance. 11 is an insulating film, and 12 is a P well.

The reset gate 5 and the aluminum wiring 8 are shown in FIG.
As shown in (a) and (b), they overlap via the insulating film 11. FIG. 2 is an equivalent circuit diagram of the charge detection device in this embodiment. The correspondence between FIG. 2 and FIG. 1 is as follows. Capacitance C sense capacitance of the floating diffusion layer 4, capacitance C _G is the coupling capacitance between the floating diffusion layer 4 and the reset gate 5, capacitance C 'is overlap reset gate 5 and the aluminum wiring 8 as in Figure 1 This shows the coupling capacitance generated as a result. Further, a reset pulse φR having an amplitude V is applied to the reset gate 5, and a DC voltage V _RD is applied to the reset drain 6.

The operation of the charge detection device of this embodiment configured as described above will be described below. The signal charge is transferred from the horizontal transfer gate 2b and converted into a voltage in the floating diffusion layer 4. This voltage is processed by an amplifying circuit later through the aluminum wiring 8 to output a signal. This operation is similar to that of the conventional charge detection device. The signal output waveform is as shown in FIG. The φR peak value should be obtained according to the total coupling capacitance between the floating diffusion layer 4 and the reset gate 5.

In this embodiment, the reset gate 5 and the coupling capacitance C 'of the aluminum wiring 8 from the floating diffusion layer 4 are connected in parallel as shown in the equivalent circuit diagram of FIG. Therefore, the total coupling capacitance between the reset gate 5 and the floating diffusion layer 4 is the sum of C _G and C ′. Accordingly, when the reset pulse amplitude is V, the increase ΔV _out of the φR peak value in the output signal is expressed by the following equation.

ΔV _out = (C ′ / C) · V (1) FIG. 3 shows φR peak value data when the magnitude of the coupling capacitance C ′ is actually changed. Looking at this, ΔV
_out changes in proportion to the coupling capacitance C ′,
It can be seen that this matches the equation (1).

As described above, in the charge detecting device according to this embodiment, the φR peak value can be arbitrarily increased by adjusting the coupling capacitance C ′ between the reset gate 5 and the aluminum wiring 8. FIG. 4 is a plan view showing a charge detection device according to a second embodiment of the present invention. In FIG. 4, 3 is an output gate, 4 is a floating diffusion layer, 5 is a reset gate, and 6 is a reset drain. Reference numeral 8 denotes an aluminum wiring connected to the floating diffusion layer 4. 2a and 2b are horizontal transfer gates. The horizontal transfer gates 2a and 2b apply the same voltage to the two gates,
It is driven by phase transfer pulses. The reset gate 5 and the aluminum wiring 8 partially overlap each other to form a coupling capacitance.

FIG. 5 is a sectional view taken along line XX 'of FIG. The reset gate 5 and the aluminum wiring 8 overlap as shown in the figure. FIG. 6 is an equivalent circuit diagram of the charge detection device in this embodiment. Also in the second embodiment, as in the first embodiment, the coupling capacitance C ₂ ′ caused by the overlap between the reset gate 5 and the aluminum wiring 8.
Are connected in parallel. The capacitance C ₂ is the sense capacitance of the floating diffusion layer 4. C _2G is a coupling capacitance between the floating diffusion layer 4 and the reset gate 5. A pulse signal having an amplitude V is applied to the reset gate 5, and D signal is applied to the reset drain 6.
C voltage V _RD is applied.

The operation of the charge detection device of this embodiment having the above-described configuration will be described below. The signal charge is transferred from the horizontal transfer gate 2b and converted into a voltage by the floating diffusion layer 4. This voltage is processed by an amplifying circuit later through the aluminum wiring 8 to output a signal. This operation is performed in the same manner as in the conventional charge detection device and the charge detection device according to the first embodiment. The signal output waveform is as shown in FIG.

Also in this embodiment, the reset gate 5
Additional coupling capacitance C ₂ ′ is connected in parallel between the capacitor and the aluminum wiring 8, so that the increase ΔV of the peak value of φR ΔV
_2out is expressed by the following equation. ΔV _2out = (C ₂ ′ / C ₂ ) · V (2) As described above, also in the charge detection device according to this embodiment, by adjusting the coupling capacitance C ₂ ′ between the reset gate 5 and the aluminum wiring 8. , The peak value of φR can be arbitrarily increased.

In the first and second embodiments, the floating diffusion layer 4 is used as the charge storage portion. However, it is needless to say that the floating diffusion layer 4 may have a structure such as a floating gate for storing charges. In the first and second embodiments, the wiring is made of aluminum. However, for example, a metal material such as tungsten or molybdenum, or polysilicon, a material having a laminated structure of the above materials, and other conductive materials are used. It goes without saying that the material may be used.

[0027]

According to the present invention, since the wiring connected to the charge storage portion and the reset gate have a portion that overlaps, a new coupling capacitance between the reset gate and the wiring can be obtained. An arbitrary coupling capacity can be obtained by adjusting the area of the overlap. With the arbitrarily obtained coupling capacitance, it is possible to arbitrarily adjust the magnitude of the φR peak value (reset pulse dive noise) during signal output.

Further, with the recent increase in the output of the charge detection device accompanying the miniaturization of the imaging device, the φR peak value can be arbitrarily adjusted regardless of the detection sensitivity while the φR peak value is becoming smaller. Therefore, when the φR peak value is used for a synchronization signal or the like, its practical effect is great.

[Brief description of the drawings]

FIG. 1A is a plan view of a charge detection device according to a first embodiment of the present invention, and FIG. 1B is a sectional view taken along the line YY 'of FIG.

FIG. 2 is an equivalent circuit diagram of the charge detection device shown in FIG.

FIG. 3 is a diagram showing φR peak value data of the charge detection device shown in FIG. 1;

FIG. 4 is a plan view of a charge detection device according to a second embodiment of the present invention.

FIG. 5 is a sectional view taken along line XX ′ of FIG. 4;

FIG. 6 is an equivalent circuit diagram of a charge detection device according to a second embodiment of the present invention.

FIG. 7 is a plan view of a conventional charge detection device.

8A is a schematic cross-sectional view taken along line XX ′ of FIG. 7, and FIGS.
(E) is the potential diagram.

FIG. 9 is a diagram showing a reset pulse, a horizontal transfer pulse, and a signal output.

FIG. 10 is an equivalent circuit diagram of an example of a conventional charge detection device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 N-type transfer path 2a, 2b Horizontal transfer gate 3 Output gate 4 Floating diffusion layer 5 Reset gate 6 Reset drain 7 Contact 8 Aluminum wiring 10 Potential adjustment injection layer 11 Insulating film 12 P well

Claims (1)

(57) [Claims] A charge storage portion formed between the source and drain portions and having both sides separated by a gate electrode, wherein the charge storage portion and the drain portion have a plurality of charge storage portions. A charge detection device, characterized in that the charge detection device has a portion in which an intervening gate electrode and a metal wiring connected to the charge storage portion overlap via an insulating film.