JPH0682693B2 - Charge transfer device - Google Patents
Charge transfer deviceInfo
- Publication number
- JPH0682693B2 JPH0682693B2 JP59171877A JP17187784A JPH0682693B2 JP H0682693 B2 JPH0682693 B2 JP H0682693B2 JP 59171877 A JP59171877 A JP 59171877A JP 17187784 A JP17187784 A JP 17187784A JP H0682693 B2 JPH0682693 B2 JP H0682693B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- conductivity type
- region
- transfer
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76808—Input structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76833—Buried channel CCD
- H01L29/76841—Two-Phase CCD
Description
【発明の詳細な説明】 産業上の利用分野 本発明は電荷転送装置に関するものであり、特に複数個
のチップを配列した長尺の密着型CCDイメージセンサに
係わるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device, and more particularly to a long contact CCD image sensor in which a plurality of chips are arranged.
従来例の構成とその問題点 近年、一次元固体撮像素子を複数個配列して被写体の原
稿と同じサイズにした所謂密着型イメージセンサの開発
が活発に進められており、一部実用化のレベルに達して
きている。Configuration of Conventional Example and Its Problems In recent years, a so-called contact-type image sensor in which a plurality of one-dimensional solid-state image pickup elements are arranged to have the same size as a document of a subject has been actively developed, and a level of practical application is partially achieved. Has reached.
第1図は従来の密着型CCD一次元固体撮像装置の転送要
部の断面図を示したものであり、第2図、第3図は、そ
の各断面におけるポテンシャル図および2相駆動の印加
パルスのタイミングt1,t2を示す。第1図において、1
はP型基板、2はNウエル領域、3はバリヤ領域でNウ
エル領域2と同じ導電型であり、その濃度はNウエル領
域2よりも低い領域である。4は蓄積ゲート、5はバリ
ヤゲートであり、6はゲート酸化膜である。P1,P2は駆
動用の各パルス信号φ1,φ2を印加する電極である。な
お第2図で転送電荷7は、電極P1,P2に、それぞれ、パ
ルス信号φ1,φ2を印加して左側から右側へ転送された
ことを表わしている。密着型センサは、集光レンズを介
さず、被写体と撮像素子とが1対1対応なので、画素の
ピッチが集光センサに比して大きくなり、それに従って
転送部のディメンジョンも大きくなる。例えば16画素/m
mの場合、第1図の蓄積ゲート4のゲート長は19μm
で、バリヤゲート5のゲート長は12.25μmであり、し
たがって、2相駆動で各パルス信号φ1,φ2を与えるCC
Dの1ビットとしては、両ゲート長の2倍であり、した
がって、素子内では62.5μmが1ピッチである。これ
は、従来の集光型のセンサで、例えば蓄積ゲートが9μ
mでバリヤゲートが5μmのCCDであって、その1ビッ
トとしての長さが28μmのものとくらべて、ピッチ、ゲ
ート長ともに2倍以上大である。FIG. 1 is a sectional view of a transfer main part of a conventional contact type CCD one-dimensional solid-state imaging device, and FIGS. 2 and 3 are potential diagrams and applied pulses for two-phase driving in each section. The timings t 1 and t 2 are shown. In FIG. 1, 1
Is a P-type substrate, 2 is an N well region, 3 is a barrier region having the same conductivity type as that of the N well region 2, and its concentration is lower than that of the N well region 2. Reference numeral 4 is a storage gate, 5 is a barrier gate, and 6 is a gate oxide film. P 1 and P 2 are electrodes to which the driving pulse signals φ 1 and φ 2 are applied. In FIG. 2, the transfer charge 7 is transferred from the left side to the right side by applying the pulse signals φ 1 and φ 2 to the electrodes P 1 and P 2 , respectively. Since the contact type sensor has a one-to-one correspondence between the subject and the image pickup element without a condensing lens, the pixel pitch becomes larger than that of the condensing sensor, and the dimension of the transfer unit also increases accordingly. 16 pixels / m
In the case of m, the gate length of the storage gate 4 in FIG. 1 is 19 μm
Therefore, the gate length of the barrier gate 5 is 12.25 μm, and therefore CC that gives each pulse signal φ 1 and φ 2 in the two-phase drive
One bit of D is twice the gate length of both gates, so 62.5 μm is one pitch in the device. This is a conventional concentrating sensor, for example, the storage gate is 9μ.
Both the pitch and the gate length are more than twice as large as those of a CCD having a barrier gate of 5 μm and a length of 1 μm of 28 μm.
以上のように密着型のCCDセンサは集光型のセンサと比
較して2倍以上のゲート長が必要となり、転送速度がゲ
ート長の2乗に反比例することを考慮すると、高速動作
特性が著しく劣ることになる。As described above, the contact type CCD sensor requires a gate length that is at least twice as long as that of the condensing type sensor, and considering that the transfer speed is inversely proportional to the square of the gate length, the high-speed operation characteristics are remarkable. Will be inferior.
発明の目的 本発明は従来例の上記欠点に鑑み、より高速可能な電荷
転送装置を提供するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and provides a charge transfer device capable of higher speed.
発明の構成 この目的を達成するために、本発明の電荷転送装置は、
所定の電荷を、ビット単位で、転送用信号によって順次
転送する電荷転送部として、一導電型基板上に形成され
た少なくとも3つの反対導電型領域を、相隣り合う各領
域毎互いに濃度を異ならせて、周期的に有し、前記反対
導電型領域のうちの少なくとも1つの領域は、直上に電
極を持たず、前記転送用信号に依存しない固定電位を保
ち、残余の前記反対導電型領域は、直上の絶縁ゲート電
極に与えられる前記転送用信号で、変動電位を生じるよ
うに構成し、これにより、高速動作を可能にしたもので
ある。To achieve this object, the charge transfer device of the present invention comprises:
At least three opposite conductivity type regions formed on one conductivity type substrate are made to have different concentrations in each adjacent region as a charge transfer unit that sequentially transfers a predetermined charge in a bit unit by a transfer signal. And has at least one region of the opposite conductivity type region that does not have an electrode immediately above and maintains a fixed potential that does not depend on the transfer signal, and the remaining opposite conductivity type region has The transfer signal applied to the insulating gate electrode immediately above is configured to generate a fluctuating potential, thereby enabling high speed operation.
実施例の説明 以下、本発明の実施例について図面を参照しながら説明
する。第4図は本発明の一実施例における密着型CCD撮
像装置の転送部要部の断面図を示したものである。図中
の符号で、11はP型基板、12,13,14はNウエル領域であ
り、濃度はNウエル領域14が一番高く、Nウエル領域13
が一番低い。Description of Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 4 is a sectional view of a main part of a transfer unit of the contact type CCD image pickup device according to the embodiment of the present invention. In the figure, reference numeral 11 is a P-type substrate, and 12, 13, 14 are N well regions, and the N well region 14 has the highest concentration and the N well region 13 has the highest concentration.
Is the lowest.
また、20は蓄積ゲートで、21はバリヤゲートであり、こ
れら2つのゲートは共通接続されている。P1及びP2は各
々周期パルス信号φ1及びφ2を印加する電極である。第
5図のポテンシャル図は第6図のタイミングt1〜t2の各
々について示す。第4図〜第6図において電極P1及び電
極P2がともにローレベルの時、即ちタイミングt1のとき
は、Nウエル領域12,13及び14の各領域はNウエルの濃
度差によりポテンシャルに差がつく。タイミングt2の時
にはパルスφ1がハイレベルとなり、転送電荷19はポテ
ンシャルの最も低い蓄積ゲート20の下の領域12内に蓄積
され、このとき、バリヤゲート21は電荷の逆流を防ぐバ
リヤとしての働きをする。次にタイミングt3の場合、パ
ルスφ1はローレベル、パルスφ2はハイレベルとなるの
で、転送電荷19は電極P1の下の蓄積ゲート部から電極P2
の蓄積ゲート20の下へ一挙に転送される。第5図を見る
とNウエル領域14の上にはゲートがないので、ポテンシ
ャルはNウエル領域14の不純物の濃度のみに依存し、ち
ょうどNウエル領域14のポテンシャルを中心にして電極
P1,P2に印加される電荷転送用の周期パルス信号φ1,φ
2のローレベル、ハイレベルに応じて、ゲート12及び13
の下の各領域のポテンシャルが上下して、電荷を転送し
ていく様子が分る。第4図の実施例では蓄積ゲートを13
μm、バリヤゲートを10μm、そして、ゲートのないN
ウエル領域14の長さを8.25μmに設定して、素子内の1
ピッチを第1図の例と同じにしたものである。従って本
実施例では蓄積ゲート長(第1図の例では19μmが最
大)が最大で13μmとなり、第1図の例と比較して、ピ
ッチが同一でもゲート長が小さくなる。通常、転送速度
はゲート長の2乗に反比例するので、本実施例の電荷転
送装置は第1図の従来のものと比べて2倍以上転送速度
が大きくなる利点を有する。Further, 20 is a storage gate and 21 is a barrier gate, and these two gates are commonly connected. P 1 and P 2 are electrodes for applying the periodic pulse signals φ 1 and φ 2 , respectively. The potential diagram of FIG. 5 is shown for each of the timings t 1 to t 2 of FIG. In FIGS. 4 to 6, when the electrodes P 1 and P 2 are both at a low level, that is, at the timing t 1 , each of the N well regions 12, 13 and 14 becomes a potential due to the concentration difference of the N well. There is a difference. At the timing t 2 , the pulse φ 1 becomes high level, the transfer charge 19 is accumulated in the region 12 under the accumulation gate 20 having the lowest potential, and at this time, the barrier gate 21 functions as a barrier for preventing backflow of charges. To do. Next, at the timing t 3 , the pulse φ 1 becomes low level and the pulse φ 2 becomes high level, so that the transfer charge 19 is transferred from the accumulation gate portion under the electrode P 1 to the electrode P 2
Are transferred to the bottom of the storage gate 20 at once. As shown in FIG. 5, since there is no gate above the N well region 14, the potential depends only on the impurity concentration of the N well region 14, and the potential is centered on the potential of the N well region 14 and the electrode
Periodic pulse signals φ 1 and φ for charge transfer applied to P 1 and P 2
Gates 12 and 13 depending on the low and high levels of 2
It can be seen that the potential of each region under and up and down transfers charges. In the embodiment shown in FIG.
μm, barrier gate 10 μm, and N without gate
Set the length of the well region 14 to 8.25 μm and
The pitch is the same as in the example of FIG. Therefore, in the present embodiment, the maximum storage gate length (19 μm in the example of FIG. 1 is maximum) is 13 μm, which is smaller than that of the example of FIG. 1 even if the pitch is the same. Usually, since the transfer speed is inversely proportional to the square of the gate length, the charge transfer device of this embodiment has an advantage that the transfer speed is more than doubled as compared with the conventional transfer device shown in FIG.
発明の効果 以上のように本発明は、実施例で述べた2相駆動の転送
部について1ビットを、従来の4ゲート4領域構成にく
らべて、4(以上)ゲート6(以上)領域構成になし
て、ゲート電極のない2領域を設けたことによって、敷
衍すると、一導電型基板上に形成された反対導電型の少
なくとも3つの領域を、相隣り合う各領域毎互いに濃度
を異ならせて、周期的に設け、前記反対導電型領域のう
ちの少なくとも1つの領域は、直上に電極を持たず、残
余の前記反対導電型領域の直上に絶縁ゲート電極を設
け、このゲート電極に与えられる転送用信号で電荷転送
を行うことによって、より高速電荷転送の可能な電荷転
送装置を得ることができ、その実用的効果は大なるもの
がある。EFFECTS OF THE INVENTION As described above, according to the present invention, one bit of the two-phase drive transfer section described in the embodiment is configured as a 4 (or more) gate 6 (or more) area configuration as compared with the conventional 4 gate 4 area configuration. By providing the two regions without the gate electrode, if at least three regions of opposite conductivity type formed on the one conductivity type substrate are made to have different concentrations from each other in adjacent regions, Periodically provided, at least one of the opposite conductivity type regions does not have an electrode directly above, and an insulated gate electrode is provided immediately above the remaining opposite conductivity type region, and a transfer electrode provided to this gate electrode is provided. By performing charge transfer with a signal, a charge transfer device capable of higher-speed charge transfer can be obtained, and the practical effect thereof is great.
第1図は従来のCCD断面図、第2図は従来のCCDのポテン
シャル図、第3図はその駆動パルス図、第4図は本発明
の構造断面図、第5図はそのポテンシャル図、第6図は
第4図の駆動パルス図である。 11……P型基板、12,13,14……それぞれ濃度の異なるN
ウエル領域、20,21……ゲート。FIG. 1 is a conventional CCD sectional view, FIG. 2 is a conventional CCD potential diagram, FIG. 3 is a driving pulse diagram thereof, FIG. 4 is a structural sectional view of the present invention, FIG. 5 is a potential diagram thereof, and FIG. FIG. 6 is a drive pulse diagram of FIG. 11 …… P-type substrate, 12,13,14 …… N with different concentrations
Well area, 20, 21 ... Gate.
Claims (1)
によって順次転送する電荷転送部として、一導電型基板
上に形成された少なくとも3つの反対導電型領域を、相
隣り合う各領域毎互いに濃度を異ならせて、周期的に有
し、前記反対導電型領域のうちの少なくとも1つの領域
は、直上に電極を持たず、前記転送用信号に依存しない
固定電位を保ち、残余の前記反対導電型領域は、直上の
絶縁ゲート電極に与えられる前記転送用信号で、変動電
位を生じる構成をそなえたことを特徴とする電荷転送装
置。1. A charge transfer section for sequentially transferring a predetermined charge in a bit unit in accordance with a transfer signal, wherein at least three regions of opposite conductivity type formed on a substrate of one conductivity type are provided for each adjacent region. Concentrations are made different from each other and periodically provided, and at least one region of the opposite conductivity type regions does not have an electrode immediately above and maintains a fixed potential independent of the transfer signal, and the remaining opposite regions. The charge transfer device according to claim 1, wherein the conductivity type region is configured to generate a fluctuating potential by the transfer signal given to the insulating gate electrode immediately above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59171877A JPH0682693B2 (en) | 1984-08-17 | 1984-08-17 | Charge transfer device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59171877A JPH0682693B2 (en) | 1984-08-17 | 1984-08-17 | Charge transfer device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6149472A JPS6149472A (en) | 1986-03-11 |
JPH0682693B2 true JPH0682693B2 (en) | 1994-10-19 |
Family
ID=15931448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59171877A Expired - Lifetime JPH0682693B2 (en) | 1984-08-17 | 1984-08-17 | Charge transfer device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0682693B2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0404306A3 (en) * | 1989-06-19 | 1991-07-17 | Tektronix Inc. | Trench structured charge-coupled device |
JPH04337670A (en) * | 1991-05-14 | 1992-11-25 | Sony Corp | Ccd shift register |
KR20010003830A (en) * | 1999-06-25 | 2001-01-15 | 김영환 | Solid state image pickup device and method of fabricating the same |
JP5428491B2 (en) * | 2009-04-23 | 2014-02-26 | ソニー株式会社 | Method for manufacturing solid-state imaging device |
JP6211898B2 (en) * | 2013-11-05 | 2017-10-11 | 浜松ホトニクス株式会社 | Linear image sensor |
JP6348272B2 (en) * | 2013-11-05 | 2018-06-27 | 浜松ホトニクス株式会社 | Charge coupled device, method for manufacturing the same, and solid-state imaging device |
CN113447616B (en) * | 2021-06-22 | 2022-09-02 | 成都归谷环境科技有限责任公司 | PWM output value calculation method of CO2 sensor |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS575361A (en) * | 1980-06-11 | 1982-01-12 | Toshiba Corp | Charge transfer device |
JPS59115556A (en) * | 1982-12-22 | 1984-07-04 | Toshiba Corp | Charge transfer type shift register |
-
1984
- 1984-08-17 JP JP59171877A patent/JPH0682693B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS575361A (en) * | 1980-06-11 | 1982-01-12 | Toshiba Corp | Charge transfer device |
JPS59115556A (en) * | 1982-12-22 | 1984-07-04 | Toshiba Corp | Charge transfer type shift register |
Also Published As
Publication number | Publication date |
---|---|
JPS6149472A (en) | 1986-03-11 |
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