JPS6149472A - Charge transfer device - Google Patents

Abstract

PURPOSE:To increase a transfer rate by forming three or more of reverse conduction type regions having mutually different concentration per one bit onto a substrate. CONSTITUTION:N well regions 12-14 are shaped to a P type substrate 11. The regions 12 are maximized and the regions 14 are minimized in concentration. 15, 16 represent storage gates and 17 barrier gates. An electrode P1 applying phi1 pulses and an electrode P2 applying phi2 pulses each have three gate structure, and there are differences among the potential of several electrode P1, P2 by differences among the concentration of the regions 12-14 under respective gate even when pulses phi1, phi2 are at a low level as time t1. Pulses phi1 are at a high level on the timing of time t2, and transfer charges 19 are stored under the gates 15, 16. Since pulses phi1 are at the low level and pulses phi2 at the high level at t3, charges 19 are transferred under the gates 15, 16. In the constitution, gate length is shortened even when pitches are the same. Since a transfer rate is inversely proportional to the square of gate length, the transfer rate is increased by twice or more according to the constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a charge transfer device, and more particularly to a long contact type COD image sensor in which a plurality of steps are arranged.

Conventional configurations and their problems In recent years, the development of so-called contact image sensors in which a plurality of -dimensional solid-state image sensors are arranged in an array 1- is the same size as a document, and some of them have reached the level of practical use. It has been reached.

FIG. 1 shows a cross-sectional view of the main transfer part of a conventional contact-type C0D-dimensional solid-state imaging device, and FIG. 2 shows the timing 1. of FIG. 3. , 12. In FIG. 1, 1 is a P-type substrate, 2 is an N-well region, and 3 is a barrier region, which is of the same conductivity type as the N-well region 2 and has a lower concentration than the N-well region 2. 4 is an accumulation gate, 5
is a barrier gate, and 6 is a gate oxide film. Pl
is φ1. P2 is an electrode for applying the φ2 pulse. Note that 7 in FIG. 2 is a transfer charge, which is transferred from the left side to the right side. Since the contact type sensor has a one-to-one correspondence, the pixel pitch is larger than that of the condensing type sensor, and the dimension of the transfer section is accordingly larger. For example, in the case of 16 pixels/mm, the gate length of the storage gate 4 in Fig. 1 is 1
9 μm, the gate length of barrier gate 6 is 12.2511
m, which is a pitch of 62.6 μm for 1 bit of CCD. In addition, in a condensing type sensor, for example, the storage gate is 9 μm, the barrier gate is 5 μm, and the CCD has a 1 bit of 28 μm.
It is.

As described above, the contact type COD sensor requires a gate length that is more than twice as long as the condensing type sensor, and its high-speed operation is significantly degraded.

OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks of the prior art, the present invention provides a charge transfer device capable of higher speed.

Structure of the Invention To achieve this object, the charge transfer device of the present invention comprises:
This is a charge transfer device that enables high-speed operation by increasing the number of gates per bit.

DESCRIPTION OF EMBODIMENTS Reference will now be made to the drawings for embodiments of the invention. 11 is a P-type substrate, 12, 13, and 14 are N-well regions, and the concentration is the highest in the N-well region 12 and the lowest in the N-well region 14. 15 and 16 are storage gates, 17 is a barrier gate, and 18 is a gate oxide film. P, is φ
1. P2 is an electrode for applying the φ2 pulse. FIG. 5 shows potentials for each of timings t1 to t5 in FIG. In FIGS. 4 to 6, the φ1 electrode P and the φ2 electrode P2 each have a three-gate structure, and as at time t1, the pulse φ4. Even when φ2 is at low level, each electrode P1. P2 is the region 12 under each gate
．． The difference in concentration between 13 and 14 creates a potential difference. Next, at time t2, the pulse φ1 is at a high level, and the transferred charge 19 is transferred to the gates 15 and 16.
The gate 17 acts as a barrier to prevent charge backflow. Next, at time t3, the pulse φ is low and the pulse φ2 is high, so the transfer charge 19 is transferred below the gates 15 and 16 of the P2 electrode. In the embodiment of FIG. 4, the storage gate 15
The gate length of 1 gate 16 is 13μm.
m /'< The gate length of IJ Yagate 17 is 8.25
The CGDI bit in μm is 62.5 pm. Therefore, in this embodiment, the gate length (in the example of FIG. 1, the maximum is 19 μm) is 13 μm at the maximum, and even if the pitch is the same, the gate length is smaller. Since the transfer speed is normally inversely proportional to the square of the gate length, the charge transfer device of this embodiment has the advantage that the transfer speed is more than twice as high as that of the conventional device.

FIG. 7 shows a sectional view of the main part of the transfer section of a contact type COD imaging device in another embodiment of the present invention, and the same numbers as in FIG. 4 indicate the same parts. Also, 20 is an accumulation gate,
21 is a barrier gate.

Pl and P2 are electrodes to which φ and φ2 are applied, respectively. FIG. 8 shows potentials for each of the timings 1 to t3 in FIG. 6. In FIGS. 6 to 8, when both the φ1 electrode P1 and the φ2 electrode P2 are at low level, that is, at timing t1, the N well region 12.1
Regions 3 and 14 have different potentials due to the difference in concentration of the N well. At timing t2, pulse φ1
becomes the no-i level, and the transferred charge 19 is transferred to the storage gate 2.
0, and the barrier gate 21 acts as a barrier to prevent charge backflow. Next, at timing t3, the P transfer charge 19 is transferred below the storage gate 20 of the P2 electrode. Looking at FIG. 8, the bold line in the figure is the potential below the N well region 14. Since there is no gate above the N well region 14, the potential is N
Depending only on the concentration of the well, the potential of each gate 12 and 13 of pulse φ1 or φ2 rises and falls according to the high level and low level, centering on the potential of region 4, and charges are transferred. I understand.

In the embodiment shown in FIG. 7, the storage gate is 13 μm, the barrier gate is 10 μm, and the length of the N-well region 4 without a gate is 8 μm.
．． With a thickness of 25 μm, data can be transferred at a speed more than twice that of the conventional example, as shown in the embodiment shown in FIG.

Effects of the Invention As described above, the present invention has the advantage that 1 bit in the transfer section is replaced by 4 bits in the transfer section.
By changing the structure from four gate regions to four or more gate regions and six or more gate regions, a charge transfer device capable of higher speed can be obtained, and its practical effects are significant.

Fig. 1 is a sectional view of a conventional COD, Fig. 2 is a potential diagram of a conventional CCD, Fig. 3 is a driving pulse diagram thereof, Fig. 4 is a structural sectional view of the present invention, and Fig. 5 is a potential diagram thereof. 6 is a drive pulse diagram of FIG. 4, FIG. 7 is a structural sectional view of another embodiment of the present invention, and FIG. 8 is a potential diagram of FIG. 7.

11...P-type substrate, 12,13.14...
・N-well regions with different concentrations, 15 to 17, 20
゜21...Gate.

Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 - Figure 7 I Figure 8

Claims (2)

[Claims] (1) A charge transfer device having a substrate of one conductivity type and three or more regions of opposite conductivity type formed on the substrate and having mutually different concentrations per bit, the three or more regions having different potentials. (2) The charge transfer device according to claim 1, wherein gate electrodes are formed at at least two locations on three or more regions.