JPS60120557A - Solid state image pick-up device having antiblooming structure - Google Patents

Abstract

PURPOSE:To obtain a solid stage image pick-up sensor having an antiblooming structure without shortening the gate length of a shift register by providing a blooming suppression element in a photoreceptor in a CCD image line sensor. CONSTITUTION:Antiblooming gates 19, 21 are disposed at both right and left sides of a photodiode array 22 so that antiblooming gates 19, 21 operate for both even and odd bits. Signal charge 29 photoelectrically converted by the array 22 is accumulated in a potential well determined by the potential under a photogate 24 by a gate voltage applied to the photogate 24, and transferred through a transfer gate 26 to a CCD analog shift register 27. Excess signal charge generated when the light amount exceeding the saturated exposure amount is emitted, overrides the potential barrier under the gate 19 and drops to the antiblooming drain 20.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention relates to a solid-state imaging device that has advantages such as small size, light weight, low power consumption, and high reliability, and particularly relates to a plumping phenomenon that adversely affects the characteristics of the solid-state imaging device. The present invention relates to a solid-state imaging device that adopts a method of providing a pluminder suppressing element structure as a countermeasure to this problem.

[Prior art]

In conventional solid-state imaging devices, especially in CCD (charge-coupled device) image line sensors, when the amount of light irradiated to the PN junction light receiving diode exceeds its saturation exposure amount, the excess charge generated overflows, which is called pluming. A phenomenon has occurred.

One of the technical measures against this pluming phenomenon is
There is a method of providing an anti-pluming f-) and an anti-pluming drain adjacent to the light-receiving diode as shown in FIGS.

FIG. 1 is a sectional view of the light receiving section and anti-pluming element structure of a CCD image line sensor.

In the figure, broken lines indicate potential profiles at the bottom of each part. When the signal charges 6 were excessively distributed and the anti-pluming gate 4 was not provided, they would flow into the CCD analog shift register beyond the transfer gate 2 and cause a pluming phenomenon, but the anti-pluming gate 4, and by setting the potential barrier under the anti-pluming gate 4 lower than the potential barrier under the transfer gate 2, it is possible to cause the excess signal charge 3 to exceed the transfer gate 2. Pass through anti-pluming gate 4.

It flows into the anti-pluming drain 5, making it possible to suppress the pluming phenomenon. Note that 1 is a photodiode buried layer. .

FIG. 2 is a structural block diagram of a CCD image line sensor having the anti-pluming gate structure shown in FIG. 1. In this conventional structure.

Photodiode - CC on one side of dimensional (linear) row 7
It has a structure in which a D analog shift register 10 is provided, and an anti-pluming gate 11 and an anti-pluming drain 12 are provided on the other direction side. Therefore, since the photoelectrically converted signal charge 8 can only be output to one side of the photodiode array 7, the limit of microfabrication in the r-to of the CCD analog shift register 10 makes it difficult to reduce the pixel pitch, that is, to increase the number of pixels. It had the disadvantage of being extremely difficult. Note that 9 is a transfer dart.

In addition, one of the major technical bottlenecks in COD image line sensors, where the integration of multiple pixels is progressing rapidly, is the limit to the reduction of dart length in CCD analog shift registers due to the reduction of pixel pitch. This is also a challenge for microfabrication technology.

In the COD image line sensor, this problem is dealt with by adopting a structure as shown in FIG. 3. The signal charge 8 photoelectrically converted by the photodiode 13 is transferred to the CCD analog shift registers 16 and 17 provided on both the left and right sides of the photodiode row 7 for each even number bit and odd number bit, respectively, and output boot 1.
8, the outputs of even and odd bits are combined and output. Note that 14.15 is a transfer dart. By adopting this method, compared to the method shown in Figure 2 in which the signal charge is transferred only to one side of the photodiode, the dart length of the CCD analog shift register has twice the margin. It becomes possible to hold the .

However, in this structure, it was impossible to provide the blooming suppressing element shown in FIG. 2 without making any changes. This is because the signal charge transfer direction is determined to be one direction of the photodiode due to the anti-pluming gate.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks in a multi-pixel CCD image line sensor of a type in which even bits and odd bits are transferred separately (even bit separation transfer type). It is an object of the present invention to provide a solid-state imaging device having an anti-pluming structure that alleviates reduction in length and makes it possible to provide a pluming suppressing element.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIGS. 4A and 4B show a first embodiment of the present invention. In this first embodiment, an anti-pluming gate 19 and an anti-pluming drain 20 are included in the light receiving part structure of a conventional even-odd bit separation transfer type (or dual channel type) image line sensor as shown in FIG. It has been established. Figure 4B is the fourth
This is a cross-sectional view taken along the line I-I in Figure A, and a potential profile corresponding to each section indicated by the broken line. Anti-Pluming Dirt 19.21
are arranged on both the left and right sides of the photodiode array 22, so that the anti-pluming gates 19 and 21 act on both even and odd bits. In this arrangement, if only the anti-blooming gates 19, 2+ are provided, the side opposite to the anti-blooming drain 20,
That is, at the bottom of c-tzl in the signal charge transfer direction,
A potential barrier similar to that under the anti-pluming gate 19 is generated to prevent signal charge transfer.

Therefore, in order to form a buried portion 21 that does not need to become an anti-pluming dirt and remove a potential barrier, N-type impurity is selectively diffused 23 under the anti-pluming e-) 21 in the signal charge transfer direction. Do the following.

Next, the operation of the first embodiment will be explained.

In FIGS. 4A and 4B, the photodiode 22
The photoelectrically converted signal charge 29 is transferred to the photodart 2.
Photo due to dart voltage applied to 2? -G (PG)
C is accumulated in the potential well determined by the lower potential of 24 and transferred through the transfer dart (TG) 26
It is transferred to the OD analog shift register 27. Also,
Excess signal charges generated when the amount of light exceeding the saturation bath light amount is irradiated exceeds the potential barrier at the bottom of the anti-pluming f-419 and falls into the anti-pluming drain 20. Therefore, the groominder phenomenon caused by excessive signal charges is suppressed. However, the conditions for causing this operation are as follows.

ψji〈−kuψN〈ψode D) Here, the potential under the transfer dart when ψ're' is accumulated is ψABG 'the potential under anti-pluming boot ψPG 'huo)P-) is the potential ψABG (D
): Potential of embedded part under anti-pluming boot The effects of the first embodiment are as follows.

Based on the above explanation, in the first embodiment, an anti-pluming P-) and an anti-pluming drain are provided in the even/odd bit separation transfer type COD image line sensor as shown in FIG. The generated potential barrier in the direction of signal charge transfer is removed by injecting N-type impurities into that portion and selectively forming a buried layer. By adopting this structure, it is possible to reduce the gate length of the CCD analog shift resistor due to the reduction of the pixel pitch while taking measures against the plumping phenomenon. 6D, which can be alleviated by dividing it into left and right sides,
Application to multi-pixel sensors becomes easier. Since the buried layer under the anti-pluming gate can be formed at the same time as the buried layer of the COD analog shift register, the pluming suppressing element can be formed using the same manufacturing process as the conventional method.

Next, FIG. 5 shows a second embodiment of the present invention. In this embodiment, the method of removing the potential barrier in the signal charge transfer direction in the first embodiment is performed by selectively changing the oxide film thickness (30) instead of impurity implantation.

With this method as well, it is possible to provide a pluming suppressing element and maintain a margin in the gate length of the COD analog shift resistor for adopting the even-odd bit separation transfer method. The operation of this embodiment is essentially exactly the same as that shown in the first embodiment. Moreover, the effect is the same as that shown in the first embodiment, except that the step of selectively changing the oxide film thickness is increased.

FIGS. 6A and 6B show a third embodiment of the present invention. In this example, the photo ff-) 24 and the anti-pluming f-) 19.2 in FIG.
1 in common with 1? -) 31, and is provided in the light receiving part structure of an even/odd bit separation transfer type CCD image line sensor.

Here, in order to create a difference between the potential at the bottom of the part that will become photo e-t 24 and the potential at the bottom of the part that corresponds to anti-plumend r-t 19°21, the part corresponding to photo f-24 is N-type impurity injection layer 3
2 is formed. Essentially as described in the second embodiment,
This third embodiment can also be implemented by adopting a method of selectively changing the oxide film thickness in order to provide a difference in potential.

The operation of the third embodiment is essentially the same as that shown in the first embodiment. However, the operating conditions in this case are as follows.

ψ'ro<toB. Kuψa. (=9n4n)) Kokote, ψ
TG 'Transfer during storage? -) Lower potential ψABG: Potential ψA under anti-pluming boot. (-ψABG(D)): Photogate (=Anti-Pluming Gate) The effect of the third embodiment is to reduce the two f-) in the first and second embodiments to 1. If you make it into a book, it will have the following effects.

(1) Since the photogate and the anti-pluming gate are formed by one common dart, there is no need to provide f-) as the anti-pluming gate.

(2) Since it can be provided in the light receiving section of an even-odd bit separation transfer type COD image line sensor, it is possible to provide a pluming suppressing element and reduce the pixel pitch.

(3) It is possible to manufacture by the same process as the conventional process without requiring a complicated manufacturing process.

The present invention is a method for forming an anti-pluming structure that can be provided in the light-receiving part structure of an even-odd bit separation type CCD image line sensor. This has the advantage that length reduction can be alleviated. Therefore, this is a very effective configuration method when a pluming suppression element is to be provided in a multi-pixel COD image line sensor with a reduced pixel pitch.

〔Effect of the invention〕

Since it can be installed in the light receiving section of an even-odd bit separation transfer type COD image line sensor, it is possible to provide a pluming suppression element and reduce the pixel pitch, and does not require a complicated manufacturing process. Moreover, it has the excellent effect that it can be manufactured using the same process as the conventional process.

[Brief explanation of the drawing]

Figure 1 shows a COD with a conventional anti-pluming structure.
A cross-sectional view of the light receiving section of an image line sensor, Fig. 2 is a block diagram of a CCD image line sensor with a conventional anti-pluming structure, and Fig. 3 is a structural block diagram of a conventional even-odd bit separation transfer type CCD image line sensor. , FIG. 4A is a cross-sectional view taken along line iI of the light receiving part in FIG. 4A of the anti-chip according to the first embodiment of the present invention,
FIG. 5 is a cross-sectional view of the light receiving section of an even-odd bit separation transfer type CCD image line sensor having an anti-pluming structure, which is a second embodiment of the present invention, and FIG. 6A is a third embodiment of the present invention. FIG. 6B, which is a structural diagram of an even-odd bit separation type COD image line sensor having a certain anti-pluming structure, is a cross-sectional view taken along the line ■--■ of the light receiving section in FIG. 6A. DESCRIPTION OF SYMBOLS 1... Photodiode buried layer, 2... Transfer group (TG), 3... Excess signal charge, 4... Anti-pluming gate (ABC), 5... Anti-pluming drain, 6 ...Photoelectrically converted signal charge, 7.
...Photodiode row, 8...Signal charge, 9...
Transfer dirt (TG), 10...COD analog shift register. 11°°° anti-pluminlt'-t (ABG),
12...Anti-pluming drain (ABD), 1
3...Photodiode row, 14.15...Transfer r
-) (TO), 16.17...CCD7 Naroda shift reso star, 18...Output dart (OG), 19.
21...Anti-pluming gate (ABC), 20
...Anti-Pluming Drain (ABD), 22.
...Photodiode buried layer, 23...Anti-blooming? -) Lower impurity injection layer (accumulation dirt), 24,
25...Photograph (PG), 26...
・Transfer Gut (TG), 27. 28...CCD analog shift register, 29...
Excess signal charge, 30... Dirt oxide film, 31... Photo dirt or anti-pluming gate, 32...
7 Buried layer (accumulation dirt) under Otogut or anti-pluming, 33...Transfer dirt (TG), 34...
・Anti-pluming drain (ABD), 35...
Photodiode, 36... CCD analog shift register, 37... Output l'-) (OG), a s...
- Photoelectrically converted signal charge %39...Excess signal charge. Patent Applicant: Oki Electric Industry Co., Ltd. Procedural Amendment July 16, 1988 Manabu Shiga, Commissioner of the Patent Office 1, Indication of Case 1982 Patent Application No. 2269432, Title of Invention Solid-state imaging device with anti-pluming structure 3. Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent Ai + Ii Correct Order No. 1” (Sho fl + Year Month 1)
1 (Voluntary) 6. Contents of each column 7t11i+I of Detailed explanation of the invention and brief description of drawings subject to amendment 8AMB'tF As shown in the attached sheet 7. Contents of amendment 1) Specification page 5, line 3 "7" is corrected to "13". 2) On page 6, line 2, "even number" is corrected to "even/odd number." 3) Page 6, line 13, page 8, last line, page 10, line 3, page 14, page 12, line 4, page 11, page 13, line 1, page 13, line 13,
The 16th line of the same page and the last line of the same page each change the “even-odd bit” to “even/odd bit”.
"odd bits", corrected. 4) On page 7, line 18, "22" is corrected to "24".

Claims (3)

[Claims] (1) A common electrode is provided to sandwich the photodiode rows arranged in one row, and the common electrode has a first means functioning as an anti-pluming P-) and a signal charge accumulating device. the first means and the second means are in contact with one end and the other end of the photodiode and are arranged alternately in the arrangement direction of the photodiode. A solid-state imaging device characterized by: (2) the first means is a bias application means for setting a potential as anti-pluming P-);
2. The solid-state imaging device according to claim 1, wherein said second means is means for selectively doping an impurity under said common electrode to remove a potential barrier. (3) The first means is a bias application means for setting a potential as an anti-blooming boot,
2. The solid-state imaging device according to claim 1, wherein the second means is means for removing the Q potential barrier by selectively reducing the thickness of the oxide film under the common electrode.