JPH0682823B2 - Solid-state imaging device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a solid-state imaging device, and more particularly to the structure of a photosensitive pixel portion thereof.

[Technical background of the invention]

FIG. 4 shows a cross-sectional structure of a photosensitive region and its peripheral portion of a conventional charge transfer type solid-state imaging device. That is, 1 is a semiconductor substrate of one conductivity type (for example, P-type silicon), 2 is a semiconductor region of a conductivity type (N-type) opposite to that of the substrate 1, and is a photosensitive pixel portion having a PN photodiode structure together with the P-type substrate. Is formed. 3 has the same conductivity type as the substrate 1 and has a high impurity concentration
A channel stop region formed of a P ^{+ type} semiconductor region for preventing signal charges generated in the photosensitive pixel portion from flowing out in a direction other than an output gate described later, 4 is an insulating film formed on a substrate, and 5 to 8 are They are an output gate electrode, a storage electrode, a shift gate electrode, and a transfer electrode of a charge-coupled (CCD) register, which are formed in a double-layer structure in the insulating film 4. A plurality of the photosensitive pixel portion regions 2 are formed on the surface of the semiconductor substrate 1 in a linear arrangement, for example.
Is formed as a first layer electrode above the output gate substrate region adjacent to the photosensitive pixel region 2, the storage electrode 6 is formed as a second layer electrode adjacent thereto, and the first layer is adjacent thereto. The shift gate electrode 7 is formed as an electrode, and the transfer electrode 8 of the CCD register is provided for each transfer stage in the direction perpendicular to the drawing. Reference numeral 9 is a light shielding film provided on the insulating film 4 except for the photosensitive region, and 10 is a protective film.

FIG. 5 shows a zero potential on the substrate 1 and the channel stop region 3 of the solid-state image pickup device, and a potential distribution in the substrate when a predetermined DC voltage or drive pulse is applied to each of the electrodes 5 to 8 and its change. The flow of signal charges is shown. That is, V ₅ is a gate potential under the output gate electrode 5 to which a constant DC voltage V _G is applied, and V ₆ is a constant DC voltage V _S (>
V _G ) is the potential of the potential well formed below the storage electrode 6, and V _7H and V _7L are shift gates corresponding to the high (H) level and the low (L) level of the applied shift pulse. The potentials under the electrode 7, V _8H and V _8L, are the potentials under the transfer electrode 8 corresponding to the high (H) level and the low (L) level of the applied transfer pulse.

Therefore, the signal charge Q generated by irradiating the photosensitive pixel portion with the light input is stored in the potential well below the storage electrode 6 via the output gate electrode 5, and is further controlled by the shift gate below the shift gate electrode 7. Transfer electrode 8
Transferred down. This charge is transferred to the output section (not shown) by the CCD register, and the charge-voltage conversion is performed to become the output voltage.

[Problems of background technology]

By the way, in the above-described photosensitive pixel portion having the PN photodiode structure, the potential V ₂ in the equilibrium state when there is no incident light is generally deeper (larger) than the potential V ₅ under the output gate electrode 5 because of thermionic emission. Therefore, the signal charge Q generated in the photosensitive pixel portion passes under the output gate electrode 5 and then passes through the storage electrode 6
In the process of outputting downward, a time delay of charge output occurs, which causes an afterimage phenomenon in the output image of the solid-state imaging device.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and provides a solid-state imaging device capable of suppressing afterimages with a small time delay when signal charges are output from a photosensitive pixel portion in the direction of an adjacent gate. .

[Outline of Invention]

That is, the solid-state imaging device of the present invention defines the transfer direction of the signal charge, which is composed of the first-conductivity-type semiconductor substrate and the first-conductivity-type semiconductor region provided in the substrate and having an impurity concentration higher than that of the substrate. A channel stop region, a first semiconductor region of the second conductivity type partially provided in a surface region of the substrate surrounded by the channel stop region, and a surface of the first semiconductor region, and A photosensitive pixel region that generates a signal charge in response to incident light, which is constituted by a second semiconductor region of a first conductivity type whose peripheral portion is in contact with a channel stop region and has an impurity concentration higher than that of a substrate; Is provided adjacent to the area in the transfer direction,
An output gate stage through which the signal charge generated in the photosensitive pixel region is passed, and a charge storage provided adjacent to the output gate stage in the transfer direction and storing the signal charge passing through the output gate stage And a shift gate stage which is provided adjacent to the charge storage stage in the transfer direction and shifts the signal charge stored in the charge storage stage to the register unit in response to a shift pulse. The potential distribution in the substrate depth direction in the region where the first semiconductor region and the second semiconductor region overlap is maintained at the same potential as the channel stop region from the surface of the second semiconductor region to a certain depth.
Further, it has a potential well in a deeper portion, and the depth of this potential well is the shallowest part of the potential of the output gate stage when the signal charge passes through the output gate stage and the potential of the channel stop region. It is characterized by being set in the middle of.

In the solid-state imaging device having the above-described configuration, the depth of the potential well provided below the region where the first semiconductor region and the second semiconductor region overlap is set to the output gate stage when the signal charge passes through the output gate stage. A state in which the signal charge generated in the photosensitive pixel region can be quickly moved to the charge storage stage that exists after the output gate stage by setting the potential between the shallowest part of the potential and the potential of the channel stop region. Is obtained. Therefore, the signal charge generated by the light incident on the photosensitive pixel region can be moved to the charge storage stage in the complete transfer mode by drift and diffusion, and the signal charge can be stored quickly in the charge storage stage. You can

Therefore, the time delay of the output can be eliminated, and the afterimage phenomenon caused by this delay can be suppressed.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to the drawings.

1 (a) and 1 (b) show a cross-sectional structure and a plane layout pattern of a photosensitive region and its peripheral portion of a solid-state image pickup device, which are different from those of the conventional example described with reference to FIG. The structure and the arrangement relationship between the photosensitive pixel portion and the channel stop region are different, and the others are the same.
The same reference numerals as those in the figure are given, the description thereof is omitted, and the different parts will be mainly described below.

That is, in the photosensitive pixel portion, the N-type semiconductor region 11 is formed with a constant space d between it and the channel stop region 3, and a part of the N-type semiconductor region 11 penetrates into the substrate region under the output gate electrode 5. There is. Further, a P ^{+ -type} semiconductor region 12 is formed so as to cover the entire surface of the N-type region 11 with one boundary below the one end of the output gate electrode 5 on the photosensitive pixel side as a boundary and to overlap the peripheral portion with the channel stop region 3. ing. In the present embodiment, in the photosensitive pixel portion having the three-layer structure of the P ^{+ type} region 12, the N type region 11 and the P type substrate 1, the impurity concentration and depth of each region are as shown by the dotted line in FIG. It is formed so as to have a uniform potential distribution. That is, up to a certain depth in the vicinity of the surface of the P ^{+ -type} region 12, the same zero potential as that of the channel stop region 3 is not depleted, and the depletion layer is generated inside the substrate deeper than that. Therefore, the potential well 20 is formed inside the substrate away from the surface.

The potential of the potential well 20 is attracted toward the zero potential because the P ^{+ type} region 12 has the zero potential. Therefore,
The deepest potential depth V ₂₀ of the potential well 20 is set to the output gate electrode 5
It can be determined between the shallowest potential depth V ₅ of the potential well formed below and the zero potential of the channel stop region 3. When the potential distribution is formed in this way, the potential depth V ₂₀ of the potential well 20 is always shallower than the potential depth V ₅ under the output gate electrode 5, and is kept constant without being affected by this potential or the like. .

Therefore, in the solid-state imaging device shown in FIG. 1 (a), the potential distribution in the substrate is changed to the potential well 20 as shown in FIG.
Potential depth V _20, the output gate electrode 5 potential depth V ₅ of the potential wells formed under, can be successively deeper in the order of the potential depth V ₆ of the potential well formed under the storage electrode 6 .

As described above, the signal charge Q generated in the photosensitive pixel portion is formed below the storage electrode 6 by sequentially increasing the potential depth V ₂₀ , the potential depth V ₅ , and the potential depth V _6. The potential well can be transferred in the complete transfer mode by drift and diffusion without the time delay of the charge output as in the conventional case. Since the signal charge Q is transferred to the potential well formed under the storage electrode 6 without causing a time delay in charge output, the afterimage phenomenon in the output image of the solid-state imaging device can be suppressed.

In the substrate region below the output gate electrode 5, an N-type region 11
Part of is invading. In the potential well formed below the output gate electrode 5, there is a portion corresponding to this intrusion portion, where the potential depth is deeper than the shallowest potential depth V ₅ . When the signal charge Q passes under the output gate electrode 5, the signal charge Q is temporarily accumulated in the deep portion, and a time delay of charge output occurs. However, by making the area of the overlapping portion of the N-type region 11 and the substrate region under the output gate electrode 5 as small as possible, the capacitance of this overlapping portion can be made sufficiently smaller than the capacitance of the photosensitive pixel portion. This is possible, and the time delay due to the overlapping portion at the time of charge output can be ignored, and the occurrence of the afterimage phenomenon is suppressed.

It is also possible to form the N-type region 11 by self-alignment using the output gate electrode 5 as a mask so that the N-type region 11 has a boundary in contact with the lower part of one end of the output gate electrode 5, but it is actually manufactured. In many cases, the structure of the above-described embodiment is obtained due to process restrictions.

Further, the P ^{+ -type} region 12 can be realized by a simple manufacturing process so as to have a boundary below one end of the output gate electrode 5 by forming the P ^{+ -type} region 12 by self-alignment using the output gate electrode 5 as a mask. .

Further, in the above-mentioned embodiment, since the channel stop region 3 and the N-type region 11 are formed with a certain distance therebetween, both regions 3,
It has the effect of increasing the breakdown voltage between 11 and.

Although there is a case where the output gate adjacent to the photosensitive pixel portion is not necessary due to the circuit configuration of the solid-state image pickup device, generally, the output gate for passing the signal charge or accumulating the signal charge is provided adjacent to the photosensitive pixel portion. The present invention can be effectively applied to a solid-state imaging device having a structure in which a gate is adjacent to a photosensitive pixel portion in many cases including a gate and a gate for controlling signal charges.

〔The invention's effect〕

As described above, according to the solid-state imaging device of the present invention, the photosensitive pixel portion is formed by the semiconductor region having the three-layer structure, and the potential of the photosensitive pixel portion can be controlled by appropriately determining the impurity concentration and the depth of each region. Since the potential is set to be shallower than the potential of the adjacent gate and the potential of the photosensitive pixel portion is maintained at the potential determined by the three-layer structure, the time delay when the signal charge is output from the photosensitive pixel portion is almost zero. It is possible to suppress the afterimage phenomenon without causing any problems.

[Brief description of drawings]

FIG. 1 (a) is a cross-sectional view showing the main part of an embodiment of the solid-state imaging device according to the present invention, and FIG. 1 (b) is a section B- in FIG.
The figure which shows the plane arrangement pattern which follows the B'line, FIG.
FIG. 3 is a diagram showing an example of a potential distribution along the line II-II ′ of the semiconductor region of the three-layer structure forming the photosensitive pixel portion of FIG. 3A, and FIG. 3 shows the potential distribution in the substrate of FIG. FIG. 4 is a cross-sectional view showing a part of a conventional solid-state imaging device, and FIG. 5 is a diagram showing the potential distribution in the substrate and the movement of signal charges in FIG. Is. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 3 ... Channel stop region, 5 ... Output gate electrode, 11 ... 1st semiconductor region of a photosensitive pixel part, 12 ...
A second semiconductor region of the photosensitive pixel portion.

Claims (3)

[Claims] 1. A semiconductor substrate of a first conductivity type, and a channel stop region, which is provided in the substrate and comprises a semiconductor region of a first conductivity type having a higher impurity concentration than the substrate, and which defines a transfer direction of signal charges. A first semiconductor region of the second conductivity type partially provided in a surface region of the substrate surrounded by the channel stop region and a surface of the first semiconductor region and a peripheral portion thereof Contact with the channel stop region,
A photosensitive pixel region configured to generate a signal charge in response to incident light, the photosensitive pixel region including a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the substrate, and being adjacent to the photosensitive pixel region in the transfer direction. Is provided,
An output gate stage through which the signal charges generated in the photosensitive pixel region pass, and is provided adjacent to the output gate stage in the transfer direction,
A charge storage stage that stores the signal charge that has passed through the output gate stage and a charge storage stage that is provided adjacent to the charge storage stage in the transfer direction and stores the signal charge stored in the charge storage stage according to a shift pulse. A shift gate stage that shifts to the register portion by a shift gate stage, and a potential distribution in a substrate depth direction in a region where the first semiconductor region and the second semiconductor region overlap with each other is from a surface of the second semiconductor region. At a certain depth, the potential is maintained at the same potential as the channel stop region and further has a potential well in a deeper portion thereof, and the potential depth of the potential well is determined when the signal charge passes through the output gate stage. Of the potential of the output gate stage and the potential of the channel stop region, and the potential is sequentially increased in the order of the potential well, the output gate stage, and the charge storage stage. The solid-state imaging device according to claim. 2. The solid-state imaging device according to claim 1, wherein a boundary of the second semiconductor region on the output gate stage side is in contact with the output gate stage. 3. A predetermined space is provided between the first semiconductor region and the channel stop region, and the first semiconductor region and the channel stop region are separated from each other. The solid-state imaging device according to claim 1, wherein the solid-state imaging device according to claim 1.