JPH03246952A - Charge-coupled device - Google Patents

Abstract

PURPOSE:To enhance reliability and to realize a good charge transfer operation by a method wherein transfer electrodes in one transfer stage are constituted of two kinds of conductors whose work function is different. CONSTITUTION:An n-type buried channel 2 is formed on the surface of a p-type silicon substrate 1; a plurality of transfer electrodes 4 are formed on it via a gate insulating film 3. The electrodes 4 are constituted of the following: metal electrodes 41 which cover the first half in the transfer direction of electric charges; and metal electrodes 42 which cover its latter half and which are piled up on the electrodes 41. Consequently, the channel 2 is endowed with the asymmetry of a potential distribution in such a way that parts of the electrodes 41 act as storage parts and that parts of the electrodes 42 act as barrier parts. When two-phase clock voltages whose phases have been shifted by 180 deg. are applied alternately to the electrodes 4, signal charges are transferred sequentially from the left to the right. Thereby, reliability is enhanced, and a good charge transfer operation can be executed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a charge-coupled device (CCD) having a fine electrode structure.
Regarding.

(Prior Art) Recently, the increase in the number of pixels in CCD imaging devices has been remarkable. A two-dimensional CCD imaging device is usually composed of a photodiode array that stores signal charges through photoelectric conversion, and a vertical CCD and a horizontal CCD that read out the signal charges of the photodiode array. The CCD in these CCD imaging devices usually uses two layers of transfer electrodes that overlap each other with an interlayer insulating film interposed therebetween. However, with the recent increase in the number of pixels and miniaturization of each part of the CCD, a problem has arisen in that short-circuit accidents between the first layer transfer electrode and the second layer transfer electrode often occur.

The reason for this is that the transfer electrode is usually formed of a polycrystalline silicon film, and the interlayer insulating film is an oxide film obtained by thermally oxidizing this transfer electrode, so the quality is not very good, and the thickness of the interlayer insulating film also scales. This means that it gradually becomes thinner, etc.

To solve this problem, a single layer transfer electrode structure with no overlap can be used, as was the case with CCDs in the early stages of development. However, in this negative layer transfer electrode structure, potential barriers, potential pockets, etc. are formed in the cap portions between the transfer electrodes, resulting in a reduction in signal charge transfer efficiency.

On the other hand, in a two-phase drive CCD, it is necessary for charge transfer to impart asymmetry to the potential distribution formed in the transfer channel within the -transfer electrode. In other words, a potential well within the transfer electrode or a deeper potential distribution is provided in the storage portion. For this purpose, ions are usually implanted partially under the transfer electrode. For example, in the case of an n-type buried channel configuration, an n + -type layer is formed in the storage section below the transfer electrode and in front in the charge transfer direction. In the case of a two-layer transfer electrode structure, it is easy to form the structure in self-alignment with the n-type layer transfer electrode of such an accumulation section. However, in the case of a negative layer transfer electrode, it is not possible to form an n+ type layer in self-alignment therewith. Therefore, when each part of the CCD is miniaturized, various inconveniences arise. That is, due to misalignment of the mask or lateral diffusion of the n+ type layer impurity in the accumulation portion, the n' type layer is formed out of the desired position. For example, if the n+ type impurity reaches below the adjacent transfer electrode in the forward direction in the transfer direction, an unnecessary potential pocket is formed in the transfer channel. Furthermore, when the transfer electrode reaches the rear end in the transfer direction, the barrier section disappears, causing problems in charge accumulation and transfer.

(Problem to be solved by the invention) As described above, with the miniaturization of the transfer stage of CCD, the occurrence of short-circuit accidents increases in the two-layer transfer electrode structure, and in the case of two-phase drive COD, one transfer electrode When impurity ions are implanted to give an asymmetry to the potential distribution underneath, there are problems such as rediffusion of the impurities and the formation of unnecessary potential pockets, or a loss of distinction between the accumulation part and the barrier part.

An object of the present invention is to provide a CCD that solves these problems.

[Structure of the Invention (Means for Solving the Problems)] The CCD of the present invention includes a semiconductor substrate on which a transfer channel is formed, and a plurality of CCDs are formed in an array on the transfer channel region of this substrate via an insulating film. The transfer electrode is comprised of two types of conductors each having a different work function.

Another CCD according to the present invention includes a semiconductor substrate on which a transfer channel is formed, and a plurality of CCDs are formed in an array on the transfer channel region of this substrate with a first insulating film interposed therebetween, without overlapping each other. Transfer electrodes each made of two types of conductors having different work functions, and a second insulating film formed so as to cover at least the gap between the transfer electrodes on the surface where these transfer electrodes are formed. . The transfer channel potential of the gap portion is set to the “H” level potential of the transfer channel under the transfer electrode and the “L” level potential of the transfer channel under the transfer electrode.
The present invention is characterized by comprising: a gap potential control electrode that is set to an intermediate level potential;

Still another CCD of the present invention includes: a semiconductor substrate on which a transfer channel is formed; a plurality of transfer electrodes formed in an array on the transfer channel region of the substrate with a first insulating film interposed therebetween without overlapping each other; A second insulating film was formed so as to cover at least the gap between the transfer electrodes on the surface where the transfer electrodes were formed. A gap potential control electrode for setting the transfer channel potential of the gap portion to an intermediate level between the "H level" potential and the "L" level potential of the transfer channel under the transfer electrode, and an in-phase clock of the plurality of transfer electrodes are applied. and a clock potential control circuit that provides a potential difference between two adjacent transfer electrodes.

(Function) According to the present invention, by configuring the transfer electrode of the -transfer stage with two types of conductors having different work functions, an asymmetry in the potential distribution is formed under the -transfer electrode. Therefore, it is possible to achieve good charge storage and transfer even with a transfer electrode having a fine structure, without the formation of unnecessary potential pockets due to rediffusion of the impurity diffusion layer or the elimination of the distinction between the storage part and the barrier part.

Further, the same effect can be obtained by providing a clock potential control circuit that externally applies different potentials to two adjacent transfer electrodes constituting one transfer stage to which clocks of the same phase are applied.

Furthermore, when the transfer electrode is W14a without overlap, by providing a gap potential control electrode that controls the potential of the gap part, high charge transfer efficiency can be obtained while preventing electrode short-circuit accidents when miniaturized. be able to.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the basic structure of a two-phase drive CCD according to an embodiment of the present invention. An n-type buried channel 2 is formed on the surface of a p-type silicon substrate 1 (the entire p-type substrate may be a p-type substrate, or an n-type substrate with a p-type well formed therein. The same applies to the following embodiments). A plurality of transfer electrodes 4 are formed in an array thereon with a gate insulating film 3 interposed therebetween. Each transfer electrode 4 is
It is composed of a first metal electrode 4 that covers the front half in the charge transfer direction, and a second metal electrode 42 that covers the rear half and partially overlaps the first metal electrode 41 . Here the first
Metal electrode 4. is the work function of the second metal electrode 42
The one that is larger than that of is selected. As a result, in the transfer electrode 4, the portion of the first metal electrode 41 becomes an accumulation portion, and the portion of the second metal electrode 4□ becomes a barrier portion.
Transfer channel 2 is given an asymmetry in potential distribution.

When two-phase clock voltages with a phase shift of 180° are alternately applied to the transfer electrodes 4, the signal charges are sequentially transferred from the left side to the right side of the figure.

In this embodiment, unlike the conventional method in which a storage section is formed under a transfer electrode by ion implantation of impurities, defects such as defective charge transfer and destruction of the storage section caused by diffusion of impurities do not occur.

FIG. 2 shows a two-phase drive CCD according to a more improved embodiment of the present invention.
It is. In the structure shown in FIG. 1, if the gap between the transfer electrodes is large, a potential pocket is formed in the transfer channel at this portion, causing charge to be left behind. Therefore, in FIG. 2, in addition to the basic structure shown in FIG.
is formed. That is, by applying a predetermined control potential to the gap potential control electrode 7, the channel potential of the gap 5 between the transfer electrodes 4 or an intermediate value between the "H" level potential and the "L" level potential of the transfer channel is set. That's what I do.

The charge transfer operation of the CCD shown in FIG. 2 will be explained using FIG. 3. FIG. 3(a) shows the potential distribution of the transfer channel and the charge transfer during the transition period when the two-phase clock changes to the "H" level and φ2 changes to the "L" level in this embodiment. It shows the situation.

Below each transfer electrode 4, there is an asymmetrical potential in which the potential of the storage part under the first metal electrode 41 is higher than the potential of the barrier part under the second metal electrode 4, that is, φH1>φH2+ φ, 1>φ1□. The distribution is formed. As already mentioned, this is due to the difference in the work function of the electrode metals.

Potential φ at the gap. is determined by the control potential applied to the gap potential control electrode 7 and the influence of the potential of the transfer electrode 4 (so-called two-dimensional effect). The "H" level potential φ, (2) is set lower than the "L" level potential φ, (2) of the rear barrier section in the transfer direction.

As a result of controlling the gap potential in this way, the clock φ1
completely goes to “H” level, and clock φ2 completely goes to “H” level.
When the signal becomes L" level, the signal charge under the φ2 electrode is transferred to the φ1 electrode without leaving anything behind.

For comparison, FIG. 3(b) shows the potential distribution in the case where there is no gap potential control electrode. In this case, since the gap potential φ6 is higher than the "H" level potential φH2 of the barrier portion in the front direction in the charge transfer direction, this portion becomes a potential pocket and signal charges are left behind.

Next, an embodiment in which the present invention is applied to a CCD imaging device will be described.

FIG. 4 is a schematic plan view showing an embodiment of an interline transfer type CCD imaging device. Figure 5 (a) (b) (c
) are a plan view and a sectional view showing the main structure. On a p-type silicon substrate 11, photodiodes 12 made of an n-type diffusion layer that perform photoelectric conversion and storage are arranged in a two-dimensional array. A plurality of vertical transfer CCDs for reading signal charges of each photodiode 12 are formed in parallel with this photodiode array. 13 or its vertical transfer CC
D is an n-type buried channel. and vertical transfer CCD
A horizontal transfer CCD is provided for reading out the transferred signal charges one horizontal column at a time.

25 is an n-type buried channel of the horizontal transfer CCD. A transfer cage 20 is formed between the vertical CCD and the horizontal CCD. Transfer electrodes 15 are arranged on the vertical transfer CCD channel 13 with a small gap 18 therebetween, with a gate insulating film 14 interposed therebetween, as shown in FIG.

The transfer electrode 15 is composed of a first metal electrode 151 that covers the storage section, and a second metal electrode 15□ that covers the barrier section and is partially overlaid on the first metal electrode 151.

The first metal electrode 151 is selected to have a work function greater than that of the second metal electrode 152. A transfer electrode 28 having a similar structure is also provided on the horizontal transfer CCD channel 25.
are formed into an array. A p+ type layer 19 serving as a channel stop is formed on the photodiode 12 side of the vertical CCD channel 13. A gap control electrode 17 is further provided on the surface on which the elements are formed in this manner via an interlayer insulating film 16.
26.27 is formed of an All film. These control electrodes 17, 26, 27 also serve as a light shield film. Therefore, the gap control electrode 17 of the vertical CCD section is
It is necessary to form a window in at least a portion of the photodiode 12. For example, in the example shown in FIG. 5, these are arranged in a stripe shape along the vertical CCD channel 13. The gap control electrode 26 of the horizontal CCD section almost entirely covers the horizontal CCD area.

Control potential V applied to the gap control electrode 17 of the vertical CCD section. 1 and the control potential VG2 applied to the gap control electrode 26 of the horizontal CCD section are set to different values in this embodiment. Specifically, vo2 is V. Set higher than 1. This is because the clock pulse voltages are different between the vertical CCD and the horizontal CCD. That is, the so-called field shift gate, which reads out the signal charge of the photodiode 12 to the vertical CCD channel 13, is also in common with the transfer electrode of the vertical CCD in this embodiment, as is usually done (see FIG. 5). b)). Therefore, in order to transfer the signal charge read out from the photodiode 12 to the vertical CCD channel 13 by applying a positive voltage to the field shift gate without causing it to flow back to the photodiode 12 side, the vertical CCD transfer electrode 15 has, for example, , -8V to Ov are used.

In contrast, in horizontal CCDs, positive clock pulses varying between OV and 5V are used. On the other hand, the channel potential of the gap portion formed by the gap control electrode needs to be determined in relation to the pulse voltage applied to the transfer electrode, as explained above with reference to FIG. Then, vertical CC
In order to set the gap potential to a preferable value between the "H° level potential" and the "L" level potential of the transfer channel in the D and horizontal CCDs, respectively, as explained in FIG. 3, VC+ must be lower than V62. It has to be.

The operation of the interline transfer CCD imaging device of this embodiment is the same as that of conventionally known devices.

In other words, the signal charge of the photodiode array is read out to the vertical CCD during the vertical blanking period of imaging, and the next field is imaged while being output by the vertical CCD transfer and the horizontal CCD transfer by horizontal column. Repeat the action.

In this embodiment, both the vertical CCD and the horizontal CCD are driven in two phases. The specific state of signal charge transfer in these vertical CCDs and horizontal CCDs will be explained using FIGS. 6(a) and 6(b).

FIG. 6(a) shows a two-phase clock φ1. This is the waveform of φ2. FIG. 6(b) shows the channel potential distribution under the transfer electrode at times t1 and t2 of the clock waveform.

As shown in the figure, the clock φ,.

By alternately repeating "L" and "H" of φ2,
Signal charges are transferred along the transfer channel. and gears, similar to those described in the previous embodiment.

Due to the function of the control electrode, no barriers or potential gaps are formed in the transfer channel that would impede the transfer of signal charges, and signal charges are transferred without leaving anything behind.

FIGS. 7(a) to 7(g) are cross-sectional views showing the manufacturing process of the vertical CCD section of the CCD imaging device of this embodiment. To briefly explain the manufacturing process, a gate oxide film 14 is first formed on a p-type silicon substrate 11 (FIG. 7(a)), and then an n-type buried channel 13 is formed by ion implantation of phosphorus (FIG. 7(a)). b)). Thereafter, a metal electrode film of node 1 is deposited (FIG. 7(C)), and patterned through a PEP process to separately form a plurality of first metal electrodes 151 (FIG. 7(d)). Subsequently, a second metal electrode film is deposited (FIG. 7(e)). This is similarly patterned through the PEP process, and a second metal electrode 15° is formed, partially overlapping the first metal electrode 15□. Separate and form (7th
Figure (r)). The gap 18 between the transfer electrodes is determined by the patterning process of the second metal electrode 15□. Finally C
After covering with a VD insulating film 16, a gap control electrode 17 is formed of an Al film or the like (FIG. 7(g)).

As described above, according to this embodiment, since no overlapping electrodes are used, it is possible to prevent electrode short-circuit accidents in the case of miniaturization, and also, by utilizing the difference in work function, an accumulation section can be formed within one transfer electrode. Since the barrier portion is formed, there is no problem caused by lateral diffusion of impurities, and by controlling the gap potential, it is possible to obtain a two-phase drive type CCD imaging device that achieves high charge transfer efficiency.

In the above embodiments, the case where different types of metal electrodes are used in the storage part and the barrier part has been explained. It is possible to use a suitable combination of conductors included.

Furthermore, in the above embodiments, the storage part and the barrier part in the transfer electrode are configured by changing the work functions of the electrodes, or the electrodes of the storage part and barrier part are formed separately from the same material.
By externally applying different biases to these, they can function as an accumulation section and a barrier section. Such an embodiment will now be described.

FIG. 8 shows such an embodiment of a two-phase CCD. Fifth
The same reference numerals as in FIG. 5 are given to parts corresponding to those in the figure.

An n-type buried channel 13 is formed in a p-type silicon substrate 11, and a plurality of transfer electrodes 21 obtained by patterning a single-layer conductive film are formed in an array thereon with a gate insulating film 14 interposed therebetween. Here, the transfer electrode 21 constitutes one transfer stage to which two adjacent electrodes 21□ and 21□ are applied with clocks of the same phase, and the electrode 211 serves as a barrier portion and the electrode 212 serves as an accumulation portion. On the surface on which the transfer electrodes 21 are formed, a gap potential control electrode 23 is provided so as to cover at least the gap between each transfer electrode 21 via an interlayer insulating film formed by CVD. Separately from the CCD chip, a clock φ1. An external drive circuit 24 is provided to generate φ2. On the other hand, in order to apply different bias potentials to the two electrodes 211, 21□ constituting the above-mentioned transfer stage, at least one clock potential control circuit 25 is installed for each clock φ1φ2, in addition to the drive circuit 24.
is provided. That is, clock φ1. φ2 directly enters electrode 21 of the barrier section of one transfer stage, and electrode 2 of the storage section.
These input to the clock signal 12 via the clock potential control circuit 25 as clocks φl and φ2' having different DC levels.

FIG. 9 shows a specific configuration example of the clock potential control circuit 25. It is composed of voltage dividing resistors R, , R2 that divide the power supply V to obtain a constant bias potential, a clamp diode D1, and a bypass capacitor C.

FIG. 10 shows the clock pulse waveform in the CCD in this embodiment. Clock φ1.Ov obtained from the external drive circuit 24 as a reference. For φ2, a clock φφ2′ shifted from a positive DC level is obtained through the clock potential control circuit 25.

According to this embodiment, the electrodes of the storage part and the barrier part have a single-layer transfer electrode structure in which they are formed separately from the same material, and the clock potentials of the storage part and the barrier part are externally controlled, resulting in an asymmetrical potential. A two-layer driving CCD with a distributed distribution is obtained. According to this embodiment, as in the previous embodiment, a highly reliable CCD can be obtained because no impurity diffusion layer is used to distinguish between the storage section and the barrier section, and no overlapping electrode structure is used. Further, as in the previous embodiment, by controlling the gap potential using the gap potential control electrode 23, it is possible to perform good charge transfer without leaving any charges behind.

By the way, in configuring the CCD system of this embodiment, it is preferable that the clock potential control circuit be placed within or near the CCD chip. A specific example of the system configuration is as follows.

FIG. 11 shows an example of the system configuration.

31 is, for example, a CCD image sensor chip, which includes a two-phase drive CCD 3 having single-layer transfer electrodes 33+, 33□.
2 is formed. The electrode 3B+ constitutes a barrier section,
Electrode 332 constitutes a storage section. A clock drive circuit 35 is provided separately from the image sensor chip 31. and C
Within the CD image sensor chip 31, electrodes 33. One clock potential control circuit 34 is provided for each of the two-phase clock signal lines to provide a potential difference between the clock signal lines 332 and 332.

FIG. 12 shows another example of the system configuration. The difference from FIG. 11 is that the clock potential control circuit 34 is configured as a control circuit chip 36 separate from the CCD image sensor chip 31,
This is packaged in the same package 37 as the CCD image sensor chip 31.
This is a point that is incorporated within the system.

By arranging the clock potential control circuit for creating a potential difference between the barrier section and the storage section of the CCD in or near the CCD chip, the signal charge transfer efficiency may be reduced due to the influence of external noise. can be effectively prevented.

The present invention is not limited to the above embodiments.

For example, although a buried channel type CCD has been described in the embodiment, the present invention can be similarly applied to a surface channel type CCD. The present invention can also be applied to p-channel CCDs that use holes as signal charges. In this case, the magnitude relationship of the work functions of the transfer electrodes is opposite to that in the embodiment.

The pond water invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, an impurity diffusion layer is not used to distinguish between the storage part and the barrier part of the transfer electrode, and an overlapping electrode structure is not used.
D is obtained. In addition, by controlling the gap potential using the gap potential control electrode, it is possible to perform good charge transfer with no charge left behind.

[Brief Description of the Drawings] Fig. 1 is a sectional view showing the main structure of a two-phase drive CCD according to one embodiment of the present invention, and Fig. 2 shows the main structure of a two-phase drive CCD according to another embodiment. 3(a) and 3(b) are diagrams showing the transfer channel potential distribution for explaining the charge transfer operation of the CCD, and FIG. 4 is a diagram showing the present invention applied to an interline transfer type CCD imaging device. A plan view of the embodiment, FIG. 5(a), (b), and (c) are plan views showing the main structure in an enlarged manner, and its xx' and Y-Y' cross-sectional views, and FIG. 6(a) (b) is a diagram showing the clock waveform and the potential distribution of the transfer channel to explain its operation, and FIG.
a) to (g) are cross-sectional views showing the manufacturing process of the vertical CCD section, FIG. 8 is a diagram showing the main part configuration of a two-phase drive CCD of another embodiment, and FIG. 9 is a diagram of the clock potential control circuit. 10 is a diagram showing a clock waveform, FIG. 11 is a diagram showing an example of the configuration of the CCD system of the same embodiment, and FIG. 12 is a diagram showing an example of the configuration of another CCD system. be. 1...p-type silicon substrate, 2...n-type buried channel, 381. Gate insulating film, 4... Transfer electrode, 41.
...First metal electrode, 42...Second metal electrode, 56
1. Gap, 6... Interlayer insulating film, 7... Gap potential control electrode, 11... P-type silicon substrate, 12...
・Photodiode, 13...Vertical CCD channel,
14... Gate insulating film, 15... Vertical CCD transfer electrode, 15. ...First metal electrode, 15□...Second metal electrode, 16...Interlayer insulating film, 17,26.27.
...Gap potential control electrode, 18...Gap, 19
... Channel stop, 20 ... Transfer gate, 28
... Horizontal CCD transfer electrode, 21 ... Transfer electrode, 23
...Gap potential control electrode, 24...Clock drive circuit, 25...Clock potential control circuit, 31...C
CD image sensor chip, 32... CCD section, 33...
Transfer electrode, 34... Clock potential control circuit, 35...
- Clock drive circuit, 6... Control circuit chip, 7... Package.

Claims (4)

[Claims] (1) A semiconductor substrate on which a transfer channel is formed, and a plurality of transfer electrodes formed in an array on the transfer channel region of this substrate via an insulating film, each made of two types of conductors with different work functions. A charge-coupled device comprising: (2) A semiconductor substrate on which a transfer channel is formed, and two types of semiconductor substrates each having a different work function, each of which has a plurality of semiconductor substrates formed in an array on the transfer channel region of this substrate without overlapping each other with a first insulating film interposed therebetween. A transfer electrode formed of a conductor, and a transfer channel potential of the gap portion formed via a second insulating film so as to cover at least the gap portion between the transfer electrodes on the surface where these transfer electrodes are formed. A charge-coupled device comprising: a gap potential control electrode for setting the voltage to an intermediate level between the "H" level potential and the "L" level potential of the transfer channel under the transfer electrode. (3) A semiconductor substrate on which a transfer channel is formed, a plurality of transfer electrodes formed in an array on the transfer channel region of this substrate with a first insulating film interposed therebetween, without overlapping each other, and these transfer electrodes are formed. The transfer channel potential of the gap portion is formed via a second insulating film so as to cover at least the gap portion between the transfer electrodes on the surface where the transfer electrodes are formed, and the “H” level potential of the transfer channel under the transfer electrode and “ a gap potential control electrode for setting an intermediate L'' level potential; and a clock potential control circuit for providing a potential difference between two adjacent transfer electrodes to which in-phase clocks of the plurality of transfer electrodes are applied. A charge-coupled device characterized by: (4) The charge coupled device according to claim 3, wherein the clock potential control circuit is formed within the charge coupled device chip or within a package containing the charge coupled device chip.