JP3020537B2 - Charge-coupled device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a charge-coupled device (CCD) having a fine electrode structure.
About.

(Prior Art) Recently, the number of pixels of a CCD imaging device has been remarkable. A two-dimensional CCD image pickup device generally includes a photodiode array that stores signal charges by photoelectric conversion, and a vertical CCD and a horizontal CCD that read out signal charges of the photodiode array. In these CCD imaging devices
Usually, two layers of transfer electrodes overlapping each other via an interlayer insulating film are used for the CCD. However, with the recent increase in the number of pixels and the miniaturization of each part of the CCD, there has been a problem that a short circuit between the first-layer transfer electrode and the second-layer transfer electrode often occurs. The reason is that the transfer electrode is usually formed of a polycrystalline silicon film, and the interlayer insulating film is an oxide film obtained by thermally oxidizing the transfer electrode, so that the quality is not very good, and the thickness of the interlayer insulating film is also scaled. Is gradually becoming thinner.

To solve this problem, as in the case of the early CCD development, a further non-overlapping transfer electrode structure may be used. However, in this one-layer transfer electrode structure, a potential barrier, a potential pocket, and the like are formed in gaps between the transfer electrodes, and the transfer efficiency of signal charges is reduced.

On the other hand, in the two-phase drive CCD, it is necessary for charge transfer to impart asymmetry to the potential distribution formed in the transfer channel in one transfer electrode. That is, a potential distribution is provided such that the potential well in the transfer electrode becomes deeper in the accumulation portion. For this purpose, ion implantation is usually performed partially below the transfer electrode. For example, in the case of an n-type buried channel configuration, an n ⁺ -type layer is formed in a storage portion below a transfer electrode and in front of a charge transfer direction. In the case of a two-layer transfer electrode structure, it is easy to form such an n ⁺ -type layer of the storage portion in a self-aligned manner with the transfer electrode. However, in the case of a single-layer transfer electrode, it is not possible to form an n ⁺ -type layer in a self-aligned manner. Therefore, when each part of the CCD is miniaturized, various problems occur. That is, the n ⁺ -type layer is formed so as to be deviated from a desired position due to misalignment of the mask or lateral diffusion of the n ⁺ -type layer impurity in the accumulation portion. For example, when the n ⁺ -type impurity reaches below the adjacent transfer electrode forward in the transfer direction, an unnecessary potential pocket is formed in the transfer channel. In addition, when the transfer electrode reaches the rear end in the transfer direction, the barrier portion disappears, which hinders charge accumulation and transfer.

(Problems to be Solved by the Invention) As described above, with the miniaturization of the transfer stage of the CCD, the occurrence of short circuit accidents increases in the two-layer transfer electrode structure, and one transfer electrode like the two-phase drive CCD. When impurity ions are implanted to give an asymmetry of the potential distribution below, there is a problem in that unnecessary potential pockets are formed due to the re-diffusion of the impurities, or the storage portion and the barrier portion cannot be distinguished.

An object of the present invention is to provide a CCD that solves such a problem.

[Structure of the Invention] (Means for Solving the Problems) In a charge-coupled device according to the present invention, a semiconductor substrate on which a transfer channel is formed and a transfer channel region of the substrate are overlapped with each other via a first insulating film. A plurality of transfer electrodes arranged without wrapping, and the gap portion formed via a second insulating film so as to cover at least the gap portion between the transfer electrodes on the surface on which the transfer electrodes are formed. And a gap potential control electrode for setting the transfer channel potential at an intermediate level between the “H” level potential and the “L” level potential of the transfer channel below the transfer electrode.

It is preferable that the transfer electrode is composed of two types of conductors having different work functions.

Further, the charge-coupled device of the present invention comprises a semiconductor substrate on which a transfer channel is formed, and a plurality of transfer electrodes arranged on a transfer channel region of the substrate without overlapping each other via a first insulating film. And a clock potential control circuit that applies a potential difference between two adjacent transfer electrodes to which the in-phase clocks of the plurality of transfer electrodes are applied.

The charge-coupled device is formed with a second insulating film interposed therebetween so as to cover at least gaps between the transfer electrodes on a surface on which the transfer electrodes are formed. It is preferable to further include a gap potential control electrode for setting the transfer channel between the “H” level potential and the “L” level potential.

(Operation) According to the present invention, asymmetry of potential distribution is formed under one transfer electrode by forming the transfer electrode of one transfer stage with two types of conductors having different work functions. Therefore,
Good charge accumulation and transfer can be achieved even with a transfer electrode having a fine structure without forming unnecessary potential pockets by re-diffusion of the impurity diffusion layer or eliminating the distinction between the accumulation portion and the barrier portion.

The same effect can be obtained by providing a clock potential control circuit that externally applies different potentials to two adjacent transfer electrodes forming one transfer stage to which a clock of the same phase is applied.

Furthermore, when the transfer electrodes have a non-overlapping structure, by providing a gap potential control electrode for controlling the potential of the gap, high charge transfer efficiency can be achieved while preventing electrode short-circuiting when miniaturized. Obtainable.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a basic structure of a two-phase drive CCD according to one embodiment of the present invention. An n-type buried channel 2 is formed on the surface of a p-type silicon substrate 1 (the whole may be a p-type substrate or a p-type well formed on an n-type substrate; the same applies to the following embodiments). A plurality of transfer electrodes 4 are arranged and formed on a gate insulating film 3 therebetween. Each transfer electrode 4
Second superimposed on the first metal electrode 4 ₁ and the part covering the rear half first metal electrode 4 ₁ on which covers the front half of the transfer direction of the charge
It is composed of metal electrodes 4 _2. Wherein the first metal electrode 4 _1, its work function that is selected larger than that of the second metal electrode 4 _2. Of the result transfer electrode 4, the first metal electrode 4 ₁ part becomes storage unit, such that the second metal electrode 4 ₂ parts result in a barrier unit, the asymmetry of the potential distribution in the transfer channel 2 Given.

When a two-phase clock voltage 180 ° out of phase is alternately applied to the transfer electrodes 4, the signal charges are sequentially transferred from the left side to the right side in the figure.

In this embodiment, unlike a conventional device in which a storage portion is formed below a transfer electrode by ion implantation of an impurity, a defect such as a charge transfer failure caused by impurity diffusion or a failure of the storage portion does not occur.

FIG. 2 shows a two-phase drive CCD according to a further improved embodiment of the present invention.
It is. In the structure of FIG. 1, if the gap between the transfer electrodes is large, a potential pocket is formed in the transfer channel at this portion, which causes the charge to be left behind. Therefore, in FIG. 2, in addition to the basic structure of FIG. 1, a gap potential control electrode 7 is formed on the surface on which the transfer electrode 4 is formed via an interlayer insulating film 6.
Is formed. That is, by applying a predetermined control potential to the gap potential control electrode 7, the channel potential of the gap 5 between the transfer electrodes 4 is set to an intermediate value between the "H" level potential and the "L" level potential of the transfer channel. Like that.

The charge transfer operation of the CCD shown in FIG. 2 will be described with reference to FIG. Figure 3 (a) in this embodiment, the two-phase clock, phi ₁ is changed to the "H" level, phi ₂ is "L" in the transition period that varies the level transfer channel potential distribution and the charge The state of transfer is shown. Each transfer electrode 4 down, the potential of the storage portion 4 ₁ under the first metal electrode is higher than the potential of the barrier section of 4 ₂ under the second metal electrodes, i.e. _{φ H1> φ H2, φ L1} > φ L2
Is formed. This is due to the difference in the work function of the electrode metal as described above. The potential φ _{G of the} gap portion is determined by the control potential applied to the gap potential control electrode 7 and the influence of the potential of the transfer electrode 4 (a so-called two-dimensional effect). In this embodiment, the gap potential φ _G is: The potential is set so as to be lower than the “H” level potential φ _H2 of the barrier part in the front in the transfer direction and higher than the “L” level potential φ _L2 of the barrier part in the rear in the transfer direction.

As a result of controlling the gap potential in this manner, the clock φ
₁ has become completely "H" level, the clock phi ₂ is completely "L" level, the signal charges under the phi ₂ electrode is transferred without removal failure under phi ₁ electrode.

FIG. 3B shows, for comparison, a potential distribution in the case where there is no gap potential control electrode. In this case, the gap potential phi _G is, since the higher than "H" level potential phi _H2 of the charge transfer direction in front of the barrier portion, this portion becomes a potential pocket, leftover signal charge occurs.

Next, an embodiment in which the present invention is applied to a CCD imaging device will be described.

FIG. 4 is a schematic plan view showing an embodiment of an interline transfer type CCD imaging device. Fig. 5 (a) (b) (c)
FIG. 2 is a plan view and a cross-sectional view showing the structure of the main part. On a p-type silicon substrate 11, photodiodes 12 are formed two-dimensionally by an n-type diffusion layer for performing photoelectric conversion and accumulation. A plurality of vertical transfer CCDs for reading out the signal charges of each photodiode 12 in parallel with this photodiode array
Are formed. Reference numeral 13 denotes an n-type buried channel of the vertical transfer CCD. A horizontal transfer CCD for reading the signal charges transferred by the vertical transfer CCD one by one horizontal column is provided. Reference numeral 25 denotes an n-type buried channel of the horizontal transfer CCD. A transfer gate 20 is formed between the vertical CCD and the horizontal CCD. On the vertical transfer CCD channel 13, transfer electrodes 15 are arranged and formed with a small gap 18 via a gate insulating film 14, as shown in FIG. Transfer electrode 15
It includes a first metal electrode 15 ₁ that covers the storage portion, and a second metal electrode 5 ₂ Metropolitan superimposed on the first metal electrode 15 ₁ part covers the barrier section. The first metal electrode 15 _1, the work function is selected larger than that of the second metal electrode 15 _2. Transfer electrodes 28 having the same structure are also arranged on the horizontal transfer CCD channel 25. On the photodiode 12 side of the vertical CCD channel 13, ap ⁺ type layer 19 serving as a channel stop is formed. A gap control electrode is further interposed on the surface on which the element is formed in this manner with an interlayer insulating film 16 interposed therebetween.
17, 26, 27 are formed by Al films. These control electrodes
17, 26 and 27 also serve as light shielding films. Therefore vertical
The gap control electrode 17 of the CCD section needs to be formed with a window at least in the portion of the photodiode 12. For example, in the example shown in FIG. It is arranged and formed along. The gap control electrode 26 in the horizontal CCD section covers almost the entire horizontal CCD area.

The control potential V _G2 applied to control potential V _G1 and the horizontal CCD of the gap control electrode 26 provided on the gap control electrode 17 of the vertical CCD portion in this embodiment is set to a different value. Specifically, V _G2 is set higher than V _G1. This is because the clock pulse voltage differs between the vertical CCD and the horizontal CCD. That is, the so-called field shift gate for reading the signal charges of the photodiode 12 to the vertical CCD channel 13 is common to the transfer electrode of the vertical CCD in this embodiment as is usually performed (FIG. 5 ( b)
reference). Therefore, by applying a positive voltage to the field shift gate, the vertical CCD channel 13
In order to transfer the signal charge read out to the photodiode 12 without backflow, the vertical CCD transfer electrode 15, for example,
A negative clock pulse varying from -8V to 0V is used. On the other hand, in a horizontal CCD, a positive clock pulse that changes in a range from 0 V to 5 V is used. On the other hand, the channel potential of the gap part by the gap control electrode is
As described above with reference to FIG. 3, it is necessary to determine the relationship with the pulse voltage applied to the transfer electrode. Then, vertical CC
In order to set the gap potential to a desirable intermediate value between the "H" level potential and the "L" level potential of the transfer channel in the D and horizontal CCDs as described with reference to FIG. 3, V _G1 is larger than V _G2 . You have to lower it.

The operation of the interline transfer CCD image pickup device of this embodiment is not different from that of a conventionally known device. That is, the signal charges of the photodiode array are read out to the vertical CCD during the vertical blanking period of the imaging, and this is transferred to the vertical CCD and the horizontal CCD.
The operation of imaging the next field while outputting the data by horizontal line transfer by the CCD is repeated.

In this embodiment, both the vertical CCD and the horizontal CCD are driven in two phases. The specific signal charge transfer in the vertical CCD and the horizontal CCD will be described with reference to FIGS. 6 (a) and 6 (b).

FIG. 6A shows the waveforms of the two-phase clocks φ ₁ and φ ₂ . Figure 6 (b), the time t ₁ and the clock waveform
shows the channel potential distribution under the transfer electrodes at t _2. As shown in the figure, the signal charges are transferred along the transfer channel by the clocks φ ₁ and φ ₂ alternately repeating “L” and “H”. As described in the previous embodiment, the barrier and potential pocket that hinder the transfer of signal charges are not formed in the transfer channel by the action of the gap control electrode.
The transfer of the signal charge is performed without being left behind.

7 (a) to 7 (g) are cross-sectional views showing the steps of manufacturing a vertical CCD section of the CCD imaging device of this embodiment. The manufacturing process will be briefly described. First, a gate oxide film 14 is formed on a p-type silicon substrate 11 (FIG. 7A), and then an n-type buried channel 13 is formed by ion implantation of phosphorus (FIG. 7). (B)). Thereafter, a first metal electrode film is deposited (the seventh metal electrode film).
Figure (c)), which is patterned through a PEP step for separating a plurality of first metal electrodes 15 ₁ (FIG. 7 (d)). Subsequently the second metal electrode film is deposited (FIG. 7 (e)), which likewise is patterned through the PEP process, the second metal electrode 15 in a state of overlapping a portion the first metal electrode 15 _{1 2} is formed separately (FIG. 7 (f)). In this second metal electrode 15 ₂ of the patterning step, it determines the gap 18 between the transfer electrodes. Finally, after covering with a CVD insulating film 16, a gap control electrode 17 is formed by an Al film or the like (FIG. 7 (g)).

As described above, according to this embodiment, an electrode short-circuit accident in the case of miniaturization can be prevented because the overlap electrode is not used, and the accumulation portion is stored in one transfer electrode by utilizing the difference in work function. And the barrier section, there is no problem due to the lateral diffusion of impurities, and by controlling the gap potential, it is possible to obtain a two-phase drive type CCD imaging device that realizes high charge transfer efficiency. .

In the above embodiments, the case where different types of metal electrodes are used for the storage portion and the barrier portion has been described. However, not only metal but also a material having conductivity substantially enough to be used as an electrode, that is, a transparent conductor or a semiconductor is used. It is possible to use a suitable combination of conductors.

Further, in the above embodiments, the storage portion and the barrier portion in the transfer electrode are configured by changing the work function of the electrode. However, the electrodes of the storage portion and the barrier portion are separately formed of the same material, and externally formed therewith. The functions of the storage section and the barrier section can be provided by applying different biases. Such an embodiment will now be described.

FIG. 8 shows a two-phase drive CCD of such an embodiment. Fifth
Parts corresponding to those in the figure are denoted by the same reference numerals as in FIG.
An n-type buried channel 13 is formed in a p-type silicon substrate 11, on which a plurality of transfer electrodes 21 obtained by patterning a single-layer conductor film via a gate insulating film 14 are arranged. Here, the transfer electrode 21 is composed of two adjacent electrodes 21.
_1, 21 ₂ is a constitute one transfer stage clock phase is applied, the electrode 21 ₁ is barrier section, the electrode 21 ₂ is the storage section. On the surface on which the transfer electrodes 21 are formed, a gap potential control electrode 23 is provided via an interlayer insulating film formed by CVD so as to cover at least a gap between the transfer electrodes 21. An external drive circuit 24 for generating clocks φ ₁ and φ ₂ is provided separately from the CCD chip. Whereas two electrodes 21 ₁ constituting one transfer stage described above, to provide different bias potentials 21 _2, separately from the drive circuit 24, the clock phi _1, phi ₂
, At least one clock potential control circuit 25 is provided. That is, the clocks φ ₁ and φ ₂ directly enter the electrode 211 of the barrier section of one transfer stage, and the electrodes 2 ₁ of the storage section.
1 ₂ This different clock phi ₁ of the direct current level through the clock voltage control circuit 25 for _', phi _2' enters a.

FIG. 9 is a specific configuration example of the clock potential control circuit 25. It is composed of voltage dividing resistors R ₁ and R ₂ for obtaining a constant bias potential by dividing the power supply V, a clamp diode D, and a bypass capacitor C.

FIG. 10 shows a clock pulse waveform in the CCD in this embodiment. Clock potential control circuit 25 responds to clocks φ ₁ and φ _{2 based on} 0 V obtained from external drive circuit 24.
Clocks φ ₁ ′ and φ ₂ ′ whose DC level is shifted in the positive direction are obtained.

According to this embodiment, there is a single-layer transfer electrode structure in which the electrodes of the storage section and the barrier section are separately formed of the same material, and the clock potential of the storage section and the barrier section is externally controlled so that the asymmetric potential A two-layer drive CCD in which the distribution is formed is obtained. According to this embodiment, a high-reliability CCD can be obtained because no impurity diffusion layer is used for distinguishing between the storage section and the barrier section, and no overlap electrode structure is used, as in the previous embodiment. In addition, as in the previous embodiment, by controlling the gap potential by the gap potential control electrode 23, it is possible to perform good charge transfer without remaining charge.

By the way, in configuring the CCD system of this embodiment, it is preferable that the clock potential control circuit is disposed in or near the CCD chip. A specific system configuration example is as follows, for example.

FIG. 11 shows an example of one system configuration. Reference numeral 31 denotes a CCD image sensor chip, for example, in which a single-layer transfer electrode 3 is provided.
3 _1, 33 two-phase driving CCD32 having ₂ are formed. Electrode 3
3 ₁ constitutes a barrier portion, the electrode 33 ₂ constitute a storage unit.
A clock drive circuit 35 is provided separately from the imaging element chip 31. And the CCD chip 31, the electrode 33 ₁ and 33
Clock potential control circuit 34 that gives a potential step between ₂
Are provided for each of the two-phase clock signal lines.

FIG. 12 is another system configuration example. The difference from FIG. 11 is that the clock potential control circuit 34 is
Separately, it is configured as a control circuit chip 36, and this is a CCD
The point is that it is incorporated in the same package 37 as the imaging element chip 31.

By arranging a clock potential control circuit to create a potential difference between the CCD barrier section and the accumulation section in or near the CCD chip, the transfer efficiency of signal charges is reduced due to external noise. Can be effectively prevented.

The present invention is not limited to the above embodiment. For example, in the embodiment, the buried channel type CCD is described, but the present invention can be similarly applied to a surface channel type. The present invention can also be applied to a p-channel CCD using holes as signal charges. In this case, the magnitude relation of the work function of the transfer electrode is opposite to that of the embodiment.

In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, since the impurity diffusion layer is not used for distinguishing the storage portion and the barrier portion of the transfer electrode and the overlap electrode structure is not used, a highly reliable CC
D is obtained. In addition, by controlling the gap potential by the gap potential control electrode, it is possible to perform good charge transfer without remaining charge.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a main part structure of a two-phase drive CCD according to one embodiment of the present invention. FIG. 2 is a cross-sectional view showing a main part structure of a two-phase drive CCD according to another embodiment. a) and (b) are diagrams showing a transfer channel potential distribution for explaining the charge transfer operation of the CCD. FIG. 4 is a plan view of an embodiment in which the present invention is applied to an interline transfer type CCD image pickup device. 5 (a), 5 (b) and 5 (c) are enlarged plan views showing the structure of the main part thereof and cross-sectional views thereof along XX 'and YY'. FIGS. 6 (a) and 6 (b) show the operation thereof. FIGS. 7 (a) to 7 (g) are cross-sectional views showing a manufacturing process of a vertical CCD portion, and FIGS. 8 (a) to 8 (g) are cross-sectional views showing a process of manufacturing the vertical CCD portion. FIG. 9 shows a configuration example of a clock potential control circuit of the phase drive CCD, FIG. 9 shows a configuration example of the clock potential control circuit, FIG. Diagram illustrating a configuration example of a CCD system of the embodiment, FIG. 12 is a diagram likewise illustrating a configuration example of another CCD systems. 1 .... p-type silicon substrate, 2 .... n-type buried channel,
3 ... gate insulating film, 4 ... transfer electrode, 4 ₁ ... first metal electrode, 4 ₂ ... second metal electrode, 5 ... gap, 6 ...
... Interlayer insulating film, 7 ... Gap potential control electrode, 11 ... p
Type silicon substrate, 12 …… Photodiode, 13 …… Vertical
CCD channel, 14 gate insulating film, 15 vertical CCD transfer electrode, 15 ₁ first metal electrode, 15 ₂ second metal electrode, 16 interlayer insulating film, 17, 26, 27 ... gap potential control electrode, 18 gap, 19 channel stop, 20
... Transfer gate, 28 ... Horizontal CCD transfer electrode, 21 ... Transfer electrode, 23 ... Gap potential control electrode, 24 ... Clock drive circuit, 25 ... Clock potential control circuit, 31 ... CCD image sensor chip, 32 ... CCD part, 33 ... transfer electrode, 34 ... clock potential control circuit, 35 ... clock drive circuit, 36 ... control circuit chip, 37 ... package.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-47-36773 (JP, A) JP-A-62-126671 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/339 H01L 27/14-27/148 H01L 29/762-29/768

Claims (5)

(57) [Claims] A semiconductor substrate on which a transfer channel is formed; a plurality of transfer electrodes arranged on a transfer channel region of the substrate via a first insulating film without overlapping each other; The transfer channel potential of the gap formed through the second insulating film so as to cover at least the gap between the transfer electrodes on the surface on which is formed the "H" level potential of the transfer channel below the transfer electrode. And a gap potential control electrode for setting the potential at an intermediate level between the "L" level potentials. 2. The transfer electrode according to claim 1, wherein the transfer electrode comprises two types of conductors having different work functions.
A charge-coupled device according to claim 1. 3. A semiconductor substrate on which a transfer channel is formed; a plurality of transfer electrodes arranged on a transfer channel region of the substrate via a first insulating film without overlapping with each other; And a clock potential control circuit for providing a potential difference between two adjacent transfer electrodes to which an in-phase clock of the transfer electrodes is applied. 4. A transfer channel potential of said gap portion, which is formed through a second insulating film so as to cover at least a gap portion between said transfer electrodes on a surface on which said transfer electrode is formed, is set to a voltage lower than said transfer electrode. “H” level potential and “L” of transfer channel
4. The charge-coupled device according to claim 3, further comprising a gap potential control electrode for setting the gap potential at an intermediate level potential. 5. The clock potential control circuit according to claim 3, wherein said clock potential control circuit is formed in a charge-coupled device chip or in a package containing said charge-coupled device chip.
Or the charge-coupled device according to 4.