JPS60105382A - Solid-state pickup element - Google Patents

Solid-state pickup element

Info

Publication number
JPS60105382A
JPS60105382A JP58212886A JP21288683A JPS60105382A JP S60105382 A JPS60105382 A JP S60105382A JP 58212886 A JP58212886 A JP 58212886A JP 21288683 A JP21288683 A JP 21288683A JP S60105382 A JPS60105382 A JP S60105382A
Authority
JP
Japan
Prior art keywords
groove
substrate
semiconductor substrate
solid
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58212886A
Other languages
Japanese (ja)
Inventor
Yoshio Okubo
大久保 祥雄
Hiroshi Oishi
大石 博司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP58212886A priority Critical patent/JPS60105382A/en
Publication of JPS60105382A publication Critical patent/JPS60105382A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/148Charge coupled imagers
    • H01L27/14887Blooming suppression

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To minimize the area needed for separation between light sensitive parts by shutting off the part for accumulating the signal charge of the adjacent light sensitive part with the groove formed at the semiconductor substrate surface and by forming the diffusion area having the conductive type opposite to the semiconductor substrate at the groove bottom part. CONSTITUTION:A groove 14 is formed at P type semiconductor substrate 13. A drain 15 for excess carrier absorption consisting of the N type diffusion layer with high concentration is formed at the bottom part of a groove 14. A surface layer 16 of the flush channel consisting of the impurity diffusion layer is formed at the surface of a substrate 13 between the light sensitive part and a groove 14. A gate electrode 17 is formed on a gate oxidation film 18. When the positive bias is impressed for a substrate 13 to a drain 15, and even when the excess charge occurs at a substrate 13, the charge is absorbed and exhausted to a drain 15 and the blooming can be prevented. Consequently, the flow-in of the excess charge between light sensitive parts can be prevented.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はビデオカメラ等の撮像装置に用いられる固体撮
像素子に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a solid-state imaging device used in imaging devices such as video cameras.

従来例の構成とその問題点 第1図は固体撮像素子の構成例を示す。これは電荷結合
型の2次元固体撮像素子で、詳しくは、フレームトラン
スファ型固体撮像素子と称されるものである。すなわち
撮像部ムの部分の光感頬部1で蓄積された信号電荷はテ
レビジョン走査方式でいう垂直消去時間の期間内に、蓄
積部Bの対応する蓄積要素1′に転送される。この後、
1水平走査毎に、1段ずつ垂直転送され、水平走査用c
anシフトレジスタ2に電荷転送される。この転送は水
平消去期間内におこなわれる。水平走査をおこなう水平
シフトレジスタ2の信号電荷は出力部3で信号出力に変
換される。
Conventional Structure and Its Problems FIG. 1 shows an example of the structure of a solid-state image sensor. This is a charge-coupled two-dimensional solid-state imaging device, and more specifically, it is called a frame transfer solid-state imaging device. That is, the signal charge accumulated in the photosensitive cheek section 1 of the imaging section B is transferred to the corresponding storage element 1' of the storage section B within the vertical erasing time period in the television scanning system. After this,
For each horizontal scan, one stage is vertically transferred, and the horizontal scanning c
Charge is transferred to the an shift register 2. This transfer occurs within the horizontal erase period. The signal charge of the horizontal shift register 2 that performs horizontal scanning is converted into a signal output by the output section 3.

固体撮像素子のM20代表的な構成例を第2図に示す。FIG. 2 shows a typical configuration example of an M20 solid-state image sensor.

インターライン転送方式と呼ばれる方式であって、絵素
に相当する光感頬部1の信号電荷は垂直消去時間内に垂
直転送線4に転送される。
This method is called an interline transfer method, and the signal charge of the photosensitive cheek portion 1 corresponding to a picture element is transferred to the vertical transfer line 4 within the vertical erasing time.

垂直転送線4は電荷転送線で構成される外に単なる導条
である場合もある。その場合は光感知部1て蓄積される
信号電荷が垂直転送線4に移るときに、その間にスイッ
チが設けられ、垂直シフトレジスタで、このスイッチが
開閉されることになる。
The vertical transfer line 4 may be a charge transfer line or may be a simple guide. In that case, when the signal charges accumulated in the photodetector 1 are transferred to the vertical transfer line 4, a switch is provided between them, and this switch is opened and closed by the vertical shift register.

また、垂直転送線4上の電荷を水平電荷転送線に注入す
るだめの変換部6が設けられる。
Further, a conversion unit 6 is provided for injecting the charges on the vertical transfer line 4 into the horizontal charge transfer line.

ところで、光電変換がおこなわれる光感頬部1の電気的
絶縁は第3図に示すような、いわゆるチャンネルストッ
プ領域によってなされてきた。すなわち、第1図におけ
る撮像部チャンネルストップ領域6は第3図に示すよう
に、基板7上のエピタキシャル層8の表面に形成された
比較的に厚い酸化膜9(〜1ミクロン)の下に設けられ
た層8と同一導電型の不純物層1oが1017〜101
8(”F7+ ’程度の濃度で1〜3ミクロン程度の厚
さで形成されることが多い。なお、同図で11はゲート
酸化膜、12は電荷転送用ゲート電極である。これが一
般にチャンネルストップと称される電位障壁部を形成す
る。しかしながら、この構造では後述の一般の動作状態
において絶縁の目的は達せられない。
By the way, electrical insulation of the photosensitive cheek part 1 where photoelectric conversion is performed has been achieved by a so-called channel stop region as shown in FIG. That is, the imaging section channel stop region 6 in FIG. 1 is provided under a relatively thick oxide film 9 (~1 micron) formed on the surface of the epitaxial layer 8 on the substrate 7, as shown in FIG. The impurity layer 1o of the same conductivity type as the layer 8 is 1017 to 101.
It is often formed with a concentration of about 8 ("F7+") and a thickness of about 1 to 3 microns. In the same figure, 11 is a gate oxide film, and 12 is a gate electrode for charge transfer. This is generally a channel stop. However, with this structure, the purpose of insulation cannot be achieved under general operating conditions, which will be described later.

すなわち、必要な解像度を実現するためには、絵素周期
は1o数ミクロンにする必要があるが、このチャンネル
ストップ領域6の幅が大きいために光感頬部10面積比
率を大きく維持するのが困難である。すなわち、第一に
チャンネルストップ領域60幅はその厚い酸化膜を小さ
い幅で形成することが困難なこと、第2に隣接した光感
頬部1間に高濃度拡散領域7を配設するだけでは不十分
なことが判明してきた。すなわち、光入力が過大のとき
は、高濃度拡散領域子による電位障壁が有効でなくなり
、いわゆるプルーミング現象が発生する。このため、そ
のような絵素部のポテンシャル井戸を溢れる電荷を積極
的に排出する機構が必要である。
That is, in order to achieve the necessary resolution, the picture element period needs to be a few microns, but since the width of this channel stop region 6 is large, it is necessary to maintain a large area ratio of the photosensitive cheek region 10. Have difficulty. That is, firstly, the width of the channel stop region 60 is such that it is difficult to form a thick oxide film with a small width, and secondly, it is difficult to form a high concentration diffusion region 7 between adjacent photosensitive cheeks 1. It has become clear that this is insufficient. That is, when the optical input is excessive, the potential barrier provided by the highly concentrated diffusion region becomes ineffective, and a so-called pluming phenomenon occurs. Therefore, a mechanism is required to actively discharge the charge overflowing the potential well of such a picture element portion.

発明の目的 本発明は上記欠点に鑑みなされたもので、光感細部間の
電気絶縁領域の幅をせまくするとともに、過剰光入力電
荷および洩れ電荷の吸収、排出ができる固体撮像素子を
提供するものである。
OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and provides a solid-state imaging device that can narrow the width of the electrically insulating region between photosensitive parts and absorb and discharge excess light input charge and leakage charge. It is.

発明の構成 本発明の固体撮像素子は隣接した光感頬部の信号電荷の
蓄積部が半導体基板表面に形成された溝によって遮断さ
れるとともに、前記溝底部に半導体基板と反対の導電型
を有する拡散領域が形成されて構成されている。
Structure of the Invention In the solid-state imaging device of the present invention, the signal charge accumulation portion of the adjacent photosensitive cheek is blocked by a groove formed on the surface of the semiconductor substrate, and the bottom of the groove has a conductivity type opposite to that of the semiconductor substrate. A diffusion region is formed and configured.

実施例の説明 第4図は本発明の第1の実施例を示す断面図である。ま
ず、半導体基板13はP型(100)方位、比抵抗値を
10〜2oΩ−鋸の単結晶シリコンからなり、溝14の
深さは3〜8ミクロンである。過剰キャリア吸収用ドレ
イン15は高濃度のN型拡散層で、基板8に対して3〜
1oボルトの正6電圧が印加される。表面層16は第1
図に示したフレームトランスファ方式の固体撮像素子で
は紙面に垂直な方向に電荷転送をおこなうために、溝1
4の間の光感頬部となる半導体基板13の表面に5×1
015〜2 X 1016cm 3の不純物濃度で、厚
さは1〜2ミクロンの不純物拡散層からなる埋め込みチ
ャンネルでおる。この場合は電荷転送のためのゲート電
極17がsoo裏〜120oi程度の厚さの二酸化けい
素からなるゲート酸化膜18の上に低抵抗多結晶シリコ
ンで形成される。
DESCRIPTION OF EMBODIMENTS FIG. 4 is a sectional view showing a first embodiment of the present invention. First, the semiconductor substrate 13 is made of single crystal silicon having a P type (100) orientation and a specific resistance value of 10 to 2 ohms, and the depth of the groove 14 is 3 to 8 microns. The drain 15 for absorbing excess carriers is a highly concentrated N-type diffusion layer, and is
A positive 6 voltage of 1o volts is applied. The surface layer 16 is the first
In the frame transfer type solid-state image sensor shown in the figure, in order to transfer charge in the direction perpendicular to the page, groove 1 is
5×1 on the surface of the semiconductor substrate 13 which becomes the photosensitive cheek area between 4
The buried channel consists of an impurity diffusion layer with a thickness of 1-2 microns and an impurity concentration of 0.015-2.times.10.sup.16 cm.sup.3. In this case, a gate electrode 17 for charge transfer is formed of low-resistance polycrystalline silicon on a gate oxide film 18 made of silicon dioxide and having a thickness of about 120 oi.

固体撮像素子では、光感頬部1の最表面層はゲート電極
17が除去される方が光の吸収による損失を回避するた
めに望ましく、かつ、表面電位の安定化、表面保護のた
めに、密度が高く、表面不純物が透過し難い窒化けい素
膜19を500〜1500人の厚さで付設すると良い。
In the solid-state imaging device, it is preferable to remove the gate electrode 17 from the outermost layer of the photosensitive cheek part 1 in order to avoid loss due to absorption of light, and to stabilize the surface potential and protect the surface. It is preferable to provide a silicon nitride film 19 with a thickness of 500 to 1,500 layers, which has a high density and is difficult for surface impurities to pass through.

可視域の中で、とくに青〜緑光領域での透過特性を最大
となるように、ゲート酸化膜18、表面層16の膜厚関
係が設定される。ゲート酸化膜18500人、窒化けい
素膜19を1000人とするときはi’+’領域の反射
率は極小値となる。これにより、固体撮像素子の感度向
上に重要な分光感度上のバランスがはかれる。
The film thickness relationship between the gate oxide film 18 and the surface layer 16 is set so as to maximize the transmission characteristics in the visible light range, especially in the blue to green light range. When the thickness of the gate oxide film is 18,500 and the thickness of the silicon nitride film 19 is 1,000, the reflectance in the i'+' region becomes a minimum value. This achieves a balance in terms of spectral sensitivity, which is important for improving the sensitivity of solid-state imaging devices.

次に、第4図の実施例の動作を説明する。N型ドレイン
16にP型基板13に対して正バイアスを印加する。こ
のため、基板13で過剰電荷が発生してもそれはドレイ
ン16に吸収・排出されブルーミングが防止される。本
実施例の如く、ドレイン15を基板13よシ深い部分に
形成しておくと、基板13の深い部分で発生した過剰電
荷が効果的に吸収される。したがって、光感細部間での
過剰電荷の流れ込みが防止される。ここで、従来のよう
にドレインを光感頬部と同一平面に形成した場合には基
板の深い部分で発生した過剰キャリヤが基板表面方向に
移動し、ドレインに吸収されるまでに隣接する光感頬部
へ過剰電荷が流れ込みブルーミングを充分に防止できな
かった。このように本発明では過剰電荷の流入防止を充
分図ることができる。
Next, the operation of the embodiment shown in FIG. 4 will be explained. A positive bias is applied to the N-type drain 16 with respect to the P-type substrate 13 . Therefore, even if excess charge is generated in the substrate 13, it is absorbed and discharged by the drain 16, thereby preventing blooming. If the drain 15 is formed deeper than the substrate 13 as in this embodiment, excess charges generated in the deeper portion of the substrate 13 can be effectively absorbed. Therefore, excessive charges are prevented from flowing between the photosensitive areas. Here, when the drain is formed on the same plane as the photosensitive cheek as in the past, excess carriers generated in the deep part of the substrate move toward the substrate surface, and before being absorbed by the drain, the adjacent photosensitive Blooming could not be sufficiently prevented due to excessive charge flowing into the cheek area. In this way, the present invention can sufficiently prevent the inflow of excess charges.

第6図は本発明の第二の実施例を示す断面図である。こ
の例はN型基板2oと、このN型基板20上に形成され
たP型エピタキシャル層21とによシ基板が形成されて
いる。基板15は比抵抗60〜2oΩm程度のものが使
用される。そしてエピタキシャル層21と基板20の間
に逆バイアスが印加される。その場合には隣接の光感頬
部1との間には溝14があるので、励起された信号電荷
が隣接の光感頬部1に洩れることはない。過剰の励起が
おこなわれたときは、隣接の光感頬部1に溢れる前に基
板20側に盛れ、逆方向電流となるだけである。したが
って、隣接絵素間の洩れ信号電荷はほぼ完全に阻止され
る。
FIG. 6 is a sectional view showing a second embodiment of the present invention. In this example, an N-type substrate 2o and a P-type epitaxial layer 21 formed on this N-type substrate 20 form a composite substrate. The substrate 15 used has a specific resistance of about 60 to 2 ohm. A reverse bias is then applied between the epitaxial layer 21 and the substrate 20. In this case, since there is a groove 14 between the adjacent photosensitive cheeks 1, the excited signal charges will not leak to the adjacent photosensitive cheeks 1. When excessive excitation occurs, the excitation simply builds up on the substrate 20 side before overflowing to the adjacent photosensitive cheek 1, resulting in a reverse current. Therefore, leakage signal charges between adjacent picture elements are almost completely blocked.

ところで、基板20がエピタキシャル層21と同じ導電
型のとき、すなわち、P型でエピタキシャル層21より
10倍以上高い濃度の場合である。
By the way, this is the case when the substrate 20 is of the same conductivity type as the epitaxial layer 21, that is, the P type and the concentration is ten times or more higher than that of the epitaxial layer 21.

この場合には基板2o内の担体に対する再結合速度が高
くなる熱処理工程を施すことによって、基板2oで発生
する担体の拡散を防止し、洩れ信号電荷を抑制すること
ができる。
In this case, by performing a heat treatment step that increases the rate of recombination of carriers within the substrate 2o, it is possible to prevent diffusion of carriers generated in the substrate 2o and suppress leakage signal charges.

第6図は本発明の固体撮像素子の製作工程を示す図であ
る。まず、エピタキシャル層21表面に二酸化けい素膜
22、窒化けい素膜23を形成し、分離領域となる部分
の二酸化けい素膜22、窒化けい素膜23を除去する。
FIG. 6 is a diagram showing the manufacturing process of the solid-state image sensor of the present invention. First, a silicon dioxide film 22 and a silicon nitride film 23 are formed on the surface of the epitaxial layer 21, and portions of the silicon dioxide film 22 and silicon nitride film 23 that will become isolation regions are removed.

この後、窒化けい素膜23をマスクとしてエピタキシャ
ル層21表面をエツチングして、溝24を形成する(第
6図a)。
Thereafter, the surface of the epitaxial layer 21 is etched using the silicon nitride film 23 as a mask to form a groove 24 (FIG. 6a).

次いで、エピタキシャル層21表面を1000人程度の
酸化をおこない酸化膜25を形成する。次いで、溝24
底部に対して、リンまたは砒素のイオン注入を行ない過
剰キャリヤ吸収用ドレイン26を形成する(第6図b)
。しかるのち、多結晶シリコン27の堆積をおこない、
溝部24を埋める。溝部24上の凹部にフォトレジスト
28を流し込む(第6図C)。この後、プラズマエツチ
ングにより堆積した多結晶シリコン27の除去をおこな
う。そして、溝部24の多結晶シリコン27が光感頬部
とほぼ同じ平面となる点で食刻を停止する。そして、溝
部24上に酸化膜29を形成する(第6図d)。その後
は通常の電荷転送素子の形成と、はぼ同じ工程によって
製作する。
Next, the surface of the epitaxial layer 21 is oxidized by about 1,000 degrees to form an oxide film 25. Next, the groove 24
Phosphorus or arsenic ions are implanted into the bottom to form a drain 26 for absorbing excess carriers (FIG. 6b).
. After that, polycrystalline silicon 27 is deposited,
Fill the groove 24. A photoresist 28 is poured into the recess above the groove 24 (FIG. 6C). Thereafter, the deposited polycrystalline silicon 27 is removed by plasma etching. Then, the etching is stopped at the point where the polycrystalline silicon 27 of the groove 24 is approximately on the same plane as the photosensitive cheek. Then, an oxide film 29 is formed on the groove portion 24 (FIG. 6d). After that, it is manufactured using almost the same steps as for forming a normal charge transfer element.

発明の効果 以上詳述した本発明の固体撮像素子は光感細部間の分離
に要する面積が少なく、高密度の光感頬部を有する高解
像度の固体撮像素子が得られる。
Effects of the Invention The solid-state imaging device of the present invention described in detail above requires less area for separating light-sensitive parts, and a high-resolution solid-state imaging device having high-density light-sensitive cheek parts can be obtained.

同時に固体撮像素子で特に問題となる大きな光入力時の
洩れ信号電荷による動作障害を完全に除去できる。
At the same time, it is possible to completely eliminate operational failures caused by leakage signal charges when a large amount of light is input, which is a particular problem with solid-state image sensors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はフレームトランスファ方式のCOD固体撮像素
子の2次元配置図、第2図はインターライン方式のca
n固体撮像素子の2次元配置図、第3図は従来の光感細
部間の分離部分を示す要部断面図、第4図、第6図は本
発明の実施例に係る固体撮像素子の断面図、第6図a 
”−dは本発明に係る固体撮像素子の製造工程断面図で
ある。 14・・・・・・溝部、15・・・・・・過剰キャリヤ
吸収用ドレイン。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名裁 
1 図 鶴2図 /、5 /、5 S図
Figure 1 is a two-dimensional layout diagram of a frame transfer type COD solid-state image sensor, and Figure 2 is an interline type ca
n A two-dimensional layout diagram of a solid-state image sensor, FIG. 3 is a cross-sectional view of main parts showing separation between conventional light-sensitive parts, and FIGS. 4 and 6 are cross-sections of a solid-state image sensor according to an embodiment of the present invention. Figure 6a
"-d is a sectional view of the manufacturing process of the solid-state image sensor according to the present invention. 14...Groove portion, 15...Drain for absorbing excess carriers. Name of agent: Patent attorney Satoshi Nakao Man and 1 other judge
1 Figure Crane 2 Figure /, 5 /, 5 S Figure

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板の表面に絶縁層を介して、たがいに平
行に配列された複数個のゲート電極と、前記ゲート電極
に直交して前記半導体基板の表面に配設された複数個の
溝部と、前記溝部の底部直下に設けられた前記半導体基
板の導電型と反対の導電型の領域をそなえ隣接した前記
溝部間に光感頬部が形成されていることを特徴とする固
体撮像素子。
(1) A plurality of gate electrodes arranged in parallel to each other on the surface of a semiconductor substrate with an insulating layer interposed therebetween, and a plurality of grooves arranged on the surface of the semiconductor substrate perpendicular to the gate electrodes. A solid-state image pickup device, comprising: a region having a conductivity type opposite to that of the semiconductor substrate provided immediately below the bottom of the groove, and a photosensitive cheek portion being formed between adjacent grooves.
(2)半導体基板上には前記基板と反対の導電型のエピ
タキシャル層を有し、前記エピタキシャル層表面から前
記半導法基板に及ぶ溝部が形成されていることを特徴と
する特許請求の範囲第1項記載の固体撮像素子。
(2) An epitaxial layer having a conductivity type opposite to that of the substrate is provided on the semiconductor substrate, and a groove extending from the surface of the epitaxial layer to the semiconductor substrate is formed. The solid-state imaging device according to item 1.
JP58212886A 1983-11-11 1983-11-11 Solid-state pickup element Pending JPS60105382A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58212886A JPS60105382A (en) 1983-11-11 1983-11-11 Solid-state pickup element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58212886A JPS60105382A (en) 1983-11-11 1983-11-11 Solid-state pickup element

Publications (1)

Publication Number Publication Date
JPS60105382A true JPS60105382A (en) 1985-06-10

Family

ID=16629884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58212886A Pending JPS60105382A (en) 1983-11-11 1983-11-11 Solid-state pickup element

Country Status (1)

Country Link
JP (1) JPS60105382A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005294701A (en) * 2004-04-02 2005-10-20 Sharp Corp Solid-state image sensor and manufacturing method thereof
JP2006196536A (en) * 2005-01-11 2006-07-27 Sony Corp Imaging element

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5325269B1 (en) * 1969-04-03 1978-07-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5325269B1 (en) * 1969-04-03 1978-07-26

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005294701A (en) * 2004-04-02 2005-10-20 Sharp Corp Solid-state image sensor and manufacturing method thereof
JP4537750B2 (en) * 2004-04-02 2010-09-08 シャープ株式会社 Solid-state imaging device and manufacturing method thereof
JP2006196536A (en) * 2005-01-11 2006-07-27 Sony Corp Imaging element

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