JPH0697669B2 - Charge coupled device - Google Patents
Charge coupled deviceInfo
- Publication number
- JPH0697669B2 JPH0697669B2 JP59190301A JP19030184A JPH0697669B2 JP H0697669 B2 JPH0697669 B2 JP H0697669B2 JP 59190301 A JP59190301 A JP 59190301A JP 19030184 A JP19030184 A JP 19030184A JP H0697669 B2 JPH0697669 B2 JP H0697669B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- potential
- electrodes
- semiconductor substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000005036 potential barrier Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000004044 response Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims 1
- 238000011144 upstream manufacturing Methods 0.000 claims 1
- 238000001444 catalytic combustion detection Methods 0.000 description 23
- 238000010586 diagram Methods 0.000 description 6
- 239000000969 carrier Substances 0.000 description 5
- 230000015654 memory Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42396—Gate electrodes for field effect devices for charge coupled devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は電荷結合素子（以下CCDと称す）に関する。The present invention relates to a charge-coupled device (hereinafter referred to as CCD).
（ロ）従来の技術 この種CCDは遅延素子、アナログメモリの他に例えば特
公昭57-32548号公報に示されている如く固体撮像装置と
しての利用が注目されており、テレビカメラの小型化に
寄与するものである。(B) Conventional Technology In addition to delay elements and analog memories, CCDs of this type are attracting attention for use as solid-state image pickup devices as disclosed in, for example, Japanese Patent Publication No. 57-32548. It contributes.
第２図（イ），（ロ）にこの種従来CCDの平面図、及び
そのA-A線断面図を示す。これ等の図に於いて、（１）
はシリコン基板、（２）はシリコン酸化膜、（31）（3
2）（31）（32）…は多結晶シリコンからなる第１電
極、（41）（42）（41）（42）…は同じく多結晶シリコ
ンからなる第２電極である。これ等第１電極と第２電極
とが交互に配置された電極列は、連続した多数の電極対
（41）（31），（42）（32），（41）（31），…を構成
し、奇数番目の電極対（41）（31），（41）（31），…
にはクロックパルスΦ1が供給され、偶数番目の電極対
（42）（32），（42）（32），…にクロックパルスΦ2
が供給されている。これ等電極（41）（31）（42）（3
2）…下のＰ型のシリコン基板（１）表面部には、燐あ
るいは砒素を導入した埋込みチャンネル層（141）（13
1）（142）（132）…が設けられており、第２電極（4
1）（42）…下の埋込みチャンネル層（141）（142）…
のＮ型化された領域は、逆にＰ型化させるような硼素を
導入する事に依って第１電極（31）（32）…下のＮ型不
純物領域の埋込みチャンネル層（131）（132）…よりＮ
型化の弱められたN-型不純物領域となっている。尚、同
図（イ）の平面図に於ける領域（ａ）（ａ）…は並列配
置された同図（ロ）の断面図に示す如きチャンネル領域
であり、これ等領域（ａ）（ａ）…間はP+型不純物から
なるチャンネルストッパ領域（ｂ）（ｂ）…が設けられ
ている。2 (a) and 2 (b) show a plan view of this type of conventional CCD and a cross-sectional view taken along the line AA. In these figures, (1)
Is a silicon substrate, (2) is a silicon oxide film, (31) (3
2), (31), (32), ... Are first electrodes made of polycrystalline silicon, and (41), (42), (41), (42), ... Are second electrodes made of polycrystalline silicon. These electrode rows in which the first electrodes and the second electrodes are alternately arranged constitute a large number of continuous electrode pairs (41) (31), (42) (32), (41) (31), .... Then, odd-numbered electrode pairs (41) (31), (41) (31), ...
Clock pulse [Phi 1 is supplied to the even-numbered electrode pair (42) (32), (42) (32), ... the clock pulse [Phi 2
Is being supplied. These electrodes (41) (31) (42) (3
2) ... A buried channel layer (141) (13) into which phosphorus or arsenic is introduced on the surface of the lower P-type silicon substrate (1).
1) (142) (132) are provided, and the second electrode (4
1) (42) ... Lower buried channel layers (141) (142) ...
On the contrary, the N-type region of the first electrode (31) (32) is buried in the N-type impurity region under the first electrodes (31) (32) by introducing boron so as to make it P-type. )… N
It is an N - type impurity region with weakened type. Areas (a), (a), ... In the plan view of FIG. 2A are channel areas as shown in the cross-sectional view of FIG. 2B arranged in parallel, and these areas (a), (a) ) ... between the channel stopper region (b) (b) ... it is provided consisting of P + -type impurity.
斯様な従来CCDに於いては第３図に示す如き２相のクロ
ックパルスΦ1，Φ2にて駆動され第１電極（31）（32）
（31）（32）…とこれと電極対をなす第２電極（41）
（42）（41）（42）…とには同一のクロックパルスΦ1
又はΦ2が印加される事となるが、上述の如くチャンネ
ル層の不純物濃度が異なる為に第１電極（31）（32）
（31）（32）…下のポテンシャルが第２電極（41）（4
2）（41）（42）…下のそれよりも深く形成される。即
ち、第３図の時刻t1（Φ1＝H,Φ2＝Ｌ）でのポテンシャ
ル形態は第４図t1で示す如く、偶数番目の電極対の第２
電極（42）（42）…下のポテンシャルがポテンシャル障
壁を形成するべく最も浅くなり、奇数番目の電極対の第
１電極（31）（31）…下のポテンシャルがポテンシャル
井戸を形成するべく最も深くなる。又時刻t2（Φ1＝L,
Φ2＝Ｈ）でのポテンシャル形態は第４図t2で示す如
く、奇数番目の電極対の第２電極（41）（41）…下のポ
テンシャルがポテンシャル障壁を形成すると共に偶数番
目の電極対の第１電極（32）（32）…下のポテンシャル
がポテンシャル井戸を形成する事となる。この様に同図
のt1の状態とt2の状態とがくり返されるとキャリアであ
る電子がポテンシャル井戸の移動に従って同図の矢印で
示す如く左から右へと転送されるのである。In such a conventional CCD, the first electrodes (31) (32) are driven by two-phase clock pulses Φ 1 , Φ 2 as shown in FIG.
(31) (32) ... and the second electrode (41) forming an electrode pair with this
(42) (41) (42) ... Same clock pulse Φ 1
Or Φ 2 will be applied, but since the impurity concentration of the channel layer is different as described above, the first electrodes (31) (32)
(31) (32) ... The lower potential is the second electrode (41) (4
2) (41) (42) ... It is formed deeper than that below. That is, the potential form at time t 1 (Φ 1 = H, Φ 2 = L) in FIG. 3 is as shown in FIG.
The potentials below the electrodes (42) (42) ... become the shallowest to form a potential barrier, and the potentials below the first electrodes (31) (31) ... of the odd-numbered electrode pairs are the deepest to form a potential well. Become. Also at time t 2 (Φ 1 = L,
Potential form at [Phi 2 = H) is as shown in FIG. 4 t 2, the second electrode (41 odd-numbered electrode pair) (41) ... even-numbered electrode pair along with the potential under to form a potential barrier The lower potentials of the first electrodes (32) (32) of this form a potential well. When the state of t 1 and the state of t 2 in this figure are repeated in this way, the electrons as carriers are transferred from the left to the right as shown by the arrow in the figure as the potential well moves.
斯様な従来のCCDを多数ビットを必要とする固体撮像素
子あるいはメモリとして用いる場合、多数ビット即ち多
数チャンネルとなる為に、大面積化を招き、多結晶シリ
コンからなる各電極（31）（32）（41）（42）…の長さ
が1cm近くなり、又この電極数も増加するので、１本の
電極巾も数μｍと細くなり、斯る電極（31）（32）（4
1）（42）…１本１本の電気抵抗が無視できない程大き
な値となっているのが現状である。When such a conventional CCD is used as a solid-state imaging device or a memory that requires a large number of bits, it has a large number of bits, that is, a large number of channels, which leads to an increase in area and each electrode made of polycrystalline silicon (31) ) (41) (42) ... The length is close to 1 cm, and the number of electrodes also increases, so the width of one electrode is also reduced to a few μm, and such electrodes (31) (32) (4
1) (42) ... Currently, the electrical resistance of each wire is so large that it cannot be ignored.
一方、上述の如き２相駆動方式のCCDに於いては、第２
電極（41）（42）…はキャリアである電子の逆流を防止
する目的を達成する為のポテンシャル障壁を形成できれ
ばよいので、電極巾は極力細く設定してCCD全体の小型
集積化を図るのが一般的であるが、この場合第２電極
（41）（42）…の電気抵抗値が第１電極（31）（32）…
のそれよりもさらに大きくなってしまう欠点が生じる。On the other hand, in the two-phase drive type CCD as described above, the second
It is sufficient for the electrodes (41) (42) ... to form a potential barrier for achieving the purpose of preventing backflow of electrons that are carriers. Generally, in this case, the electric resistance value of the second electrodes (41) (42) ... Is such that the first electrodes (31) (32) ...
There is a drawback that it becomes even larger than that.
即ち、この場合第２電極（41）（42）…の電気抵抗値が
第１電極（31）（32）…のそれより大きいので、第５図
に示す如くクロックパルスΦ1及びΦ2に依る第２電極
（41）（42）…位置への印加電圧Φ12，及びΦ22の立上
り又は立下り時の時定数がクロックパルスΦ1及びΦ2に
依る第１電極（31）（32）…位置への印加電圧Φ11及び
Φ21のそれよりも長くなる。従って第２電極（41）（4
2）…下に形成されるポテンシャル障壁の応答時間が第
１電極（31）（32）…下に形成されるポテンシャル井戸
の応答時間より遅くなるので、ポテンシャル井戸の移動
が完了してからポテンシャル障壁の移動が完了するまで
の間の遅延差時間にキャリアである電子が逆流してしま
う不都合があった。この様子は第６図に示しており，同
図に依れば第５図の時刻t1でのポテンシャル形態から時
刻t3でのポテンシャル形態に移る途中の上記遅延差時間
に於ける時刻t3での電子の逆流現象が理解できる。この
様にクロックパルスの変形に依って、電子の逆流転送が
生じるとただ単に転送効率の低下を来たすだけでなくこ
の逆流電子がノイズとなり、CCD固体撮像装置に於いて
は再生画像のコントラストの劣化を招いたり、CCDメモ
リに於いては記憶内容の破壊を引き起こす原因となって
いた。That is, in this case, since the electric resistance values of the second electrodes (41) (42) ... Are larger than those of the first electrodes (31) (32) ..., they depend on the clock pulses Φ 1 and Φ 2 as shown in FIG. Second electrodes (41) (42) ... First electrodes (31) (32) whose time constants at the time of rising or falling of the applied voltage Φ 12 and Φ 22 depend on the clock pulses Φ 1 and Φ 2 . The voltage applied to the position is longer than that of Φ 11 and Φ 21 . Therefore, the second electrode (41) (4
2) ... Since the response time of the potential barrier formed below is slower than the response time of the potential well formed below the first electrodes (31) (32) ..., the potential barrier is completed after the movement of the potential well is completed. There is an inconvenience that the electrons, which are carriers, flow back during the delay difference time until the movement of is completed. This state is shown in FIG. 6, and according to the same figure, the time t 3 in the delay difference time on the way from the potential form at time t 1 in FIG. 5 to the potential form at time t 3 is shown. Understand the backflow phenomenon of electrons. In this way, if backflow transfer of electrons occurs due to deformation of the clock pulse, not only does transfer efficiency drop, but also this backflow electron becomes noise, and in the CCD solid-state imaging device, the contrast of the reproduced image deteriorates. It has been a cause of causing the destruction of the memory contents in the CCD memory.
（ハ）発明が解決しようとする問題点 本発明は上述の点に鑑みてなされたものであり、キャリ
アの逆流現象を解消したCCDを提供するものである。(C) Problems to be Solved by the Invention The present invention has been made in view of the above points, and provides a CCD in which the carrier backflow phenomenon is eliminated.
（ニ）問題点を解決するための手段 本発明のCCDは半導体基板上に絶縁膜を介して電極列を
配置した電荷結合素子に於いて、該電極列は共通の電圧
源からの印加電圧に依って半導体基板中にポテンシャル
井戸を形成する為の第１電極とこれと隣接してポテンシ
ャル障壁を形成する為の第２電極とからなる２枚１組の
電極対からなり、上記第１電極の電気抵抗を第２電極の
電気抵抗より大ならしめたものである。(D) Means for Solving the Problems The CCD of the present invention is a charge-coupled device in which an electrode array is arranged on a semiconductor substrate with an insulating film interposed between the electrode array and a voltage applied from a common voltage source. Therefore, it is composed of a pair of two electrodes consisting of a first electrode for forming a potential well in a semiconductor substrate and a second electrode for forming a potential barrier adjacent to the first electrode. The electrical resistance is made larger than the electrical resistance of the second electrode.
（ホ）作用 本発明に依ればポテンシャル井戸を形成する為の第１電
極の電気抵抗をポテンシャル井戸を形成する為の第２電
極のそれよりも大ならしめる事に依り、ポテンシャル障
壁形成の為の応答時間をポテンシャル井戸形成の為の応
答時間より短くしてこのポテンシャル障壁にてキャリア
の逆流現象を解消する事ができる。(E) Action According to the present invention, the electric resistance of the first electrode for forming the potential well is set to be larger than that of the second electrode for forming the potential well, thereby forming the potential barrier. It is possible to eliminate the carrier backflow phenomenon by this potential barrier by making the response time of (1) shorter than the response time for forming the potential well.
（ヘ）実施例 第１図（イ）（ロ）に本発明のCCDの一実施例の平面
図、及びそのA-A線断面図を示す。同図に於いて、第２
図（イ）（ロ）の従来CCDと同一部分には第１図（イ）
（ロ）と同一符号を付している。本発明実施例CCDが従
来CCDと異なるところは、第２電極（41′）（42′）…
の膜厚を第１電極（31）（32）…のそれより大きくする
事に依って、第１電極（31）（32）…の電気抵抗を第２
電極（41′）（42′）…のそれより大ならしめた点にあ
る。(F) Embodiment FIG. 1 (a) (b) shows a plan view of an embodiment of the CCD of the present invention and a sectional view taken along the line AA. In the figure, the second
Fig. 1 (a) is the same part as the conventional CCD in Fig. (A) and (b).
The same reference numerals as in (b) are attached. The present embodiment CCD is different from the conventional CCD in that the second electrodes (41 ') (42') ...
By making the film thickness of the first electrodes (31) (32) ... to be larger than that of the first electrodes (31) (32).
The electrode (41 ') (42') ... is larger than that.
斯る実施例CCDは、ポテンシャル障壁を形成する為の第
２電極（41′）（42′）…の電極巾をポテンシャル井戸
を形成する為の第１電極（31）（32）…の電極巾の約2/
3に狭めてCCD全体の集積化を図ったものに於いて、電極
巾の短縮に依る電気抵抗の増大分を電極の膜厚を約２倍
にまで厚くする事に依って、ポテンシャル井戸を形成す
る為に電極巾が大きく形成されている第１電極（31）
（32）…の断面積を上記第２電極（41′）（42′）のそ
れより小さく設定しているのである。In this embodiment CCD, the electrode width of the second electrodes (41 ') (42') for forming the potential barrier is set to the electrode width of the first electrodes (31) (32) for forming the potential well. About 2 /
Forming a potential well by narrowing to 3 and integrating the entire CCD to increase the electric resistance increase due to the shortening of the electrode width to about twice the film thickness of the electrode. Electrode (31) with a large electrode width for
The cross-sectional area of (32) ... Is set smaller than that of the second electrodes (41 '), (42').
従って、同一の多結晶シリコン材料（比抵抗約10-3Ωc
m）からなる第１及び第２電極（31）（32），（41′）
（42′）であっても第１電極（31）（32）の電気抵抗が
第２電極（41′）（42′）のそれよりも大きくなるの
で、電極対（31）（41′）に共通の電圧源である第３図
図示のクロックパルスΦ1が、又電極対（32）（42′）
に共通の電圧源である第３図図示のクロックパルスΦ2
が印加された場合、各電極（41′）（31）（42′）（3
2）には第７図に示す如き遅延現象を有する電圧
Φ′12，Φ′11，Φ′22，Φ′21が印加される事とな
る。Therefore, the same polycrystalline silicon material (specific resistance of about 10 -3 Ωc
m) first and second electrodes (31) (32), (41 ')
Even in the case of (42 '), the electric resistance of the first electrodes (31) (32) is larger than that of the second electrodes (41') (42 '), so that the electrode pair (31) (41') The clock pulse Φ 1 shown in FIG. 3, which is a common voltage source, is also supplied to the electrode pair (32) (42 ').
The clock pulse Φ 2 shown in FIG.
Is applied, each electrode (41 ') (31) (42') (3
Voltages Φ ′ 12 , Φ ′ 11 , Φ ′ 22 and Φ ′ 21 having a delay phenomenon as shown in FIG. 7 are applied to 2).
第８図に第７図に於ける時刻t1,t2,t3,t4時の印加電圧
Φ′12，Φ′11，Φ′22，Φ′21に応答するポテンシャ
ル形態の状態変化を示す。同図に依れば、印加電圧Φ′
12，Φ′22，の立上り時又は立下り時（時刻t1,t2）の
時定数、即ち遅延時間が印加電圧Φ′11，Φ′21のそれ
よりも小さいので、時刻t1から時刻t4に至るポテンシャ
ル井戸の移動形成に常に先んじてポテンシャル障壁の移
動形成が行なわれる事がわかる。従ってキャリアである
電子は上述のポテンシャル障壁に依って常に転送方向が
規制される事となり、この電子の逆流転送はない。FIG. 8 shows the state changes of the potential form in response to the applied voltages Φ ′ 12 , Φ ′ 11 , Φ ′ 22 , and Φ ′ 21 at the times t 1 , t 2 , t 3 , t 4 in FIG. Show. According to the figure, the applied voltage Φ ′
12, since [Phi '22, the time constant at the rise time or fall (time t 1, t 2), i.e. the delay time applied voltage Φ' 11, Φ '21 of less than that, the time from time t 1 It can be seen that the migration formation of the potential barrier is always performed prior to the migration formation of the potential well up to t 4 . Therefore, the electrons as carriers are always regulated in the transfer direction by the above potential barrier, and there is no backflow transfer of the electrons.
（ト）発明の効果 本発明のCCDは共通電圧源からの印加電圧に依って半導
体基板中にポテンシャル井戸を形成する為の第１電極と
これと隣接してポテンシャル障壁を形成する為の第２電
極とからなる２枚１組の電極対からなる電極列を備え、
第１電極の電気抵抗を第２電極の電気抵抗より大ならし
めているので、第１電極に依って形成されるポテンシャ
ル井戸よりも第２電極に依って形成されるポテンシャル
障壁の方が応答時間が短くなり、このポテンシャル障壁
にて転送方向が決定されるキャリアの逆流転送を解消す
る事ができる。従って本発明に係るCCD固体撮像装置に
於いては、逆流キャリアの解消に依って再生画像のコン
トラストの劣化を防止でき、CCDメモリに於いては記憶
内容が破壊される惧れはない。(G) Effect of the Invention In the CCD of the present invention, a first electrode for forming a potential well in a semiconductor substrate and a second electrode for forming a potential barrier adjacent thereto are formed according to an applied voltage from a common voltage source. An electrode array consisting of two electrode pairs consisting of an electrode,
Since the electric resistance of the first electrode is made larger than that of the second electrode, the response time of the potential barrier formed by the second electrode is larger than that of the potential well formed by the first electrode. It becomes shorter, and it is possible to eliminate the backflow transfer of carriers whose transfer direction is determined by this potential barrier. Therefore, in the CCD solid-state image pickup device according to the present invention, the deterioration of the contrast of the reproduced image can be prevented by eliminating the backflow carrier, and the stored contents of the CCD memory are not likely to be destroyed.
第１図（イ），（ロ）は本発明のCCDの一実施例の平面
図、及び断面図、第２図（イ）（ロ）は従来のCCDの平
面図、及び断面図、第３図及び第４図はクロックパルス
の波形図、及びそれに伴う理論的なポテンシャル図、第
５図及び第６図は従来CCDに於ける各電極の電圧波形
図、及びそれに伴う実際のポテンシャル図、第７図及び
第８図は本発明CCDに於ける各電極の電圧波形図、及び
それに伴う実際のポテンシャル図である。 （１）……シリコン基板、（２）……シリコン酸化膜、
（31）（32）……第１電極、（41）（42）（41′）（4
2′）……第２電極。1 (a) and 1 (b) are a plan view and a sectional view of an embodiment of the CCD of the present invention, and FIG. 2 (a) (b) are a plan view and a sectional view of a conventional CCD. FIGS. 4 and 5 are waveform diagrams of clock pulses and theoretical potential diagrams accompanying them, and FIGS. 5 and 6 are voltage waveform diagrams of respective electrodes in a conventional CCD and actual potential diagrams associated therewith. 7 and 8 are a voltage waveform diagram of each electrode in the CCD of the present invention and an actual potential diagram associated therewith. (1) ... Silicon substrate, (2) ... Silicon oxide film,
(31) (32) ... first electrode, (41) (42) (41 ') (4
2 ') ... Second electrode.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭53−30282（ＪＰ，Ａ) 特開 昭51−78179（ＪＰ，Ａ) 特開 昭57−5361（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-53-30282 (JP, A) JP-A-51-78179 (JP, A) JP-A-57-5361 (JP, A)
Claims (1)
置し、この電極列に沿って上記半導体基板中の電荷を一
方向に転送する電荷結合素子に於いて、上記電極列は、
共通の電圧源からの印加電圧に依って半導体基板中に所
定の深さのポテンシャル井戸を形成する為の第１電極
と、この第１電極に対して電荷転送方向の上流側に隣接
して配置され、上記第１電極と同一の印加電圧に依って
上記ポテンシャル井戸よりも浅いポテンシャル障壁を形
成する為の第２電極とからなる２枚１組の電極対からな
り、この電極対の偶数番目と奇数番目とに交互に印加さ
れる２相のクロックパルスに応答して上記半導体基板中
の電荷を上記電極列に沿って転送すると共に、上記第１
電極及び第２電極を同一材料により形成し、且つ、上記
第２電極の幅を上記第１電極の幅より狭くする一方で上
記第２電極の膜厚を上記第１電極の膜厚より厚くして上
記第２電極の電気抵抗を上記第１電極の電気抵抗より小
さくし、上記電極対を成す上記第１電極及び上記第２電
極に同時に上記印加電圧が与えられると上記半導体基板
中のポテンシャル形態を上記第２電極下で上記第１電極
下より先んじて変動せしめる事を特徴とする電荷結合素
子。1. A charge-coupled device in which an electrode array is arranged on a semiconductor substrate via an insulating film, and charges in the semiconductor substrate are unidirectionally transferred along the electrode array, wherein the electrode array comprises:
A first electrode for forming a potential well of a predetermined depth in a semiconductor substrate according to an applied voltage from a common voltage source, and an adjoining upstream electrode in the charge transfer direction with respect to the first electrode And a second electrode for forming a potential barrier shallower than the potential well by the same applied voltage as that of the first electrode. The charges in the semiconductor substrate are transferred along the electrode array in response to the two-phase clock pulses alternately applied to the odd-numbered and
The electrode and the second electrode are formed of the same material, and the width of the second electrode is made narrower than the width of the first electrode while the film thickness of the second electrode is made thicker than the film thickness of the first electrode. When the electric resistance of the second electrode is made smaller than the electric resistance of the first electrode, and the applied voltage is applied to the first electrode and the second electrode forming the electrode pair at the same time, the potential form in the semiconductor substrate is changed. The charge-coupled device is characterized in that it is varied under the second electrode and under the first electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59190301A JPH0697669B2 (en) | 1984-09-11 | 1984-09-11 | Charge coupled device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59190301A JPH0697669B2 (en) | 1984-09-11 | 1984-09-11 | Charge coupled device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6167963A JPS6167963A (en) | 1986-04-08 |
| JPH0697669B2 true JPH0697669B2 (en) | 1994-11-30 |
Family
ID=16255880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59190301A Expired - Lifetime JPH0697669B2 (en) | 1984-09-11 | 1984-09-11 | Charge coupled device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0697669B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3141401B2 (en) * | 1991-01-23 | 2001-03-05 | ソニー株式会社 | Charge transfer device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5178179A (en) * | 1974-12-27 | 1976-07-07 | Sony Corp | |
| JPS5330282A (en) * | 1976-09-01 | 1978-03-22 | Hitachi Ltd | Semiconductor device |
| JPS575361A (en) * | 1980-06-11 | 1982-01-12 | Toshiba Corp | Charge transfer device |
-
1984
- 1984-09-11 JP JP59190301A patent/JPH0697669B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6167963A (en) | 1986-04-08 |
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