JP2723063B2 - Charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device, and more particularly, to a CCD shift register provided with a charge detection portion having a transmission electrode formed of a storage electrode and a barrier electrode and a floating diffusion layer.

[0002]

2. Description of the Related Art FIG. 5 shows a charge transfer device (for example, "Technical Report of the Institute of Television Engineers of Japan", Vol. 16, No. 28,
FIG. 5A is a plan view (FIG. 5A) and FIG. 5B is a cross-sectional view (FIG. 5B) showing the configuration of pages 13 to 18 (described in 1992).

An N-type buried channel layer 2 is provided on the surface of a P-type silicon substrate 1 and partitioned by a P ⁺ type channel stopper 6. A plurality of strip-shaped transfer electrodes (three, 8, 9, and 10 of them) are arranged in a row across the surface of the N-type buried channel layer 2 via the gate oxide film 7. These transfer electrodes are pairs of barrier electrodes (..., 9b) and storage electrodes (..., 9s). For example, an N ⁻ -type barrier region 3 is provided on the surface of the N-type buried channel layer 2 immediately below the barrier electrode.
Is provided. An output gate electrode 11 is provided near the final transfer electrode 10. Reference numeral 4 denotes a floating diffusion layer (here, a region continuous with the N-type buried channel layer 2), which is connected to the output amplifier AMP. 12 is a reset gate electrode,
5 is a reset drain.

FIG. 6 schematically shows a driving pulse applied to each of the transfer electrode and the reset gate electrode, and a potential under each electrode at time t. FIG.
6 assumes a two-phase drive shift register, and the drive pulse φ _L applied to the final transfer electrode 10 is the same as the pulse φ ₁ applied to the transfer electrode 8. The signal charge Q ₂ stored immediately below the final transfer electrode 10 is φ
_{By changing L} from the high level to the low level, the potential is transferred to the floating diffusion layer 4 beyond the potential immediately below the output gate electrode 11 at time t.

[0005]

Problems to be Solved by the Invention The CC shown in FIGS.
Maximum amount of charge that can be transferred in D shift register is determined by the potential difference [Delta] [Psi] ₁ between the area and the lower storage electrode and the barrier electrode of a N-type buried channel layer under the storage electrode. Usually, the area of the floating diffusion layer 4 is designed to be as small as possible to improve the detection sensitivity at the output section, and the channel width is narrowed from below the final transfer electrode. Therefore, in order to keep the amount of charge stored under the final transfer electrode to the same value as under the transfer electrodes of the otherwise even a storage electrode length L ₂ of the final transfer electrode than the storage electrode length L ₁ of the other transfer electrodes It needs to be longer. For example, in the case of the conventional example shown in FIG.
To 10 μm, but L ₁ = 3.5 μm
In this case, L ₂ ≧ 4.4 μm must be satisfied. As a result, there is a problem that the transfer time of the signal charge from the final transfer electrode to the floating diffusion layer is limited, and high-speed operation is hindered.

An object of the present invention is to provide a charge transfer device which can operate at high speed and eliminates the above-mentioned conventional disadvantages.

[0007]

According to the present invention, there is provided a charge transfer device comprising n (n is a positive integer) barrier electrode-storage electrode pairs arranged in a row on a surface of a semiconductor substrate via a gate insulating film. , A final transfer electrode that is a storage electrode disposed close to the n-th storage electrode, an output gate electrode disposed close to the final transfer electrode, and the semiconductor immediately below the output gate electrode. A charge detection unit having a floating diffusion layer provided in proximity to the surface of the substrate; and a drive pulse applied to the final transfer electrode when the drive pulse applied to the n-th storage electrode is at a low level. Means for changing from a high level to a low level.

Here, for example, the impurity concentration at the surface of the semiconductor substrate may be lower immediately below the barrier electrode than below the storage electrode.

The low level voltage of the drive pulse applied to the final transfer electrode may be higher than the low level voltage of the drive pulse applied to transfer electrodes other than the last transfer electrode.

Further, the impurity concentration of the surface portion of the semiconductor substrate immediately below the final transfer electrode may be higher than that of the portion immediately below the transfer electrode other than the final transfer electrode.

Furthermore, an N-type buried channel layer formed in a P-type region on the surface of the semiconductor substrate may be provided below the transfer electrode.

[0012]

[Action] n-number of the maximum amount of charge that can be transferred under the transfer electrodes is determined by the potential difference [Delta] [Psi] ₁ between the area and the lower storage electrode and the barrier electrode of a transfer channel under the storage electrode. Final maximum charge amount which can be accumulated under the transfer electrodes is determined by the potential difference [Delta] [Psi] ₂ under the final transfer electrode and the lower output gate electrode. Therefore, ΔΨ
By ₂ a greater than [Delta] [Psi] _1, can be set the channel length L _2A under the final transfer electrode to the n-channel L ₁ under the storage electrode of the transfer electrodes of equal to or less.

[0013]

FIG. 1A is a plan view showing a main part of a first embodiment of the present invention, and FIG. 1B is a sectional view taken along line XX of FIG. 1A. FIG. 2B is a time chart showing drive pulses respectively applied to the transfer electrode and the reset gate electrode for explaining the first embodiment, and FIG. 2A is the same at times t ₁ and t ₂ . FIG. 5 is a potential diagram schematically showing a potential under each electrode.

Also in this embodiment, a two-phase drive shift register is assumed as in the conventional example shown in FIGS. The present embodiment differs from the conventional example in the structure in that the final transfer electrode 10A is constituted only by the storage electrode. Accordingly, the driving pulse φ _L applied to the final transfer electrode 10A is also changed to the pulse φ ₁ applied to the transfer electrode 8.
Means that the high level voltage and the low level voltage are the same, but the timings are different. At time t _1, then output the signal charges are accumulated under the final transfer electrode 10A. At time t _2, the by leaving phi _L state pulse phi ₂ is at low level voltage applied to the transfer electrode 9 becomes a low level voltage, the final transfer electrode 10
The signal charge accumulated under A is output gate electrode 11
The potential is transferred to the floating diffusion layer 4 beyond the potential under A. Unlike the driving pulse of the conventional example shown in FIG.
When A changes from high level to low level voltage ,
The reason for keeping the previous transfer electrode 9 at the low-level voltage is to prevent signal charges from returning back below the transfer electrode 9 because the final transfer electrode is constituted only by the storage electrode. is there. Incidentally, and FIG. 2 (b) to the driving pulses shown, phi ₂ is high level phi _L than the timing of changing from the low level to the high level voltage from the low level
Although the timing at which the voltage changes to a lower voltage is delayed, if φ _L maintains a low-level voltage for a period necessary for the signal charges under the final transfer electrode to be completely transferred to the floating diffusion layer, φ ₂ and simultaneously or φ earlier than ₂ φ _L there is no problem even if from a low level to a high level of voltage.

In the present embodiment, the maximum charge amount under the transfer electrodes other than the final transfer electrode 10A is the same as in the conventional example, and the area of the storage electrode and the potential difference ΔΨ ₁ between the storage electrode and the barrier electrode.
Is determined. The impurity implantation amount of the N-type buried channel layer is 1 × 10 ^{12 to} 5 × 10 ¹² cm ⁻² , and the ion implantation amount of the impurity of the opposite conductivity type for forming the N ⁻ -type barrier region 3 is 4 ΔΨ when × 10 ¹¹ to 8 × 10 ¹¹ cm ^-2
₁ can be 2V. On the other hand, the maximum charge amount under the final transfer electrode is determined by the potential difference [Delta] [Psi] ₂ under the final transfer electrode and the lower output gate electrode. When the output gate voltage V _OG is 1 to ₂ V as in the conventional example, ΔΨ ₂ can be 3 V. However, the driving pulses φ _1, φ _2, φ _L high-level voltage V _H is 5 volts, the low level voltage V _L is 0 volts, the thickness of the gate oxide film 7 is 400 to 800 nm. When the width of the N-type buried channel layer is linearly reduced from 30 μm to 10 μm in a region with a distance of 5 μm, the channel length L _2A below the final transfer electrode 10A can be reduced to 3.0 μm. However, the storage electrodes 9s, 8s,.
Channel length L ₁ below the 3.5 [mu] m. Therefore, the signal charge Q ₂ to which was under the final transfer electrode 10A at time t _1, the time to be transferred to the floating diffusion layer 4 is shorter than the conventional example, high-speed operation can be realized.

FIG. 3B is a time chart showing driving pulses for explaining the second embodiment of the present invention.
(A) is a potential under each electrode at time t ₂ is a potential diagram showing schematically.

[0017] indicates a driving pulse waveform differs from FIG. 2, the low level voltage of phi _L V _LA (e.g. 1 to 2 V) is phi ₁ and phi ₂ of the low level voltage V _L (e.g., 0
V). The device structure of the charge transfer device is the same as that shown in FIG. This allows, when transferring from the final transfer electrode 10A at time t ₂ as shown in FIG. 3 (a) to the floating diffusion layer 4, between the storage electrode 9s of a final transfer electrode 10A and the previous transfer electrodes Since a potential difference is generated and an electric field for accelerating the transfer in the transfer direction is formed, a higher-speed operation can be performed. In FIG. 3B, the high-level voltage of φ _L is φ ₁ and φ
_Although an example is shown in which only the low level voltage is raised at the same value as ₂ , the high level voltage can also be raised at the same time. In this case, since the potential difference [Delta] [Psi] ₂ of the final transfer electrode and the output gate electrode shown in FIGS. 2 (a) becomes larger, the final transfer electrode length L _2A can be further shortened, higher speed of transfer is realized You.

FIG. 4 is a sectional view showing a third embodiment of the present invention.

In this embodiment, the N-type buried channel layer 2 has an impurity implantation amount of about 2 × 10 ¹¹ to 4 × 10 ¹¹ cm ⁻² below the final transfer electrode 10B than the N-type buried channel layer 2. It has many high concentration regions 2A. Thus, the potential under the final transfer electrode 10B becomes deeper than the potential under the other transfer electrodes even when the same voltage is applied. Therefore, FIG.
Even when driven by the pulse shown in (b), the effect of accelerating the charge transfer from below the final transfer electrode to the floating diffusion layer can be obtained as in the embodiment of FIG.

Although FIG. 4 shows an example in which the high-concentration region 2A is formed only under the final transfer electrode, the high-concentration region 2A is formed below the output gate electrode 11A, the floating diffusion layer 4, and the reset gate electrode 12. May be extended. Further, it is also possible to combine with the driving pulse shown in FIG. Then, the speed can be further increased.

[0021]

As described above, according to the present invention, since the final transfer electrode is constituted only by the storage electrode, the transfer time of the signal charge to the floating diffusion layer can be shortened by shortening the electrode length, and the speed can be increased. Operation can be realized. Further, by the pulse low-level voltage to be applied to the final transfer electrode is higher than the low-level voltage of the other transfer electrodes, or impurity concentration than the other under the final transfer electrode to form a high buried layer, It is possible to further speed up the charge transfer from below the final transfer electrode to the floating diffusion layer.

[Brief description of the drawings]

FIG. 1 is a plan view (FIG. 1) showing a first embodiment of the present invention;
(A)) and sectional drawing (FIG.1 (b)).

FIG. 2 is a potential diagram (FIG. 2A) and a time chart of drive pulses (FIG. 2B) for explaining the first embodiment of the present invention.

3A and 3B are a potential diagram (FIG. 3A) and a time chart of drive pulses (FIG. 3B) for explaining a second embodiment of the present invention.

FIG. 4 is a sectional view showing a third embodiment of the present invention.

FIG. 5 is a plan view (FIG. 5A) and a cross-sectional view (FIG. 5B) showing a conventional example.

FIG. 6 is a potential diagram (FIG. 6A) and a time chart of drive pulses (FIG. 6B) for explaining a conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 P-type silicon substrate 2 N-type buried channel layer 2 A high-concentration region 3 barrier region 4 floating diffusion layer 5 reset drain 6 P ⁺ -type channel stopper 8, 9 transfer electrode 8 s, 9 s storage electrode 8 b, 9 b barrier electrode 10, 10 A , 10B Final transfer electrode 11, 11A Output gate electrode 12 Reset gate electrode

Claims (5)

(57) [Claims] A transfer electrode group comprising n (n is a positive integer) barrier electrode-storage electrode pairs arranged in a row on a surface of a semiconductor substrate with a gate insulating film interposed therebetween, and the n-th storage electrode A final transfer electrode that is a storage electrode disposed in close proximity to the semiconductor device, an output gate electrode disposed in proximity to the final transfer electrode, and a floating electrode provided in proximity to a surface portion of the semiconductor substrate immediately below the output gate electrode. A charge detection unit having a diffusion layer,
High level applied to the final transfer electrode when the drive pulse applied to the nth storage electrode is at a low level
And a two-level drive in which the low level is maintained for a certain period of time.
Means for changing a dynamic pulse from a high level to a low level. 2. The charge transfer device according to claim 1, wherein an impurity concentration at a surface portion of the semiconductor substrate is lower immediately below the barrier electrode than at a position immediately below the storage electrode. 3. The electric charge according to claim 1, wherein the low-level voltage of the drive pulse applied to the final transfer electrode is higher than the low-level voltage of the drive pulse applied to the transfer electrodes other than the last transfer electrode. Transfer device. 4. The charge transfer device according to claim 1, wherein an impurity concentration of a surface portion of the semiconductor substrate immediately below the final transfer electrode is higher than an impurity concentration immediately below the transfer electrode other than the final transfer electrode. 5. The charge transfer device according to claim 1, wherein the N-type buried channel layer formed in the P-type region on the surface of the semiconductor substrate is provided below the transfer electrode.