CA1101548A - Two phase charge coupled devices employing fixed charge for creating asymmetrical potential wells - Google Patents
Two phase charge coupled devices employing fixed charge for creating asymmetrical potential wellsInfo
- Publication number
- CA1101548A CA1101548A CA149,504A CA149504A CA1101548A CA 1101548 A CA1101548 A CA 1101548A CA 149504 A CA149504 A CA 149504A CA 1101548 A CA1101548 A CA 1101548A
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- 239000000758 substrate Substances 0.000 claims abstract description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 15
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052681 coesite Inorganic materials 0.000 description 6
- 229910052906 cristobalite Inorganic materials 0.000 description 6
- 229910052682 stishovite Inorganic materials 0.000 description 6
- 229910052905 tridymite Inorganic materials 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000037452 priming Effects 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- -1 oxide Substances 0.000 description 1
- 230000003389 potentiating effect Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42396—Gate electrodes for field effect devices for charge coupled devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76866—Surface Channel CCD
- H01L29/76875—Two-Phase CCD
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
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Abstract
Abstract Two phase operation of charge-coupled circuits is achieved by employing electrode pairs which create asymmetri-cal potential wells in a semiconductor substrate by storing fixed charge in the insulation beneath one electrode of each pair. The charge may be stored, for example, at the inter-face between a relatively thin silicon dioxide layer and a relatively thick silicon nitride layer.
Description
RC~ 64,936 1 The present invention is directed in charge coupled circuits whose electrodes are arranged in pairs for generating asymmetrical potential for achieving unidirectional charge propagation.
A number of electrode structures for creating asymmetrical potential wells in a semiconductor substrate of a charge-coupled shift circuit are described in copending application Serial No. 129~812, now Canadian Patent No.
1,080,847 filed by the present inventor and assigned to the same assignee as the present application. These include electrode pairs of which one electrode is closer to the substrate than the other and electrode pairs of which one electrode is permanently biased at a direct voltage level different than the other. Some important operating advantages of these structures are:that high-~speed unidi~ectional charge ~ :
propagation can be achieved with a two phase driving voltage and employing simple and compact cell geometry.
The present application described still other ~-arrangements for obtaining asymmetrical potential wells with simple, relatively small electrode structures.
~ two-phase operated information storage and transfer device embodying the invention includes a semi-conductor substrate and an insulating layer formed on this substrate. It includes also electrode means on said insulating layer and charge in said insulating layer which ls of di~feren-t magnitude beneath one portion of the electrode means than beneath the remaining portion thereof to thereby create in said substrate when a voltage is applied to said electrode means, an asymmetrical potential well.
X ~ ~
~ 5~ RCA 64,936 ~ ~
1 In the detailed description which follows reference is made to the drawings attached to and forming a part of this specification, and in whi¢h:
FIGURE 1 is a cross section taken through a charge~
coupled circuit according to one embodiment of the invention; ~-FIGURE 2 is a drawing of the two-phase voltage wave-form employed in the operation of the circuit of FIGURE l;
FIGURE 3 is a drawing of potential wells which occur during the operation of the circuit of FIGURE l; ~
FIGURES 4, 5 and 6 are cross sections through ~ -other embodi~ents of charge-coupled circuits according to the invention; and FIGURE 7 is a drawing of;potential wells which occur during the operation of the circuit of FIGURE 6.
The charge-coupled~circuit~shown in FIGURE 1 includes a p-type silicon substrate 6 formed with insulation means on one surface thereof. The! insulation~means includes ~-O ~ :-.
a very thin (20~50 Angstroms (A)) layer 8 of silicon dioxide ~ ~
O O
~SiO2) and a relatively thicker (400 A to 800 A or so) layer 9 of silicon nitride (Si3N4). In the transistor art, multiple layers such as these are known a5 MNOS (metal, nitride, oxide, semiconductor) structures. Electrodes arranged in pairs 10-1, 12-1; 10-2, 12-2; and so on, are located on the si3N4 surface.
Before discussiny the operation of the circuit of FIGURE 1, a brief review is in order of the general theory of operation of charge-coupled devices. If a positive voltage pulse is applied to an eIectrode such as 12-1 there is formed a so-called deep depletion region in the portion of the p-type silicon substrate immediately beneath this X
~ 8 RCA 64,936 1 electrode. In other words, the applied positive voltage pulse repels majority carriers, holes in the case of a p-type substrate, from the surface of the substrate directly beneath the electrode 12-1. This causes a potential well to be formed at the surface of the p~type silicon which corresponds to the induced depletion region. The depth of the potential well is proportional to the square of the depth of the depletion region.
Any potential well formed at the surface of the silicon substrate will tend to accumulate minority carriers (electrons in this example). If available from no other place, they will come from the substrate itself. However, as in circuits described in the copending application, the minority charges initially may be introduced by a source electrode which may be imbedded in the p-type silicon and which may be located at one end of the silicon substrate or may be introduced by llght or other means.
Charge stored in the substrate under one electrode may be propagated to the region of the substrate beneath the 20 next electrode by the use of multiple-phase voltages. As explained in the copending application, when three or more phases are employed, unidirectional charge propagation takes place. However, it is desirable in the interest of simpli-fying the construction to be able to operate a charge-coupled circuit with a two-phase drivling voltage. When operated in this way9 special electrode structures must be employed which create asymmetrical potential wells in the substrate to insure unidirectional charge propagation The electrode structure shown in FIGURE l does provide asymmetrioal potentlal wells in the substrate 6.
_g_ ~3~5~ RCA 64,936 1 As already mentioned, the electrodes are arranged in pairs.
To start with, the electrode 12 o~ each pair is connected through a switch, shown schematically at 14-1, 14-2 and 14-3, to a source of negative voltage -V which may have a value o~
5 say 40 volts or so (~or a 40 A layer). In response to this :~
negative voltage, a positive charge accumulates at the SiO2, Si3N4 interface beneath each electrode 12. After this charge has accumulated, and this takes only a matter o~ seconds or less, the voltage source -V may be disconnected and the charge will remain stored.
After the charge, as described above, has been accumulated in the insulation means, the switches 14 are thrown to their second position. This directly connects each 12 electrode to its corresponding~10 electrode. Now, even în the absence of a multiple-phase voltage, there is created beneath each electrode pair an asymmetrical potential well. Due to the charge located beneath the 12 electrode of each pair, the potential well is deeper in the substrate beneath that electrode than in the region o~ the substrate beneath its paired electrode 10. When a positive voltage is applied to an electrode pair 12, lO, the potential well beneath the electrode 12 becomes deeper and the potential well beneath the electrode 10 becomes deeper; however7 the asymmetry remains in view of the additional electric field created by the permanently stored positive charge.
The operation of the FIGURE 1 circuit is graphically depicted in EIGURES 2 and 3. The ~1 and ~2 waveforms may extend ~rom say 0 volts to +10 volts. At time to~ the ~1 voltage, which is relatively positive, creates a relatively 3 deep, asymmetrical potential well in the semiconductor RCA 64,936 5~
1 substrate beneath electrode pair 10-1, 12-1 as shown in the upper part of FIGURE 3. The charye signal i.e., electrons in this case, will be transferred along the surface of the silicon substrate under the "channel oxide" (the thin sio2 layer). ~ut for the purpose of this illustration, the charge signal is represented by the crosses which indicate the reduction of the surEace potential due to the presence of the charge signal. In view of the substantially deeper potential well beneath electrode 12-1 (due to the fixed positive charge stored in the oxide under 12-1) than beneath electrode 10-1, this negative charge accumulates substantially entirely in the region of the substrate beneath electrode 12~
At time to~ 0 volts is being applied to the next adjacent electrode pair 10-2, 12-2. Accordingly, the asymmetrical potential weIl formerl beneath this electrode pair is reIatively shallower than that beneath the pair 10-1, 12-1. The relatively shallower well at 10-2 creates a potential barrier to the flow, i.n the ~orward direction ~to the right), of charge stored at 18 and to the flow, in the reverse direction (to the left), of khe charge stored under 12-2. (For purpose of generality, even though 0 volts is applied to this electrode, this well is shown to have some finite depth. This also may be taken to represent a fixed but relatively low level of reverse bias applied to the substrate, as discussed in the copending application.) In similar fashion, the asymmetrical potential well beneath electrode pair 10-0, 12-0 (these electrodes are not shown in FIGURE 1) is of the same configuration as the potential weIl beneath 10-2, 12 2. Note that the potential well beneath electrode 12-0 is shallower than the potential well --6~
~,/
5~L8 RCA 6~,936 1 beneath electrode 10-1. This condition is required to insure unidirectional ilow of the charge signal (i.e. the electrons) from left to right.
At -time tl, the voltage ~2 already is positive to the extent of -~10 volts. The voltage ~1 is changing in value from its positive value of ~10 volts to 0 volts. The effect of these voltages i5 to cause a transfer of negative charge to occur as depicted in the middle portion of FIGURE
3. The asymmetrical potential well beneath electrode pair 10-2, 12-2 is at its greatest depth. The asymmetrical potential well beneath electrode pair 10-1, 12-1 is becoming shallower. When the potential well at electrode 12-1 be-comes shallower than the potential well beneath electrode 10-2, the charge stored under the former electrode "spills into" the potential well beneath the latter electrode.
Nowever, at this time the potential well beneath the electrode 12-2 is even deeper than the potential well beneath electrode 10~2 so that charge continues to "run down hill" until it settles into the potential well beneath electrode 12-2.
Under the influence of the self-induced drift field, the thermal diffusion, and the fringing fiel.d, the charge will be transferred, within a matter of nanoseconds, essentially completely from the potential well beneath electrode 12-1 to the potential well beneath electrode 12-2.
Shortly after time tl, all ~of the negative charge formerly stored at electrode 12-1 is stored at electrode lZ-2. Considerably later, at time t2 (last portion of FIGURE 3) the charge remains in the potential well beneath electrode 12 2, as shown. Shortly before time t3, this 3 charge would begin to transfer to the next electrode pair ~ 5~ RCA 64,93~
1 10-3, 12-3.
~ preferred form of electrode structure according to one embodiment of the invention is shown in FIGURE ~.
The method for fabricating this general type of structure is discussed in detail in the copending application although there the insulation employed is on]y a single material Note that here the interface between the thin SiO2 layer and the relatively thicker Si3N~ layer occurs only beneath the aluminum electrodes 12. Accordingly, the positive charge 10 shown, initially may be introduced without the need for ~ -switches such as 14 of FIGURE I. It is necessary only to connect all of the ~1 and ~2 leads together and to a relatively negative voltage source -V and then to disconnect the voltage source and place the circuit in operation in the manner already discussed. (The same holds for the FIGURE 5 and 6 arrangements.) As in the embodiment of FIGURE 1, once the positive charges accumulate at the Si3N4, SiO~ inter-facesj they remain there permanently, provided the positive phase voltages are always maintained considerably smaller than the initial negative priming pulse (by a factor such as 3 or 4) While illustrated as having a p-type substrate, it is to be understood that the arrangement of FIGURE 4 can instead have an n-type silicon substrate. In this case, fixed, negative charges initially may~be stored under the aluminum electrodes by applying a positive voltage level to all electxodes for a short period of time. Also, while the polysilicon electrodes are shown to be of n-type, either p or n-type may be used with either the n-type or the p-type silicon substrate.
RCA 64,936 ~ -:
:: .
1 The operation of the two-phase charge-coupled structure described here relies on fixed storage of diff'erent amounts or dif'ferent polarities of charge in the channel oxide under two ad~acent electrodes powered by the same phase voltage. The preferred way to form such charge-coupled structures is in the form of overlapping electrodes. Such electrodes can be in the form of polysilicon electrodes overlapped by aluminum electrodes as shown in FIGIJRES 4, 5 and ~. However, an alternate way is to use pairs of electrodes both made of polysilicon or of some other re~
fractory material.
While in the embodiment of the invention shown in FIGURE 4 the polarity of the charge is chosen to produce a deeper potential well under one electrode of a pair than under the other, it can instead be chosen to~form a barrier under one electrode of the pair. This will be discussed later in connection with FIGURE 6.
Another ~orm of the present invention is illustrated in FIGURE 5. Here, the substrate is illustrated as being of n-type rather than of p-type and the insulation includes a relatively thick (l000 A - 2000 A) layer of aluminum oxide (Al203) between the aluminum electrodes and the substrate and between the aluminum and polysilicon electrodes. The charge stored in the Alz03 beneath the aluminum electrodes 25 is negative and results in deeper potential wells (more '-negative surface potential) at the substrate locations beneath the stored charges than at the substrate locations beneath the polysilicon electrodes. The intentionally introduced layer (about 40 A9 thick) of SiO2 used in the construction of the MNOS structures, as shown in FIGURE 4, RCA 64,936 .5~3 1 is not really necessary when using aluminum oxide. With the latter, the permanent storage of a negative charge may be accomplished as described, ~or example, in S. Nakanuma et al, "A Read-Only Memory Using ~AS Transistors", Digest of Technical Papers, 1970 International Solid State Circuit Con~erence, Philadelphia, Pa., pp. ~8~69.
As other alternati~es, the aluminum oxide of FIGURE 5 may be of the type ~ormed by pyrohydrolysis o~
AlC13 (S.K. Tung and R.~. Ca~fney, Trans. Met. Soc. AIME, 233, 572 [1968]) or o~ the type ~ormed by reduction o~
Al-isopropoxide (M.T. Duf~y and ~. Revesz, J. Electrochemical Soc. 117, 372 [1969]). In both of these cases, the A1203 can be prepared with a fixed negative charge already "naturally" stored therein. This means that two~phase charge-coupled structures made in these ways can be operated without the need for an initial positive priming voltage to be applied to the electrodes under which it is desired that the negative charge be stored. However, even in these cases, if the aluminum oxide initially is made without a su~icient amount of the negative charge ~or the present purposes, the additional negative charge needed can be introduced by the means already discussed (the application o~ positive voltage level ~or a given time intervalj and discussed also -;~
in another context in the ~. Nakanuma et al article.
In the operation o~ the FIGURE 5 circuit, rather than employing multiple phase voltages which extend from 0 to ~10 volts, they instead have a value ~rom 0 volts to some negative voltage such as -10 volts. The phase relation-ship between the ~1 and ~2 voltages is analagous to that ~ FIGUR~ 2 and is as shown in FIGURF 13 in the copending - RCA 64,936 .3~
1 application mentioned above. The minority carriers which accumulate in the FIGURE 5 circuits, of course, are holes rather than electrons.
Since it is normally simple to store only the negative charge in the pyrolytic aluminum oxide, the type of substrate employed determines whether (a) deep wells or (b) barriers are created. In the FIGURE 5 structure, the substrate is of n-type so deep wells are produced, as already discussed. In the FIGURE 6 structure, the substrate is p-type so that the negative charges in the A1203 beneath the alùminum electrodes create potential barriers to the flow of charge. This structure can be made to provide exceptionally good performance if there is a relatively narrow separation between the~polysilicon electrodes, for example, 3 micro-meters (~m) as shown in FIGURE 6.
The operation of the two-phase charge-coupled shift registers using charge stored in the aluminùm oxide to form ~ ;
: .
energy barriers for the signal charge can be similar to the ~ operation illustrated in FIGURE 3, provided that an appropriate d--c bias voltage is applied to the electrodes to compensate for the induced energy ~arriers. Operation in this way is illustrated in FIGURES 7a and 7b. FIGURE 7a shows the potential wells created in the absence of ~1 and ~2 voltages.
FIGURE 7b illustrates the case where ~2 goes negative while ~1 remains as in FIGURE 7a. Another mode of operation is also possible, as shbwn in FIGURE 7c. Here, the maximum value of the phase voltages is such that finite potential barriers always exit beneath the permanent negatively charged regions, which prevent the complete RCA 64,936 ~.~}I.D~
1 transfer of charge between two potential wells. Such operation, in which the charge stored at each potential well is made to be comparable with the signal charge, is desirable for minimizing the effect of charge trapping at the silicon, aluminum-o~ide interface. ThiS type of opera-tion is possible for the FIGURE 6 structure or for a struc-ture (not shown) havlng a p-type substrate, SiO2 under the aluminum electrodes and A1203 under the polysilicon electrodes and with reIatively large negative charges stored in the ,, A1203 beneath the polysilicon electrodes.
In the embodiments of the invention discussed above, charge'is permanently stored in the insulation beneath one'of the eIectrodes of each'pair and no charge is stored ' in the insulation beneath the other electrode. It is to be understood, of course, that other forms of the invention are -possible. For example, negative~charge may be stored in the ;
insulation under one electrode of each pair and positLve charge in the insulation under another or different amounts of charge, one can be but need not necessarily be zero, may be stored in the insulation under the two electrodes of a pair. What is important in each case is that there be a ,;~
different charge ~either in amount or sign3 stored in the insulation beneath one eIectrode of each pair than in the ;
insulation beneath the other to provide the required asymmetry to the potent~al well formed in the substrate. It is also to be understood that while two examples of materials which may be employed for the insulation means that are given, there are'others which'are possible and which are within the scope of the present invention.
, .- ..
D(~\ 6 a, q36 1 The layout of electrodes (plan view), in the circuits described here may be similar to that described in the copending application For example, a two dimensional array operating as a shift register may have a configuration similar to that of FIGURES 17-19 o~ the copending application.
The present invention also may be used in other applications such as in light sensing arrays, memories and so on. In these various arrangements, each signal channel comprises a relatively thin SiO2 or other insulating film located between thicker insulating ~ilm regions. The present in-vention also is useful in charge-coupled structures in which the channel regions comprise relatively weakly doped sub-strate regions located between relatively strongly doped substrate regions as described recently b~ Bell Telephone La~oratories.
A number of electrode structures for creating asymmetrical potential wells in a semiconductor substrate of a charge-coupled shift circuit are described in copending application Serial No. 129~812, now Canadian Patent No.
1,080,847 filed by the present inventor and assigned to the same assignee as the present application. These include electrode pairs of which one electrode is closer to the substrate than the other and electrode pairs of which one electrode is permanently biased at a direct voltage level different than the other. Some important operating advantages of these structures are:that high-~speed unidi~ectional charge ~ :
propagation can be achieved with a two phase driving voltage and employing simple and compact cell geometry.
The present application described still other ~-arrangements for obtaining asymmetrical potential wells with simple, relatively small electrode structures.
~ two-phase operated information storage and transfer device embodying the invention includes a semi-conductor substrate and an insulating layer formed on this substrate. It includes also electrode means on said insulating layer and charge in said insulating layer which ls of di~feren-t magnitude beneath one portion of the electrode means than beneath the remaining portion thereof to thereby create in said substrate when a voltage is applied to said electrode means, an asymmetrical potential well.
X ~ ~
~ 5~ RCA 64,936 ~ ~
1 In the detailed description which follows reference is made to the drawings attached to and forming a part of this specification, and in whi¢h:
FIGURE 1 is a cross section taken through a charge~
coupled circuit according to one embodiment of the invention; ~-FIGURE 2 is a drawing of the two-phase voltage wave-form employed in the operation of the circuit of FIGURE l;
FIGURE 3 is a drawing of potential wells which occur during the operation of the circuit of FIGURE l; ~
FIGURES 4, 5 and 6 are cross sections through ~ -other embodi~ents of charge-coupled circuits according to the invention; and FIGURE 7 is a drawing of;potential wells which occur during the operation of the circuit of FIGURE 6.
The charge-coupled~circuit~shown in FIGURE 1 includes a p-type silicon substrate 6 formed with insulation means on one surface thereof. The! insulation~means includes ~-O ~ :-.
a very thin (20~50 Angstroms (A)) layer 8 of silicon dioxide ~ ~
O O
~SiO2) and a relatively thicker (400 A to 800 A or so) layer 9 of silicon nitride (Si3N4). In the transistor art, multiple layers such as these are known a5 MNOS (metal, nitride, oxide, semiconductor) structures. Electrodes arranged in pairs 10-1, 12-1; 10-2, 12-2; and so on, are located on the si3N4 surface.
Before discussiny the operation of the circuit of FIGURE 1, a brief review is in order of the general theory of operation of charge-coupled devices. If a positive voltage pulse is applied to an eIectrode such as 12-1 there is formed a so-called deep depletion region in the portion of the p-type silicon substrate immediately beneath this X
~ 8 RCA 64,936 1 electrode. In other words, the applied positive voltage pulse repels majority carriers, holes in the case of a p-type substrate, from the surface of the substrate directly beneath the electrode 12-1. This causes a potential well to be formed at the surface of the p~type silicon which corresponds to the induced depletion region. The depth of the potential well is proportional to the square of the depth of the depletion region.
Any potential well formed at the surface of the silicon substrate will tend to accumulate minority carriers (electrons in this example). If available from no other place, they will come from the substrate itself. However, as in circuits described in the copending application, the minority charges initially may be introduced by a source electrode which may be imbedded in the p-type silicon and which may be located at one end of the silicon substrate or may be introduced by llght or other means.
Charge stored in the substrate under one electrode may be propagated to the region of the substrate beneath the 20 next electrode by the use of multiple-phase voltages. As explained in the copending application, when three or more phases are employed, unidirectional charge propagation takes place. However, it is desirable in the interest of simpli-fying the construction to be able to operate a charge-coupled circuit with a two-phase drivling voltage. When operated in this way9 special electrode structures must be employed which create asymmetrical potential wells in the substrate to insure unidirectional charge propagation The electrode structure shown in FIGURE l does provide asymmetrioal potentlal wells in the substrate 6.
_g_ ~3~5~ RCA 64,936 1 As already mentioned, the electrodes are arranged in pairs.
To start with, the electrode 12 o~ each pair is connected through a switch, shown schematically at 14-1, 14-2 and 14-3, to a source of negative voltage -V which may have a value o~
5 say 40 volts or so (~or a 40 A layer). In response to this :~
negative voltage, a positive charge accumulates at the SiO2, Si3N4 interface beneath each electrode 12. After this charge has accumulated, and this takes only a matter o~ seconds or less, the voltage source -V may be disconnected and the charge will remain stored.
After the charge, as described above, has been accumulated in the insulation means, the switches 14 are thrown to their second position. This directly connects each 12 electrode to its corresponding~10 electrode. Now, even în the absence of a multiple-phase voltage, there is created beneath each electrode pair an asymmetrical potential well. Due to the charge located beneath the 12 electrode of each pair, the potential well is deeper in the substrate beneath that electrode than in the region o~ the substrate beneath its paired electrode 10. When a positive voltage is applied to an electrode pair 12, lO, the potential well beneath the electrode 12 becomes deeper and the potential well beneath the electrode 10 becomes deeper; however7 the asymmetry remains in view of the additional electric field created by the permanently stored positive charge.
The operation of the FIGURE 1 circuit is graphically depicted in EIGURES 2 and 3. The ~1 and ~2 waveforms may extend ~rom say 0 volts to +10 volts. At time to~ the ~1 voltage, which is relatively positive, creates a relatively 3 deep, asymmetrical potential well in the semiconductor RCA 64,936 5~
1 substrate beneath electrode pair 10-1, 12-1 as shown in the upper part of FIGURE 3. The charye signal i.e., electrons in this case, will be transferred along the surface of the silicon substrate under the "channel oxide" (the thin sio2 layer). ~ut for the purpose of this illustration, the charge signal is represented by the crosses which indicate the reduction of the surEace potential due to the presence of the charge signal. In view of the substantially deeper potential well beneath electrode 12-1 (due to the fixed positive charge stored in the oxide under 12-1) than beneath electrode 10-1, this negative charge accumulates substantially entirely in the region of the substrate beneath electrode 12~
At time to~ 0 volts is being applied to the next adjacent electrode pair 10-2, 12-2. Accordingly, the asymmetrical potential weIl formerl beneath this electrode pair is reIatively shallower than that beneath the pair 10-1, 12-1. The relatively shallower well at 10-2 creates a potential barrier to the flow, i.n the ~orward direction ~to the right), of charge stored at 18 and to the flow, in the reverse direction (to the left), of khe charge stored under 12-2. (For purpose of generality, even though 0 volts is applied to this electrode, this well is shown to have some finite depth. This also may be taken to represent a fixed but relatively low level of reverse bias applied to the substrate, as discussed in the copending application.) In similar fashion, the asymmetrical potential well beneath electrode pair 10-0, 12-0 (these electrodes are not shown in FIGURE 1) is of the same configuration as the potential weIl beneath 10-2, 12 2. Note that the potential well beneath electrode 12-0 is shallower than the potential well --6~
~,/
5~L8 RCA 6~,936 1 beneath electrode 10-1. This condition is required to insure unidirectional ilow of the charge signal (i.e. the electrons) from left to right.
At -time tl, the voltage ~2 already is positive to the extent of -~10 volts. The voltage ~1 is changing in value from its positive value of ~10 volts to 0 volts. The effect of these voltages i5 to cause a transfer of negative charge to occur as depicted in the middle portion of FIGURE
3. The asymmetrical potential well beneath electrode pair 10-2, 12-2 is at its greatest depth. The asymmetrical potential well beneath electrode pair 10-1, 12-1 is becoming shallower. When the potential well at electrode 12-1 be-comes shallower than the potential well beneath electrode 10-2, the charge stored under the former electrode "spills into" the potential well beneath the latter electrode.
Nowever, at this time the potential well beneath the electrode 12-2 is even deeper than the potential well beneath electrode 10~2 so that charge continues to "run down hill" until it settles into the potential well beneath electrode 12-2.
Under the influence of the self-induced drift field, the thermal diffusion, and the fringing fiel.d, the charge will be transferred, within a matter of nanoseconds, essentially completely from the potential well beneath electrode 12-1 to the potential well beneath electrode 12-2.
Shortly after time tl, all ~of the negative charge formerly stored at electrode 12-1 is stored at electrode lZ-2. Considerably later, at time t2 (last portion of FIGURE 3) the charge remains in the potential well beneath electrode 12 2, as shown. Shortly before time t3, this 3 charge would begin to transfer to the next electrode pair ~ 5~ RCA 64,93~
1 10-3, 12-3.
~ preferred form of electrode structure according to one embodiment of the invention is shown in FIGURE ~.
The method for fabricating this general type of structure is discussed in detail in the copending application although there the insulation employed is on]y a single material Note that here the interface between the thin SiO2 layer and the relatively thicker Si3N~ layer occurs only beneath the aluminum electrodes 12. Accordingly, the positive charge 10 shown, initially may be introduced without the need for ~ -switches such as 14 of FIGURE I. It is necessary only to connect all of the ~1 and ~2 leads together and to a relatively negative voltage source -V and then to disconnect the voltage source and place the circuit in operation in the manner already discussed. (The same holds for the FIGURE 5 and 6 arrangements.) As in the embodiment of FIGURE 1, once the positive charges accumulate at the Si3N4, SiO~ inter-facesj they remain there permanently, provided the positive phase voltages are always maintained considerably smaller than the initial negative priming pulse (by a factor such as 3 or 4) While illustrated as having a p-type substrate, it is to be understood that the arrangement of FIGURE 4 can instead have an n-type silicon substrate. In this case, fixed, negative charges initially may~be stored under the aluminum electrodes by applying a positive voltage level to all electxodes for a short period of time. Also, while the polysilicon electrodes are shown to be of n-type, either p or n-type may be used with either the n-type or the p-type silicon substrate.
RCA 64,936 ~ -:
:: .
1 The operation of the two-phase charge-coupled structure described here relies on fixed storage of diff'erent amounts or dif'ferent polarities of charge in the channel oxide under two ad~acent electrodes powered by the same phase voltage. The preferred way to form such charge-coupled structures is in the form of overlapping electrodes. Such electrodes can be in the form of polysilicon electrodes overlapped by aluminum electrodes as shown in FIGIJRES 4, 5 and ~. However, an alternate way is to use pairs of electrodes both made of polysilicon or of some other re~
fractory material.
While in the embodiment of the invention shown in FIGURE 4 the polarity of the charge is chosen to produce a deeper potential well under one electrode of a pair than under the other, it can instead be chosen to~form a barrier under one electrode of the pair. This will be discussed later in connection with FIGURE 6.
Another ~orm of the present invention is illustrated in FIGURE 5. Here, the substrate is illustrated as being of n-type rather than of p-type and the insulation includes a relatively thick (l000 A - 2000 A) layer of aluminum oxide (Al203) between the aluminum electrodes and the substrate and between the aluminum and polysilicon electrodes. The charge stored in the Alz03 beneath the aluminum electrodes 25 is negative and results in deeper potential wells (more '-negative surface potential) at the substrate locations beneath the stored charges than at the substrate locations beneath the polysilicon electrodes. The intentionally introduced layer (about 40 A9 thick) of SiO2 used in the construction of the MNOS structures, as shown in FIGURE 4, RCA 64,936 .5~3 1 is not really necessary when using aluminum oxide. With the latter, the permanent storage of a negative charge may be accomplished as described, ~or example, in S. Nakanuma et al, "A Read-Only Memory Using ~AS Transistors", Digest of Technical Papers, 1970 International Solid State Circuit Con~erence, Philadelphia, Pa., pp. ~8~69.
As other alternati~es, the aluminum oxide of FIGURE 5 may be of the type ~ormed by pyrohydrolysis o~
AlC13 (S.K. Tung and R.~. Ca~fney, Trans. Met. Soc. AIME, 233, 572 [1968]) or o~ the type ~ormed by reduction o~
Al-isopropoxide (M.T. Duf~y and ~. Revesz, J. Electrochemical Soc. 117, 372 [1969]). In both of these cases, the A1203 can be prepared with a fixed negative charge already "naturally" stored therein. This means that two~phase charge-coupled structures made in these ways can be operated without the need for an initial positive priming voltage to be applied to the electrodes under which it is desired that the negative charge be stored. However, even in these cases, if the aluminum oxide initially is made without a su~icient amount of the negative charge ~or the present purposes, the additional negative charge needed can be introduced by the means already discussed (the application o~ positive voltage level ~or a given time intervalj and discussed also -;~
in another context in the ~. Nakanuma et al article.
In the operation o~ the FIGURE 5 circuit, rather than employing multiple phase voltages which extend from 0 to ~10 volts, they instead have a value ~rom 0 volts to some negative voltage such as -10 volts. The phase relation-ship between the ~1 and ~2 voltages is analagous to that ~ FIGUR~ 2 and is as shown in FIGURF 13 in the copending - RCA 64,936 .3~
1 application mentioned above. The minority carriers which accumulate in the FIGURE 5 circuits, of course, are holes rather than electrons.
Since it is normally simple to store only the negative charge in the pyrolytic aluminum oxide, the type of substrate employed determines whether (a) deep wells or (b) barriers are created. In the FIGURE 5 structure, the substrate is of n-type so deep wells are produced, as already discussed. In the FIGURE 6 structure, the substrate is p-type so that the negative charges in the A1203 beneath the alùminum electrodes create potential barriers to the flow of charge. This structure can be made to provide exceptionally good performance if there is a relatively narrow separation between the~polysilicon electrodes, for example, 3 micro-meters (~m) as shown in FIGURE 6.
The operation of the two-phase charge-coupled shift registers using charge stored in the aluminùm oxide to form ~ ;
: .
energy barriers for the signal charge can be similar to the ~ operation illustrated in FIGURE 3, provided that an appropriate d--c bias voltage is applied to the electrodes to compensate for the induced energy ~arriers. Operation in this way is illustrated in FIGURES 7a and 7b. FIGURE 7a shows the potential wells created in the absence of ~1 and ~2 voltages.
FIGURE 7b illustrates the case where ~2 goes negative while ~1 remains as in FIGURE 7a. Another mode of operation is also possible, as shbwn in FIGURE 7c. Here, the maximum value of the phase voltages is such that finite potential barriers always exit beneath the permanent negatively charged regions, which prevent the complete RCA 64,936 ~.~}I.D~
1 transfer of charge between two potential wells. Such operation, in which the charge stored at each potential well is made to be comparable with the signal charge, is desirable for minimizing the effect of charge trapping at the silicon, aluminum-o~ide interface. ThiS type of opera-tion is possible for the FIGURE 6 structure or for a struc-ture (not shown) havlng a p-type substrate, SiO2 under the aluminum electrodes and A1203 under the polysilicon electrodes and with reIatively large negative charges stored in the ,, A1203 beneath the polysilicon electrodes.
In the embodiments of the invention discussed above, charge'is permanently stored in the insulation beneath one'of the eIectrodes of each'pair and no charge is stored ' in the insulation beneath the other electrode. It is to be understood, of course, that other forms of the invention are -possible. For example, negative~charge may be stored in the ;
insulation under one electrode of each pair and positLve charge in the insulation under another or different amounts of charge, one can be but need not necessarily be zero, may be stored in the insulation under the two electrodes of a pair. What is important in each case is that there be a ,;~
different charge ~either in amount or sign3 stored in the insulation beneath one eIectrode of each pair than in the ;
insulation beneath the other to provide the required asymmetry to the potent~al well formed in the substrate. It is also to be understood that while two examples of materials which may be employed for the insulation means that are given, there are'others which'are possible and which are within the scope of the present invention.
, .- ..
D(~\ 6 a, q36 1 The layout of electrodes (plan view), in the circuits described here may be similar to that described in the copending application For example, a two dimensional array operating as a shift register may have a configuration similar to that of FIGURES 17-19 o~ the copending application.
The present invention also may be used in other applications such as in light sensing arrays, memories and so on. In these various arrangements, each signal channel comprises a relatively thin SiO2 or other insulating film located between thicker insulating ~ilm regions. The present in-vention also is useful in charge-coupled structures in which the channel regions comprise relatively weakly doped sub-strate regions located between relatively strongly doped substrate regions as described recently b~ Bell Telephone La~oratories.
Claims (6)
1. In a two phase operated charge-coupled circuit, which includes a substrate formed of semiconductor material, insulating means on one surface of the substrate, and a pair of adjacent electrodes on said insulating means, both electrically coupled to said substrate and both conductively connected to one another and driven by the same voltage during charge-coupled operation means for creating beneath said pair of adjacent electrodes an asymmetrical potential well characterized in comprising insulating means storing a fixed charge beneath one electrode of the pair which is different than that in the insulating means beneath the other electrode of the pair.
2. In a two phase charge-coupled circuit as set forth in Claim 1, said insulating means comprising a relatively thin silicon dioxide layer and a relatively thick silicon nitride layer, both beneath at least one electrode of said pair, said silicon dioxide layer being located on the substrate between said silicon nitride layer and said substrate.
3. In a two phase charge-coupled circuit as set forth in Claim 1, said insulating means comprising only an aluminum oxide layer beneath one electrode of said pair and said substrate and only a silicon dioxide layer between the other electrode of said pair and said substrate.
RCA 64,936
RCA 64,936
4. A two phase operated charge-coupled circuit, which includes a substrate formed of a semiconductor material, and a pair of adjacent electrodes located over one surface of said substrate and electrically coupled thereto, said electrodes directly connected to one another and driven by the same voltage during charge-coupled opera-tion, said circuit characterized in that it further includes:
first insulating means storing a fixed charge located between one of said electrodes and the substrate and serving to insulate said one electrode from said substrate; and second insulating means of another type and storing substantially no charge located between the other of said electrodes and the substrate and serving to insulate said other electrode from said substrate.
first insulating means storing a fixed charge located between one of said electrodes and the substrate and serving to insulate said one electrode from said substrate; and second insulating means of another type and storing substantially no charge located between the other of said electrodes and the substrate and serving to insulate said other electrode from said substrate.
5. In a two phase operated charger-coupled circuit as set forth in Claim 4, said first insulating means comprising a relatively thin silicon dioxide layer beneath a relatively thick silicon nitride layer, the former layer lying on the surface of the substrate and the latter between the silicon dioxide layer and said one electrode and said second insulating means comprising a relatively thick layer of silicon dioxide.
6. In a two phase charge-coupled circuit as set forth in Claim 4, said first insulating means comprising a layer of aluminum oxide and said second insulating means comprising a layer of silicon dioxide.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17315271A | 1971-08-19 | 1971-08-19 | |
| US173,152 | 1971-08-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1101548A true CA1101548A (en) | 1981-05-19 |
Family
ID=22630755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA149,504A Expired CA1101548A (en) | 1971-08-19 | 1972-08-15 | Two phase charge coupled devices employing fixed charge for creating asymmetrical potential wells |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5123865B2 (en) |
| CA (1) | CA1101548A (en) |
| DE (1) | DE2240249C3 (en) |
| FR (1) | FR2149568B1 (en) |
| GB (1) | GB1395558A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4875176A (en) * | 1972-01-12 | 1973-10-09 | ||
| DE2351393C3 (en) * | 1973-10-12 | 1978-06-22 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Charge transfer device in two-phase technology and process for its manufacture |
| JPS5815271A (en) * | 1981-07-21 | 1983-01-28 | Nec Corp | Charge coupled element |
-
1972
- 1972-08-15 CA CA149,504A patent/CA1101548A/en not_active Expired
- 1972-08-16 GB GB3817172A patent/GB1395558A/en not_active Expired
- 1972-08-16 DE DE19722240249 patent/DE2240249C3/en not_active Expired
- 1972-08-18 JP JP8273272A patent/JPS5123865B2/ja not_active Expired
- 1972-08-18 FR FR7229680A patent/FR2149568B1/fr not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS4830879A (en) | 1973-04-23 |
| FR2149568B1 (en) | 1976-10-29 |
| DE2240249A1 (en) | 1973-02-22 |
| JPS5123865B2 (en) | 1976-07-20 |
| DE2240249C3 (en) | 1975-05-07 |
| DE2240249B2 (en) | 1974-05-22 |
| FR2149568A1 (en) | 1973-03-30 |
| GB1395558A (en) | 1975-05-29 |
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