JP2977983B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a photoelectric conversion element and a charge transfer path in a semiconductor substrate.

[0002]

2. Description of the Related Art The present inventors have already proposed a solid-state imaging device called a domino type. FIG. 9 shows a solid-state imaging device having this configuration.

In FIG. 9, a large number of photodiodes P are arranged in a matrix in an imaging section. For example, P11
Denotes a photodiode in a first row and a first column, and P12 denotes a photodiode in a first row and a second column. A vertical charge transfer path (VCCD) is arranged corresponding to each column of the photodiodes.

[0004] The VCCD 1 has a first column P of photodiodes.
, P21, P31,... And are coupled to each photodiode Pi1 by a transfer gate Tg. The electric charge accumulated in each photodiode Pij is shifted to the VCCD via the transfer gate Tg, and is transferred in the vertical direction in the VCCD.

[0005] Two polysilicon electrodes are formed corresponding to each row of the photodiodes. For example, two CCD electrodes G11 and G21 are formed corresponding to the photodiodes P11, P12, P13,... In the first row, and form a VCCD transfer electrode adjacent to these photodiodes.

The charge transfer in the VCCD is performed in units of two rows as described later. Therefore, the VCCD electrodes corresponding to the photodiodes P21, P22, P23,... In the second row are denoted by G31 and G41. To each electrode of the VCCD, four-phase charge transfer signals φ1, φ2, φ3, φ4 are applied with two rows as one unit.

Drive circuits are connected to these VCCD electrodes on both the left and right sides. The drive circuit on the right is M
OS transistors m11, m21, m31, m41, m
A charge transfer signal is supplied to each VCCD electrode via.

The control circuit on the left side of the figure supplies control signals to the respective VCCD electrodes via MOS transistors M11, M21, M31, M41, M12,... And bipolar transistors Q21, Q4 to even-numbered VCCD electrodes.
Control signals are supplied via 1, Q22,. The control signal supplied via the bipolar transistors Q21, Q41,... Is supplied to the VCCD electrode disposed above the transfer gate Tg, and is used to shift the image charge accumulated in each photodiode Pij to the VCCD. .

Further, MOS transistors M11, M2
The control signal supplied through 1,... Supplies an image holding voltage to a region where charge transfer is not performed during charge transfer in the VCCD. That is, a low-level voltage _VL is applied to odd-numbered VCCD electrodes, and a high-level voltage φ is applied to even-numbered VCCD electrodes.
_H is applied. In this way, the VCCD can retain the image charge without causing pixel mixing.

Note that each of the MOS transistors M and m is N
It can be composed of MOS transistors. The shift register SR included in the control circuit on the right side has the pixel matrix 2
This circuit supplies signals S1 and S2 for controlling ON / OFF of the charge transfer signal in units of rows.

A horizontal charge transfer path HCC is provided below the pixel matrix.
D is arranged thereon, and four HCs per row are disposed thereon.
A CD electrode is arranged. Each of these four HCCs
The charge transfer signals α1, α2, α3, α4 are applied to the D electrode.

After irradiating an image to the image pickup unit and accumulating electric charge in each photodiode Pij, the accumulated image signal is shifted to VCCD via a transfer gate Tg.
In the CCD, electric charges are accumulated under even-numbered electrodes. If you try to perform charge transfer in this state,
Pixel mixing occurs.

For this reason, charge transfer is performed sequentially from the side near the HCCD, and after generating empty packets, the charge transfer region is sequentially expanded upward while performing the charge transfer in a manner that does not cause pixel mixing. . Note that this charge transfer method
This is similar to what is called an accordion transfer method.

FIG. 10 is a schematic diagram for explaining the accordion transfer system. FIG. 10A schematically shows a potential distribution formed in the charge transfer path below the CCD. Even-numbered electrodes Ev and odd-numbered electrodes Od are arranged alternately. In the first state, a potential well is formed below each odd-numbered electrode Od, and charges q _a , q _b , and q _c are accumulated in the potential well.

[0015] Next, when increasing the rightmost voltage of the even-numbered electrodes Ev, potential wells are formed, the charge q _a is spread over 2 electrode minutes. Then the rightmost even-numbered electrode O
When the voltage of d is lowered, the potential well in this portion changes to a potential barrier, and the charge q _a once spread over two electrodes is transferred to the right by one electrode.

Next, when the voltage of the second even-numbered electrode Ev from the right is increased, the potential well spreads below it and the electric charge q
_b becomes distributed over two electrodes. Also,
In this case, when the lowest of the right voltage of the even-numbered electrodes Ev, charges q _a potential barrier is formed below it, is pushed out to the right.

[0017] Thereafter, the charge, to form a potential barrier to the left of q _b, if so as to form a potential well on the right, the charge q
_b is sequentially transferred to the right. As described above, instead of transferring all the electric charges at the same time, the electric charge accumulated for every two electrodes of the VCCD can be transferred by expanding the electric charge transfer area while sequentially taking out electric charges from the side having the electric charge sweeping port. it can.

FIG. 10B is a diagram schematically showing such a charge transfer system. In the figure, the charge transfer path is shown in the vertical direction, and the time change is taken in the right direction. FIG. 10B
In, the charge accumulated in the upper half of the charge transfer path is
The case of transferring to the lower half is shown. In the solid-state imaging device shown in FIG. 9, the lower half charge transfer path shown in FIG. 10B is omitted, and the HCCD is arranged at this position.

In the configuration shown in FIG. 9, two charge transfer electrodes are provided for each row of the photodiode matrix, and charge transfer is performed by performing four-phase driving. The present inventors have previously proposed a method in which charge transfer can be basically performed by one control signal for each row of a pixel matrix. FIG. 11 shows a conceptual diagram of this solid-state imaging device.

The photodiode Pij is the same as the photodiode Pij shown in FIG. 9, and the transfer gate Tg and the vertical charge transfer path VCCD connected to these photodiodes Pij are also the same as those in FIG.

On the vertical charge transfer path VCCD, one VCCD electrode E is provided for each row of the photodiodes Pij.
1, E2, E3,... Are arranged. These VCC
The D electrodes E1, E2,...
.phi.2 is applied via switches SW1, SW2,.

These switches SW1, SW2,...
ON / OFF is controlled by the scanning signal S. In each charge transfer path, a set of built-in potential barriers and potential wells are formed for each row to prevent charge mixing. Therefore, the vertical charge transfer path VC
Even when the accumulated charges are shifted to the CD, no mixing of these charges occurs.

On the left side of the pixel matrix, a potential holding circuit RT is arranged, and a charge holding potential _VL is applied via transistors T1, T2, T3,. Although a circuit for supplying a charge shift signal is not shown, if a charge shift signal is supplied to each VCCD electrode by a circuit similar to that of FIG. 9, the transfer gate T
g, the charge can be shifted to the vertical charge transfer path VCCD.

FIG. 11 shows the state of the vertical charge transfer path VCCD in a state where charges are shifted from each photodiode Pij.
This is schematically shown in (B). In the upper part of the figure, the VCCD electrode E1,
E2, E3,..., And a vertical charge transfer path VCC
1 schematically shows the electron energy in D.

A built-in impurity concentration distribution is formed in the VCCD, and one set of a potential well W and a potential barrier B due to a difference in built-in potential is formed for each electrode.
Charges Q1, Q shifted from photodiode Pij
Are stored in potential wells below each VCCD electrode.

After the charge shift, when the potential of the horizontal charge transfer path HCCD is increased, the electron energy thereunder drops, and
The potential barrier between the CCD electrode E1 disappears. Therefore, the charge Q1 stored in the potential well W1 is
D. Thereafter, when the potential of the HCCD is returned to the original state, the potential barrier is restored on the right side of the potential well W1.

After the empty packet is formed under the VCCD electrode E1, when the potential of the VCCD electrode E1 is raised, the electron energy thereunder drops and the potential barrier Q1 disappears.
Then, the charge Q2 stored in the potential well W2 is transferred to the potential well W1. Thereafter, when the potential of the VCCD electrode E1 is restored, the potential barrier B1 is restored with the charge Q2 accumulated in the potential well W1.

After the empty packet is formed in the potential well W2 in this way, when the potentials of the HCCD and the VCCD electrode E2 are increased, the charge Q2 of the potential well W1 is transferred to the HCCD, and the charge Q3 of the potential well W3 is changed to the potential. The well is shifted to W2.

Similarly, in the next cycle, charges Q4 and Q3 can be simultaneously transferred. Thus, in the solid-state imaging device shown in FIG. 11, charge transfer can be performed by two-phase driving.

FIG. 12 is a diagram for explaining the operation of the solid-state imaging device of FIG. 11 in more detail. When an impurity concentration distribution is formed in the vertical charge transfer path VCCD, different channel potentials are formed in a region where the impurity concentration is high and a region where the impurity concentration is low, as shown in FIG. In the figure,
The vertical direction indicates the channel potential (the upward direction corresponds to the electron energy), and the horizontal direction indicates the depth from the semiconductor surface into the semiconductor substrate.

When a high voltage (H) during charge shift is applied to the VCCD electrode, the channel potential generated at the potential well and V _WH and the channel potential V _BH generated at the potential barrier are shown. At this time, a channel potential V _TG is generated at the transfer gate.

FIG. 12B shows the distribution of the channel potential in the direction along the VCCD. In this figure, two VCCD electrodes are formed for each row of photodiodes and the same potential is applied to two electrodes corresponding to each row because of a manufacturing process for forming a difference in channel potential. The configuration is shown.

By changing the thickness of the insulating film below the electrodes, the influence when the same potential is applied can be made different. In this case, a difference in channel potential is formed by a difference in impurity concentration and a difference in influence from the electrode. When a high voltage is applied during the charge shift, VC
The channel potential in the CD is as shown by the solid line.

The channel potential of the transfer gate at this time is indicated by a broken line. In such a state, the charge stored in each photodiode is shifted to a potential well in the VCCD via the transfer gate.

[0035]

When the charge shifts from the photodiode to the charge transfer path, a high voltage is applied to the electrodes of the charge transfer column in order to eliminate the potential barrier of the transfer gate. At this time, 1 for each row of the pixel matrix
In a configuration with two electrodes, the channel potential of the potential barrier in the charge transfer path also increases, and the charge shifted from the photodiode that has accumulated a large amount of charge to the charge transfer path may overflow to the adjacent electrode part. Occurs.

FIG. 12C schematically shows this state.
When a high potential is applied to the VCCD electrode, the transfer gate Tg and the channel potential of the VCCD increase (electron energy decreases), and the photodiode Pij
The charge accumulated in the transfer gate is transferred to VCC
Flow out to D. At this time, since the electron energy of the potential barrier portion B of the VCCD is also low, the photodiode Pi
A part of the electric charge flowing out of j is the potential barrier portion B of the VCCD.
, And overflow to the adjacent pixel portion. In this way, charge mixing occurs.

An object of the present invention is to provide a solid-state image pickup device having a photodiode and a charge transfer path, capable of driving the charge transfer path in two phases, with a configuration in which overflow does not easily occur when a charge shifts from the photodiode to the charge transfer path. To provide a solid-state imaging device having the same.

Another object of the present invention is to provide a driving method in such a solid-state imaging device that does not cause charge mixing during charge shift.

[0039]

According to the present invention, there is provided a method for driving a solid-state image pickup device, wherein electric charges accumulated in a photoelectric conversion element array including a plurality of photoelectric conversion elements are arranged adjacent to the photoelectric conversion element array. A method for driving a solid-state imaging device, which shifts to a charge transfer column having one storage unit and one barrier unit per photoelectric conversion element, and sequentially transfers signal charges in the charge transfer column to read out signal charges. A deep potential well is formed in the storage section while applying a different potential to the storage section and the barrier section adjacent to the photoelectric conversion element in the transfer column and forming a high potential barrier in the barrier section between the adjacent storage sections. Shifting the electric charge from the photoelectric conversion element to the storage unit, and simultaneously controlling the potential of one of the barrier units adjacent to the storage unit of the electric charge transfer column with the same signal. In a step of transferring charges.

The solid-state imaging device according to the present invention further comprises a photoelectric conversion element array including a large number of photoelectric conversion elements, a charge transfer path arranged adjacent to the photoelectric conversion element array, A charge transfer column including a first set of insulating electrodes disposed at a position corresponding to the photoelectric conversion element and a second set of insulating electrodes disposed between adjacent first sets of insulating electrodes; A charge shift circuit for applying a shift signal for shifting charges from the element array to the charge transfer path to the first set of insulating electrodes; and a plurality of potential barriers in the charge transfer path during the application of the shift signal. And a potential barrier holding circuit for applying a predetermined bias voltage to the second set of insulating electrodes, and a second set of ones adjacent to the first set of insulating electrodes corresponding to each photoelectric conversion element. The same voltage signal is simultaneously applied to the pair of insulated electrodes. Etsutsu, and a driving circuit for transferring the charge in the charge transfer path.

[0041]

When a charge is shifted from a row of photoelectric conversion elements to a charge transfer path, a barrier portion that forms a high potential barrier is left between storage portions where the charge is to be accumulated, so that charge mixing occurs. Is prevented.

[0042]

FIG. 1 is a plan view schematically showing a solid-state imaging device according to an embodiment of the present invention. In the imaging unit, a large number of photodiodes Pij are arranged in a matrix.

A vertical charge transfer path VCCD is formed corresponding to each column of the pixel matrix. For example, a vertical charge transfer path VCCD1 is formed on the right side of the photodiodes P11, P21, P31,... In the first column, and is connected to each photodiode by a transfer gate Tg. One horizontal charge transfer path H is provided at the lower end of each vertical charge transfer path VCCD.
CCD is coupled.

On the vertical charge transfer path VCCD, two VCCD electrodes G11, G21, G per row of the pixel matrix are provided.
31, G41, G12, G22,...
These VCCD electrodes are connected to control circuits on the right and left sides in the figure, respectively.

On the right side of the figure, the VCCD electrode G1
1, G21, G31, G41, G12,... Are NMOS
Are connected to the phase signals φ1 and φ2 via transistors m11, m21, m31, m12,... The gates of the transistors m11, m21,... Form a set of two rows, and the scanning signals S1, S2,.
Has been given.

The phase signal φ1 is supplied to the VCCD of G11, G41, G12, G42,.
The phase signal φ2 is applied to the VCCD electrodes G21, G31, G22, G32,... Via the transistor m. Also, each VCCD electrode G11, G
.. Are indicated by φ11, φ21,.

On the left side of the figure, each VCCD electrode is N
MOS transistors M11, M21, and is connected to ... signal source V _L or phi _H through. The even-numbered electrodes are connected to the charge shift voltage V _S via bipolar transistors Q21, Q41,.

A horizontal charge transfer path HC is provided at the lower end of the VCCD.
A CD is arranged on which four electrodes are formed for each column. These electrodes are alternately connected to the phase signals α1 and α2 two by two.

In each charge transfer path, a storage section ST and a barrier section B having different channel potentials are formed by the same control voltage. A description will be given taking a pixel portion as an example.

FIG. 2 schematically shows the structure of the pixel portion.
FIG. 2A shows a planar configuration, and FIG. 2B shows a channel potential. In FIG. 2A, a transfer gate Tg is formed adjacent to the photodiode Pij, and a vertical charge transfer path VCCD is formed on the opposite side of the transfer gate Tg.

The portion adjacent to the transfer gate Tg of the VCCD is a storage portion S having a high channel potential.
T, and a barrier portion B having a low channel potential is formed between the storage portions. The storage section ST and the barrier section B have at least different impurity concentrations. Further, the difference in channel potential can be increased by changing the insulating film thickness of the insulating electrode formed on the VCCD.

FIG. 2B shows a change in channel potential due to a gate voltage. Since the storage section ST and the barrier section have at least different impurity concentrations, they exhibit different channel potentials for the same gate voltage.

The channel potential of the storage unit ST is higher than the channel potential of the barrier unit B, and provides a stable state for electrons. In the figure, the channel potential of the transfer gate portion Tg is also shown.

The channel potential of the transfer gate portion Tg is lower than the channel potential of the barrier portion B. As the gate voltage is applied in the negative voltage direction, the channel potentials of the storage section ST and the barrier section B both become constant at a predetermined gate voltage. This critical value is called a pinning voltage.

Control voltage (low voltage) V for holding electric charge
_L takes a negative voltage greater than the pinning voltage, the middle voltage V _M taken intermediate state (e.g., ground potential), a high voltage (high voltage) V _H for charge shift takes a positive voltage of a predetermined value or more.

It should be noted here, the channel potential V _BM of the barrier section B in the middle voltage V _M, high select than the channel potential V _SL of the storage unit ST at the low voltage V _L, the barrier section B in V _H Channel potential V _BH
High select than the channel potential V _SM of the storage unit ST in the middle voltage V _M is.

The high voltage V_HTransfer game in
Channel potential V _TGIs V_SLAnd V_BHof
Take in the middle. Setting of such channel potential
Is the impurity concentration in the semiconductor substrate, the insulating film on the semiconductor substrate
Can be variously selected according to the thickness of the electrode, electrode material, etc.
You.

According to the configuration of FIG. 1, separate electrodes are formed on the storage section ST and the barrier section B of the VCCD, and independent control voltages can be applied to the respective electrodes. Charge mixing during shifting can be prevented.

The operation of the field shift will be described with reference to FIG. FIG. 3A shows the channel potential at the time of the field shift. The horizontal axis indicates the depth from the semiconductor surface, and the vertical axis indicates the channel potential.

Since a high-level control voltage is applied to the storage unit ST, the channel potential V _SH becomes sufficiently high, and the channel potential V _TG of the transfer gate unit is sufficiently lowered to shift charges from the photodiode to the storage unit. it can. At this time, a low-level voltage _VL is applied to the barrier section of the VCCD. Therefore, the channel potential V _BL of the barrier section can be kept higher than the channel potential of the transfer gate section as shown in the figure.

FIG. 3B shows the distribution of the channel potential in the direction along the VCCD. The solid line shows the distribution of the channel potential in the VCCD, and the broken line shows the channel potential of the transfer gate section.

In this state, the charge flows from the transfer gate portion Tg into the storage portion ST of the VCCD. However, the channel potential of the barrier portion B is higher than the channel potential of the transfer gate portion in the drawing. It is possible to prevent the charge from overflowing to the adjacent pixel.

FIG. 3C shows that the photodiode P
A state when charges are shifted to the storage unit ST of the CD is schematically shown. Since a sufficiently high potential barrier is formed on both sides of the charge path, the charge that shifts from the photodiode P to the storage unit ST rarely overflows the potential barrier and overflows to an adjacent pixel.

Next, referring to FIG. 4, low-level voltage V
_A charge transfer path that takes _L in a pinning state will be described. FIG.
(A) schematically shows the configuration of the charge transfer path and its channel potential Vm. Electron energy is reversed.

As shown on the right side of the figure, the VCCD as a charge transfer path is formed on the surface of a p-type semiconductor substrate 14, for example.
It is configured by forming an n-type charge transfer path. The charge transfer path includes n ⁺ -type well portions 15 and n ⁻ -type barrier portions 16 alternately.

Above the charge transfer paths, gate electrodes 17 and 18 made of polycrystalline silicon or the like are arranged via an insulating film. In the configuration shown in the figure, a gate electrode 17 made of first polysilicon is arranged above the well portion 15, and a gate electrode 18 made of second polysilicon is arranged above the barrier portion 16.

Here, the gate oxide film 19 disposed on the well portion 15 is selected to be thinner than the gate oxide film 20 disposed on the barrier portion 16. That is, the gate electrode 17 on the well 15 and the barrier 1
When a voltage of the same potential is applied to the gate electrode 18 above the gate electrode 6, the well portion 15 is more affected by the gate voltage than the barrier portion 16 because the gate oxide film 19 is thinner than the gate oxide film 20.

When the gate voltage Vg applied to the gate electrodes 17 and 18 is changed, the channel potential Vm in the charge transfer path changes as shown in the left graph in FIG.
In the graph of FIG. 4A, the vertical axis indicates the electron energy with respect to the electrons, and the horizontal axis indicates the gate voltage.
The electron energy is a stable low electron energy on the lower side.
Since it is for electrons, applying a positive gate voltage lowers the electron energy.

The channel potential Vm (15) of the well portion 15 in the n ⁺ type region is in a state where electron energy for electrons is lower than the channel potential Vm (16) of the barrier portion 16 in the n ⁻ type region. When the charge transfer path is in the depletion state, changing the gate voltage Vg also changes the channel potential.

However, when the gate voltage Vg is increased in the reverse bias direction, an inversion state occurs in the charge transfer path at a reverse bias deeper than a certain value, and the channel potential Vm takes a constant value. The gate voltage at which the channel potential does not change is defined as the pinning voltage Vgp.
Call.

Since the well portion 15 and the barrier portion 16 have different impurity concentrations, if the gate oxide films 19 and 20 have the same thickness, the gate pinning voltage and the associated pinning potential also differ. When the gate voltage Vg is the low level voltage _VL , the potential of the well 15 is
If the potential of 6 is also selected to be in the pinning state,
The electron energy of the well portion 15 is surrounded by a potential barrier due to a difference in pinning potential to form a potential well.

In the configuration shown in FIG.
6 is selected to be thicker than the gate oxide film 19 on the well 15, a reverse bias voltage deeper than originally required is applied to the gate electrode 18 on the barrier 16. The pinning state is realized only when the voltage is applied.

Adjusting the difference in thickness between gate oxide films 19 and 20
As a result, the well portion 15 and the barrier portion 16 are pinned.
The gate voltages that enter the switching state can be the same. C
Gate pinning voltage for well 15 and barrier 16
Are the same, so that the well portion 15
And the low-level gate electrode V applied to the barrier section 16 _L
Is expanded. Therefore, the tolerance of the driving voltage is expanded.
Will be great.

A barrier adjacent to the well portion 15 for holding electric charges
One of the rear part 16 has a middle level V_MGate voltage
When applied, the electron energy of the barrier section 16 becomes low level.
Le V _LLower than the electron energy of the well portion 15 of
The charge can be transferred.

In order to hold the charge in the pinning state, it is necessary that the well portion 15 and the barrier portion 16 have sufficiently different pinning potentials. In the above configuration, the impurity concentration of the charge transfer path is changed. This was achieved. In addition to the impurity concentration, the pinning potential can be changed by changing the depth of the pn junction or the like. Gate pinning voltage Vg
Adjustment of p can be performed by selecting a gate oxide film, a gate electrode material, a junction depth, and the like.

FIG. 4B schematically shows a change in dark current due to a change in gate voltage. In the figure, the horizontal axis is the gate voltage V
g, and the vertical axis indicates the dark current _ID . As the gate voltage is changed from a reverse bias to a forward bias, the embedded charge transfer path takes an inversion state, a depletion state, and an accumulation state.

In the inversion state and the accumulation state, the charge generation center on the semiconductor surface is occupied by free charge carriers, so that the dark current _ID is significantly reduced. Therefore, the dark current _ID changes depending on the gate voltage as shown in the figure. By maintaining the gate voltage Vg at or below the pinning voltage Vgp (deep reverse bias), if an inversion state occurs on the semiconductor surface, the dark current _ID can be reduced.

FIG. 4C shows the electron energy distribution in the depth direction of the semiconductor substrate. In the p-type region, the electron energy of the conduction band cb and the electron energy of the valence band vb have constant values, and holes 41 exist in the valence band vb. In the n-type region forming the charge transfer path, the electron energy is reduced by the built-in potential of the pn junction, the electron energy on the semiconductor surface is lifted by the gate voltage, and a potential well is formed therein. Electrons 42 are accumulated in this potential well.

Further, since the gate voltage is reverse-biased sufficiently deep, an inversion state occurs on the semiconductor surface, and holes 43 are generated on the surface portion. The holes occupy the charge generation center on the semiconductor surface, and significantly reduce the influence thereof. For this reason, generation of electron-hole pairs on the semiconductor surface is prevented, and a change in accumulated charge due to dark current is prevented.

In the accordion type charge transfer shown in FIG. 10, the time until the transfer of the charge is different depending on the position in the charge transfer path. Since the dark current increases with time, if the dark current is large, the distribution of signal charges changes. However, according to the above-described configuration, even if the accumulated charge is held for different times in the charge transfer path, the dark current is significantly reduced, so that the change in the accumulated charge is reduced.

In this manner, fixed pattern noise in the domino type solid-state image pickup device, flicker in the FIT pseudo frame electronic shutter type solid-state image pickup device and the like are reduced.

FIG. 5 is a timing chart of control signals when operating the solid-state imaging device shown in FIG. In the figure, the horizontal axis represents the time axis, and the vertical axis represents the potential of various signals.

Predetermined time t during vertical blanking period _TVB
2, the field shift signal φ _FS goes high, and the bipolar transistors Q21 and Q4 shown in FIG.
Are turned on, and voltages φ21, φ41, φ22,... Of the even-numbered VCCD electrodes arranged on the transfer gate are turned on.
… Goes high.

At this time, the voltages φ11, φ31,... Applied to the odd-numbered VCCD electrodes are V _L supplied via the MOS transistors M11, M31,. Therefore, the field shift (charge shift) as described with reference to FIG. 3 is performed.

Thereafter, when the set of four VCCD electrodes is considered, the same voltage is applied to the second and third electrodes, and the same voltage is applied to the first and fourth electrodes. Can be In the first horizontal blanking period T _HB, charge transfer signal only to the first set of VCCD electrode is supplied, in the second th horizontal blanking period T _HB,
A charge transfer signal is applied to the first set and the second set of VCCD electrodes. In this way, the area to which the charge transfer signal is sequentially applied is enlarged.

In the signal configuration of FIG. 5, time t9 and time t9
Horizontal blanking period T between 10 _HBIn the n-th
Charge transfer signal to be supplied to the set of VCCD electrodes
Become. The area for giving such a charge transfer signal is gradually expanded.
Are performed by the scanning signals S1, S2,.
You.

FIG. 6 is an enlarged view of such a charge transfer signal.
Shown. Each horizontal blanking period T _HBIn the two-phase drive
Is performed once and the charge transfer signal is
The charges are transferred to the one row HCCD side.

As described above, charge transfer in the VCCD is performed by two-phase driving in which the same voltage is applied to two adjacent electrodes. For this reason, the charge transfer control circuit is simplified. It is obvious that the same two-phase driving is possible in the HCCD.

FIG. 7A shows a step of forming a transfer channel serving as a barrier region. An SiO ₂ layer 23 is formed on the surface of the p-type silicon region 21 and an n-type impurity is ion-implanted. The ion-implanted n-type impurity forms an n ⁻ -type region 22 on the surface of the p-type silicon region 21. This n
^The mold region 22 will form the barrier region.

[0090] Next, as shown in FIG. 7 (B), SiO ₂
A one-poly gate 24 is formed by forming a polycrystalline silicon (poly Si) layer on the layer 23 and patterning the same. Next, using this one-poly gate 24 as a mask, anisotropic etching of the SiO ₂ layer 23 is performed, followed by ion implantation of an n-type impurity.

In the anisotropic etching, the exposed S
A part of the iO ₂ layer 23 is removed by etching. The depth of the SiO ₂ layer 23 to be removed by etching is selected so that when a gate voltage is formed thereon, the well region W and the barrier region B enter the pinning state at the same gate voltage.

Following such anisotropic etching, an n-type impurity is ion-implanted using the same one poly gate 24 as a mask to increase the impurity concentration of the ion-implanted charge transfer path.

Alternatively, the SiO ₂ layer 23 in the area exposed by the anisotropic etching is once removed entirely, and a new SiO ₂ layer having a desired thickness is newly formed. Thereafter, ion implantation similar to that described above is performed.

The n-type impurity does not reach below the 1-poly gate 24, and the n-type impurity is ion-implanted only into the region without the 1-poly gate 24 to form the n-type region 25. Since the n-type region 25 has a higher n-type impurity concentration than the n ⁻ -type region 22, the electron energy with respect to the electrons is reduced to form a well region. Since the formation of the region 25 is self-aligned with the 1-poly gate 24, the position accuracy is high.

Next, as shown in FIG. 7C, the surface of the one poly gate 24 is oxidized to form an oxide film 30, on which polycrystalline silicon (poly Si) is deposited and patterned. A two-poly gate 26 is formed. This 2
Poly gate 26 is automatically aligned with n-type region 25 serving as a well region.

Since the two-poly gate 26 is disposed on the gate oxide film thinned by the anisotropic etching in the step of FIG. 7B, the influence on the charge transfer path is stronger than that of the one-poly gate 24.

In this manner, two electrodes per row are formed by the pair of the poly gate 24 and the poly gate 26. After that, an Al wiring or the like is formed, and each poly gate is connected to a drive circuit.

When the same voltage is applied to the adjacent one-poly gate 24 and two-poly gate 26, the barrier region 22 and the well region 25 have different impurity concentrations in the transfer channel region, and thus have different electron energies for electrons. Thus, a potential barrier and a potential well for electrons can be formed.

FIG. 7D shows that the barrier portion is formed of an n-type region having a surface impurity concentration of 1.0 × 10 ¹⁷ cm ⁻³ and a junction depth of 0.4 μm, and the well portion further has a surface impurity concentration of 5 × 10 ¹⁷ cm ⁻³ . 10
Vg− when ¹⁶ cm ⁻³ and 0.8 μm depth are formed in layers
Vm characteristics are shown. Note that the thickness of the gate oxide film is
The broken line shows the characteristics of the well portion when the angle is set to 00 °. The horizontal axis shows the gate voltage Vg, and the vertical axis shows the channel potential Vm. Since the potential is shown with respect to the positive charge, the electron energy of the electrons is lower on the upper side.

The channel potential in the pinning state has a potential difference set by a difference in impurity concentration or the like. When the gate oxide film has a uniform thickness, the gate voltage Vgp that enters the pinning state is different between the barrier portion and the well portion. However, since the thickness of the gate oxide film on the well region is reduced, the channel potential of the well region changes from the state shown by the broken line to the state shown by the solid line.

By adjusting the thickness of the gate oxide film, it is possible to make the gate pinning voltage Vgp for the well region equal to the gate pinning electrode Vgp for the barrier region as shown by the solid line.

FIG. 8 shows another construction of the VCCD. FIG.
In this method, ion implantation of an n-type impurity was performed twice. In this method, ion implantation of an n-type impurity and ion implantation of a p-type impurity are used.

First, as shown in FIG.
The surfaces of the regions 21, to form a SiO ₂ layer 23, SiO ₂
An n-type impurity is ion-implanted through the layer 23. An n-type region 27 is formed by ion implantation of an n-type impurity. This n-type region 27 forms a well region of the transfer channel.

[0104] Next, as shown in FIG. 8 (B), SiO ₂
On the layer 23, a polycrystalline silicon layer is formed and patterned to form a one-poly gate 28. Next, using this one-poly gate 28 as a mask, a p-type impurity is ion-implanted.

In the region where one poly gate 28 exists, p
The type impurity is not ion-implanted, and the p-type impurity is ion-implanted only in a region where the 1-poly gate 28 does not exist and the SiO ₂ layer 23 is exposed. In this manner, in the region into which the p-type impurity has been ion-implanted, the n-type impurity concentration is compensated by the p-type impurity concentration, and the region becomes the n ⁻ -type region 29.

After that, as shown in FIG.
The surface of the gate 28 is oxidized to form SiO _TwoForming a layer 31;
Furthermore, a predetermined thickness of SiO_TwoGrowing the layer by CVD,
Depositing a poly-Si layer on it and patterning it
Therefore, a two-poly gate 32 is formed.

The SiO ₂ layer grown by CVD has the following properties:
It is located above the poly gate 28, but below it for the 2-poly gate 32. Therefore, the two poly gates 32 are separated from the surface of the transfer channel by a longer distance than the one poly gate 28.

In this structure, a well region is formed below one poly gate 28, and a barrier region 29 is formed below two poly gates 32. FIG. 8D is a graph showing the channel potential of the transfer channel formed in the well region W and the barrier region B as a function of the applied gate voltage Vg.

When the thickness of the gate oxide film is the same, since the barrier region B has a low impurity concentration, the barrier region B enters the pinning state by the shallower reverse biased gate voltage Vg as shown by the broken line.

However, in the above-described embodiment, the gate oxide film under the second poly gate 32 is the first poly gate 2
Since the thickness of the gate oxide film is thicker than that of the gate oxide film below 8, the influence of the gate voltage on the transfer channel is reduced, and the characteristic of the broken line is changed to the characteristic of the solid line. By adjusting the thickness difference of the gate oxide film, it is possible to select the well region and the barrier region simultaneously into the pinning state at the same gate voltage.

Note that the effect of the same gate voltage on the transfer channel can be made different by using other means alone or in combination. For example, the influence can be varied by changing the material of the gate electrode, changing the junction depth, changing the material of the gate insulating film, and the like. These means can be used alone or in combination.

Although the present invention has been described in connection with the preferred embodiments,
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0113]

As described above, according to the present invention,
When shifting charges from the photoelectric conversion element to the charge transfer path, charge mixing can be prevented, and charge transfer in the charge transfer path can be performed by two-phase driving.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a solid-state imaging device according to an embodiment of the present invention.

2A and 2B are a plan view and a graph for explaining a pixel unit of the solid-state imaging device in FIG.

3A and 3B are a graph and a conceptual diagram for explaining a field shift of the solid-state imaging device in FIG.

FIG. 4 is a conceptual diagram for explaining pinning of the solid-state imaging device in FIG. 1;

FIG. 5 is a timing chart of control signals for operating the solid-state imaging device shown in FIG. 1;

FIG. 6 is a partially enlarged view of the timing chart of FIG. 5;

FIGS. 7A and 7B are a cross-sectional view and a graph for explaining a method of manufacturing the VCCD of the solid-state imaging device of FIG.

FIG. 8 is a cross-sectional view and a graph for explaining another manufacturing method for manufacturing the VCCD of the solid-state imaging device shown in FIG. 1;

FIG. 9 is a schematic plan view illustrating the configuration of a domino type solid-state imaging device according to a conventional technique.

FIG. 10 is a conceptual diagram for explaining an accordion transfer method.

FIG. 11 is a plan view and a conceptual diagram showing a solid-state imaging device according to the above proposal.

12 is a conceptual diagram for explaining the operation of the solid-state imaging device shown in FIG.

[Explanation of symbols]

 P Photodiode VCCD Vertical charge transfer path HCCD Horizontal charge transfer path Tg Transfer gate section M, m MOS transistor Q Bipolar transistor G VCCD electrode ST Storage section B Barrier section

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Akio Sakota 1-6-6 Matsuzakadaira, Yamato-cho, Kurokawa-gun, Miyagi Fujifilm Microdevices Co., Ltd. In-house (58) Field surveyed (Int. Cl. ⁶ , DB name) H04N 5/30-5/335

Claims (4)

(57) [Claims] An electric charge stored in a photoelectric conversion element array including a plurality of photoelectric conversion elements is arranged adjacent to the photoelectric conversion element array, and one storage unit and one storage unit are provided for each photoelectric conversion element.
A method for driving a solid-state imaging device that shifts into a charge transfer column having two barrier sections and sequentially transfers signal charges in the charge transfer column to read out signal charges, the storage device being adjacent to a photoelectric conversion element in the charge transfer column. A deep potential well is formed in the storage portion while applying a different potential to the portion and the barrier portion to form a high potential barrier in the barrier portion between the adjacent storage portions, and the electric charge is transferred from the photoelectric conversion element to the storage portion. And a step of transferring electric charges by two-phase driving while simultaneously controlling the potential of one of the barrier units adjacent to the storage unit of the charge transfer column with the same signal. 2. The method according to claim 2, wherein the charge transfer column is high in a storage unit.
Low in the barrier portion, having a built-in channel potential distribution, having an insulating electrode on each storage portion and each barrier portion, applying a negative voltage to the electrode on each barrier portion in the shifting step, 2. A positive voltage is applied to an electrode on each storage unit, and in the transfer step, the same transfer pulse is applied to an electrode on each storage unit and an electrode on a barrier unit adjacent in a direction opposite to the transfer direction. Driving method of a solid-state imaging device. 3. A photoelectric conversion element row including a large number of photoelectric conversion elements, a charge transfer path arranged adjacent to the photoelectric conversion element row, and a charge transfer path disposed thereon and at a position corresponding to each photoelectric conversion element. A charge transfer column including a first set of insulated electrodes disposed and a second set of insulated electrodes disposed between adjacent first sets of insulated electrodes; and a charge from the photoelectric conversion element line to a charge transfer path. A charge shift circuit for applying a shift signal for shifting the first set of insulating electrodes to the first set of insulating electrodes; and forming the second potential barrier in the charge transfer path during the application of the shift signal. A potential barrier holding circuit for applying a predetermined bias voltage to a set of insulated electrodes; and a pair of a first set of insulated electrodes adjacent to the first set of insulated electrodes corresponding to each photoelectric conversion element. At the same time, applying the same voltage signal, A solid-state imaging device and a driving circuit for forward. 4. The solid-state imaging device according to claim 3, wherein in the charge transfer path, a region under the first set of insulating electrodes has a higher impurity concentration than a region under the second set of insulating electrodes.