JPH0583636A - Solid-state image pickup device and its driving method - Google Patents

Abstract

PURPOSE:To simplify the constitution of a CCD driving circuit in a solid-state image pickup device using a semiconductor photodiode and a charge coupled device CCD and its driving method. CONSTITUTION:This device is equipped with vertical CCDs 1, 2, and 3 composed of a large number of photoelectric conversion elements D arranged in matrix shape and the vertical CCDs in plural columns arranged corresponding to each column, and capable of controlling one potential well W and one potential barrier B by one driving voltage and composed so as to receive one control voltage phi1, phi2. or VL per one row, and control circuits 8, 9 which generate one control signal per every row of the vertical CCDs in plural columns.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup device, and more particularly to a solid-state image pickup device using a semiconductor photodiode and a charge coupled device (CCD) and a driving method thereof.

[0002]

2. Description of the Related Art As a solid-state image pickup device, a CCD transfer system is known and is used in electronic cameras, copying machines, and other video equipment. A large number of photodiodes are arranged vertically and horizontally to form a pixel matrix. further,
Adjacent to each photodiode array is a vertical charge transfer path (VCC
D) is formed, and a horizontal charge transfer path (HCCD) is formed adjacent to the end of each VCCD.

In recent years, there is a strong demand for high integration of solid-state image pickup devices. In order to realize a high degree of integration, it is desired to increase the number of photodiodes and suppress an increase in semiconductor chip area.

In order to realize a high degree of integration, it is desired to reduce the number of cells of VCCD. For example, a VCCD with two cells per row of photodiodes is used.

In order to read the charges accumulated in the photodiodes by using the VCCD having two cells per row, a method of sequentially reading the charges from the photodiodes in every other row is adopted. In this case, 1 in 2 fields
An image of the frame is formed. In order to improve the vertical resolution, it is desirable to read charges from all the photodiodes at once.

A frame transfer type solid-state image pickup having a light receiving section including a plurality of vertical transfer paths having a photoelectric conversion function and a charge transfer function, and a storage section including a plurality of vertical transfer paths connected to these charge transfer paths. An accordion transfer method has been proposed as a method for reading accumulated charges in a device (PHILIPS TECHNICAL REVIEW).
VOL. 43, No. 1/2, 1986, A.M. J.
P. Theuwissen and C.I. H. L. Weij
tens).

FIG. 8 shows an accordion transfer system.
FIG. 8A is a conceptual diagram showing how the potential under the electrode of the transfer path changes with the passage of time.
FIG. 8B is a conceptual plan view showing how charges move by the accordion transfer method.

In FIG. 8A, the electrodes of the transfer path are classified into odd-numbered electrodes Od and even-numbered electrodes Ev.
A CCD cell is formed under each of these electrodes. First,
The potential under the odd-numbered electrodes is lowered, potential wells are formed, and charges qa, qb, and qc are accumulated.

If the potential barrier disposed between the potential wells is lowered in this state, charge mixing will occur. Therefore, first, the potential under the even-numbered electrode on the rightmost side is lowered to extend the potential well to 2 cells. Then, the electric charge qa is distributed to the right by one cell.

Next, when the potential of the left side portion of the potential well accumulating the charge qa is raised and at the same time the potential of the right potential barrier portion is lowered, the charge qa moves to the right by one cell while being distributed in two cells. Then, a potential barrier for two cells is formed between the charges qa and qb. Thereafter, the potential of the left side portion of the charge qa is sequentially increased and the potential of the right side portion is decreased, so that the charge qa is sequentially transferred to the right side.

Further, when a potential barrier for two cells is generated between the charges qa and qb, the potential qb on the right side of the charge qb is lowered next, so that the charge qb is spread over two cells and distributed. become. At this time, since a potential barrier for two cells exists between the charges qa and qb, charge mixing does not occur. In this way, the charges accumulated every other cell are extended and distributed at a pitch twice as large as the charges, so that the charges can be transferred.

FIG. 8B schematically shows the charge distribution thus transferred. In the figure, the horizontal axis indicates the time change and the vertical axis indicates the cells of the transfer path. In the leftmost state, charges qa, qb, every other cell are charged in the upper half of the transfer path.
qc and qd are accumulated. Among these charges, the charges arranged below are transferred downward while sequentially forming a potential well of 2 cell length and a potential barrier of 2 cell length from the charge arranged on the lower side.

That is, the charge during transfer is 2
A potential barrier for two cells is formed between the charges distributed over the cells and being transferred. In this way, it is possible to transfer charges accumulated every other cell while preventing charge mixing. In the rightmost state where the transfer is completed, the charges qa, qb, qc, and qd are distributed again every other cell.

Since the generation of the potential well and the potential barrier at the time of transfer is similar to the state when the bellows part of the accordion of the musical instrument is gradually widened and then closed again, this charge transfer method is the accordion transfer method. Called.

As seen in the potential diagram of FIG. 8A, the accordion transfer type drive signal may be a two-phase signal.

The applicant of the present invention has proposed a domino transfer method for performing similar charge transfer in a solid-state image pickup device including a photodiode matrix, a vertical charge transfer path and a horizontal charge transfer path. The transfer path of the accordion transfer method is CCD in the domino transfer method. Further, the driving signal is also transferred by four-phase driving similar to the interline CCD.

[0017]

According to the interline transfer system, the charges arranged in every other cell of the CCD are replaced by two charges.
It was transferred by the phase drive signal. However, when transferring
Only one signal could be transferred to two rows of photodiodes.

In a solid-state image pickup device equipped with a photodiode matrix and a VCCD for transferring charges read from the photodiode matrix, a domino transfer system is implemented by arranging one cell per row in the VCCD to implement all pixel signal. Can be read independently at the same time.

However, in order to form the drive signal, four drive signal sources are required for every two rows of photodiodes. When it is attempted to further improve the integration degree of the solid-state image pickup device, the CCD drive circuit comes to limit the integration degree.

An object of the present invention is to provide a solid-state image pickup device having a simple CCD driving circuit.

Another object of the present invention is a CCD having a simple structure.
A method of driving a solid-state imaging device that can be driven by a drive circuit.

[0022]

According to a method of driving a solid-state image pickup device of the present invention, charges accumulated in a large number of photoelectric conversion elements arranged in a matrix are arranged corresponding to each column of the photoelectric conversion elements. Sequentially transferred to the vertical CCDs of multiple columns,
A horizontal CC in which charges in the CD are commonly connected to a vertical CCD
A method for driving a solid-state imaging device, in which charges are sequentially transferred to D, charges in a horizontal CCD are sequentially transferred to read out signal charges, and one potential well and one potential are obtained by applying one voltage to the vertical CCD. Barrier and control the vertical CC
It is characterized in that D is driven in two phases to transfer charges.

Here, the CCD system in which the charges read from the photoelectric conversion element are first transferred is called the vertical direction for convenience.

[0024]

When the charges are transferred by the interline transfer method, one charge is distributed and transferred in two rows of the photodiode during the transfer. In order to separate the charges adjacent to each other, it suffices that there be two potential barriers per two rows.

When one potential well and one potential barrier are controlled by applying one voltage to the vertical CCD, one
The charge transfer can be performed by one control signal per row. In this specification, regardless of whether electrons or holes,
The level of potential is expressed by the expression "level of potential". A low potential for electrons is a high voltage in the positive direction.

For example, one potential well and one per row
When two potential barriers are arranged and charge is transferred from the photodiode to the CCD, the charge is accumulated in each potential well. In this state, for example, if the CCD is in the vertical direction and the potential barrier on the lower side of the potential well in which the lowermost charge is accumulated is controlled to lower the potential, the lowermost charge moves to the lower side. Move one line. Then, a blank for one row is generated between the moved charges and the adjacent charges, and when the control signal is returned to the original state, two potential barriers exist. Similarly, the next charge is transferred down one row.

When there is a blank space for one row between the lowermost charge and the next charge, these charges can be transferred to the lower side at the same time. At this time, even if the potential of the lower potential well and the potential barrier of the second lower charge is lowered and the charge is transferred to the lower side, one potential barrier remains on the lower side.
Charge mixing does not occur. In this way, the charges in the CCD can be driven in two phases by one control signal per row.

[0028]

FIG. 1 shows an embodiment of the present invention. Figure 1 (A)
Is a schematic top view of the solid-state imaging device, and FIG.
It is a potential diagram showing potential inside.

In FIG. 1A, a large number of photodiodes P are distributed in a matrix in the semiconductor substrate. VCCDs 1, 2, 3 are arranged adjacent to each column of photodiodes. One HCCD 6 is formed adjacent to one end of each of these VCCDs 1, 2, and 3.

One electrode E1, E2, E3, ... Is arranged for each row of photodiodes on the VCCDs 1, 2, 3 and is driven by a two-phase drive signal.

Drive electrodes E1, E2, E3 of VCCD ...
Are connected to the drive circuit 8 on the right side of the drawing,
It is connected to the potential holding circuit 9 on the left side.

The drive circuit 8 includes a switch circuit 10 including a switch for each row. HCC the photodiode matrix
Numbering from the side close to D6 to the first row, the second row, the third row, ..., In the switch circuit 10, the switch SW1 is arranged corresponding to the first row, and the switch SW2 corresponding to the second row.
Are arranged, and thus one switch SW is provided for each row.
Are placed.

These switches SW are respectively connected to VCC.
The D drive electrodes E1, E2, E3, ... Are connected one by one.
Further, the phase signal φ1 is applied to the odd-numbered switches SW1, SW3, SW5 ...
The phase signal φ2 is applied to 2, SW4, SW6, ....

Further, the switches SW1 and SW2 are simultaneously driven by the scanning signal S1, and the switches SW3 and SW4.
Are simultaneously driven by the scanning signal S2, and thus the switches SW are driven by the scanning signal S two by two.

The switches SW1 and S1 are turned on by the scanning signal S1.
When W2 is turned on, the phase signals φ1 and φ are applied to the electrodes E1 and E2.
2 is applied.

Next, when the switches SW1 to SW4 are turned on by the scanning signals S1 and S2, the phase signal φ1 is applied to the electrodes E1 and E3, and the phase signal φ2 is applied to the electrodes E2 and E4. In this way, the scan signal S sequentially expands its application range from the lower side.

When the switch SW is off, the electrode E connected to the switch is in a floating state. In order to prevent this floating state, the charge holding potential VL is applied to each electrode E2 on the left side through the potential holding transistor T. In the electrode E to which the phase signal φ is not applied, the charge holding potential VL is applied via the potential holding transistor T. When the phase signal φ is applied to the electrode E via the switch SW, the potential relationship of the potential holding transistor T changes and the charge holding potential VL is electrically separated from the electrode E.

FIG. 1B shows the potential in the VCCD. One potential barrier B and one potential well W are formed under each electrode E when an equal voltage is applied to each electrode E.

In the state where the charges are read from the photodiode to the VCCD, the charges Q are accumulated under each electrode E.

When the potential on the HCCD side is lowered, the electrode E
The charge Q1 stored under 1 is sucked out to the HCCD. When the potential on the HCCD side is returned to the original state, a potential barrier is formed again on the right side of the potential well W1 below the electrode E1.

Next, when the potential of the electrode E1 is pushed down, the potentials of the potential barrier B1 and the potential well W1 are lowered, and the potential well W
The charge Q2 stored in 2 moves to the potential well W1 below the electrode E1. When the driving voltage is returned to the original state, the potential well W2 becomes empty and the charge Q2 is accumulated in the potential well W1.

Next, when the potential of the electrode E2 is pushed down, the potential barrier B2 disappears and the charge Q3 moves to the potential well W2. At this time, the potential barrier B1 is kept as it is,
The charge Q3 is prevented from moving to the right of the potential well W2. When the applied voltage is returned to the original state, the potential wells W2 and W2
Electric charges are accumulated in 4 and W5, and W1 and W3 become empty.

Next, when the potentials of the electrodes E1 and E3 are pushed down, the charges Q3 and Q4 move from the potential wells W2 and W4 to the potential wells W1 and W3, respectively. In this way, charge transfer of the domino or accordion system can be performed.

2 to 7 show a charge transfer device and a driving method thereof according to a more specific embodiment of the present invention.

The photodiodes P11, P12, ... Are arranged in a matrix and connected to the VCCDs 1, 2, ... Which are arranged in the column direction through a transfer gate Tg (displayed only at the position of the photodiode P61). These regions are formed of, for example, n-type regions formed in the p well. Photodiode P, transfer gate T
The surface of the region excluding g, the VCCDs 1, 2, ... Is a region having a high p-type impurity concentration, and the channel stop region 11
Is formed. The photodiode Pij represents a photodiode in the i-th row and the j-th column.

The portions of the VCCDs 1, 2, 3, ... Which are continuous with the transfer gate Tg are photodiodes P63 and P.
A well region W having a low potential is formed as shown at a position 53, and a barrier region B having a high potential is formed between the well regions W.
Is formed.

Further, two insulating electrodes G are formed on the semiconductor surface corresponding to each row, and control the well region W and the barrier region B of the VCCD, respectively. For example, in terms of arrangement, the insulating electrodes G1a and G1b are arranged corresponding to the first row of the matrix, and the electrodes G2a and G2b are arranged corresponding to the second row. However, functionally, the electrodes G1b and G2a correspond to the first row as described below.

The shift register 12 has a timing signal φ.
Input A, φB, φIN, and scan signals S1, S2, S3
To occur. These scanning signals S are the switching MOS
Drive signal φ1 via transistors U1, U2, ...
1, φ21, φ12, φ22, ... Odd-numbered switch transistors U1, U3, U
.. are supplied with the phase signal .phi.1, and the scanning signals S1, S
The gate is controlled by 2, ...
1, φ12, φ13, ...

For example, the drive signal φ12 is the phase signal φ
1 represents the one controlled by the scanning signal S2. That is, when the phase signals φ1 and φ2 change, the scanning signal S1
Drive signal .phi.11 and .phi.21 also rise. If the scanning signal S1 is “0”, the driving signal φ1
1, φ21 does not occur.

The shift register 12 first scans the scan signal S1.
Of the scan signal S1 at the next timing.
And S2 rise, and at the next timing, the scanning signal S
1. Make S1, S2, and S3 stand up. Thus, the number of scan signals S output from the shift register sequentially increases. Therefore, the switching transistors U that are turned on are sequentially increased in number by two to supply the drive signal.

The drive signal φ11 is transmitted to the electrode G1a closest to the HCCD 6, and the next drive signal φ21 is commonly applied to the other electrode G1b in the first row and the electrode G2a in the barrier region in the second row. Thereafter, similarly, the drive signal φ12 is applied to the electrode G2b corresponding to the well region of the second row and the electrode G3a corresponding to the barrier region of the third row, and the drive signal φ22 is applied to the electrode G3b corresponding to the well region of the third row. And the electrode G4a corresponding to the barrier region of the fourth row.

As described above, each drive signal gives a common control signal to the well region in the lower row and the barrier region in the upper row. In the VCCDs 1, 2 and 3, a pair of well regions and barrier regions are formed when a common signal is applied to two adjacent set electrodes.

The electrode G1a is connected to the substrate voltage Vsub via the transistor V1 as shown on the left side of the drawing, and the charge holding potential Vsub is connected via the potential holding transistor T1.
Connected to L. The electrode G corresponding to the well region of the first row
The electrodes G2a corresponding to the barrier regions of the 1st and 2nd rows are commonly connected to the substrate voltage Vsub via the transistor V2 and to the charge holding potential VL via the potential holding transistor T2.

Thereafter, similarly, the electrode corresponding to the well region in the lower row and the electrode corresponding to the barrier region in the upper row are connected to the common Vsub, and are connected to the substrate potential via the transistor V to hold the potential. It is connected to the charge holding potential VL via the transistor T.

The transistor V is controlled by the field shift signal φFS and reads out the charges accumulated in the photodiode P to the well regions W of the VCCDs 1, 2, 3 ,.

Further, the potential holding transistor T is controlled by the gate voltage φG, and when the switching transistor U is off, the charge holding potential VL is applied to each electrode. However, when the drive voltage φij is applied to the electrode G, the transistor T is turned off, and the electrode has the potential of the drive voltage.

As is clear from the figure, the VCCDs 1, 2,
Two regions (cells) are formed per row in 3, ..., Two electrodes for controlling these regions are wired in pairs, and the electrodes on the right side and the left side control circuit per row, respectively. One control signal is connected.

The HCCD 6 is provided with four electrodes per column and driven in two phases by the drive signals H1 and H2.

FIG. 3 shows the fabrication of a VCCD in which the well and barrier regions can be formed simultaneously with the same applied potential. The built-in potential of the semiconductor region changes depending on the conductivity type and the impurity concentration of the impurities to be doped.
By utilizing this phenomenon, the well region and the barrier region can be formed.

FIG. 3A shows a step of forming a transfer channel to be a barrier region. A SiO ₂ layer 23 is formed on the surface of the p-type silicon region 21, and n-type impurities are ion-implanted. The ion-implanted n-type impurity forms an n ⁻ -type region 22 on the surface portion of the p-type silicon region 21. This n
^The- type region 22 will form a barrier region.

Next, as shown in FIG. 3B, SiO ₂
A 1-poly gate 24 is formed by forming a polycrystalline silicon (poly Si) layer on the layer 23 and patterning it. Next, using this 1-poly gate 24 as a mask, n-type impurities are ion-implanted.

The n-type impurity does not reach under the 1-poly gate 24, and the n-type impurity is ion-implanted only in the region without the 1-poly gate 24 to form the n-type region 25. Since the n-type region 25 has a higher n-type impurity concentration than the n ⁻ -type region 22, the potential for electrons becomes lower and a well region is formed. In addition, the formation of this region 25 is performed with 1 poly gate 2
Since it is self-aligned with 4, its positional accuracy is high.

Next, as shown in FIG. 3C, the surface of the one poly gate 24 is oxidized to form an oxide film 30, on which polycrystalline silicon (poly Si) is deposited and patterned. 2 Poly gate 26 is formed. This 2
The poly gate 26 is automatically aligned with the n-type region 25 serving as the well region.

In this way, two electrodes per row are formed by the set of one poly gate 24 and two poly gate 26. After that, as shown in FIG. 2, adjacent one poly gate and two poly gates are connected in common and connected to a drive circuit.

When the same voltage is applied to the adjacent 1-poly gate 24 and 2-poly gate 26, the barrier regions 22 and the well regions 25 have different impurity concentrations in the transfer channel region, and therefore have different potentials for electrons. In this way, potential barriers and potential wells for electrons can be created.

FIG. 4 shows another construction of the VCCD. Figure 3
In the preparation, the n-type impurity ion implantation was performed twice, but in this preparation, the n-type impurity ion implantation and the p-type impurity ion implantation are used.

First, as shown in FIG. 4A, p-type Si
The surfaces of the regions 21, to form a SiO ₂ layer 23, SiO ₂
N-type impurities are ion-implanted through the layer 23. The n-type region 27 is formed by ion implantation of n-type impurities. This n-type region 27 will form a well region of the transfer channel.

Next, as shown in FIG. 4 (B), SiO ₂
A polycrystalline silicon layer is formed on the layer 23 and patterned to form the 1-poly gate 28. Then, using this 1-poly gate 28 as a mask, p-type impurities are ion-implanted.

1 In the region where the poly gate 28 exists, p
The p-type impurity is not ion-implanted, and the p-type impurity is ion-implanted only in the region where the 1-poly gate 28 does not exist and the SiO ₂ layer 23 is exposed. In this way, in the region into which the p-type impurity is ion-implanted, the n-type impurity concentration is compensated by the p-type impurity concentration and becomes the n ⁻ -type region 29.

Thereafter, the surface of the 1-poly gate 28 is oxidized to form a SiO ₂ layer 31, and a poly-Si layer is deposited on the SiO ₂ layer 31 and patterned to form a 2-poly gate 32.

In this structure, a well region is formed below one poly gate 28, and a barrier region 29 is formed below two poly gate 32.

Although an example of forming regions having different impurity concentrations in order to form the potential well and the potential barrier has been described, the potential difference can be formed by other means. For example, if the thickness of the insulating layer on the transfer channel is changed, the influence of the same potential on the transfer channel is different and a potential difference can be generated. Further, the influence on the gate electrode can be changed by changing the material of the gate electrode. These means can be used alone or in combination.

In the structure of FIG. 2 in which the potential well and the potential barrier are automatically generated in the VCCD as described above, how charges are transferred will be described below.

5 and 6 are timing charts of control signals. In FIG. 5, the shift register 12 of FIG.
The timing signals .phi.A, .phi.B, and .phi.IN given to the signals have waveforms shown in the third to fifth stages, and generate scanning signals S1 to Sn as shown below.

After φIN rises, in the next horizontal blanking period HBK, only S1 rises,
In the next horizontal blanking period HBK, the scan signals S1 and S2 rise and the next horizontal portion ranking period H
In BK, the scan signals S1, S2, and S3 rise, and the number of rises of the scan signal S sequentially increases in this way.

The phase signal φ1 or φ2 is applied to the transfer transistor U to which the scanning signal S is applied. Therefore, the transistor U supplied with the rising scanning signal S is turned on, and the drive signal φij is formed from the phase signal φ1 or φ2 and is applied to the electrode G.

FIG. 6 shows the waveforms of the drive signals φ11, φ21, φ12, φ22, ... Formed in this way.

The control circuit portion shown on the left side of FIG. 2 is supplied with the control signal φFS shown in the upper part of FIG. 5 to perform field shift for taking in an image signal. The control signal φG holds the electrode to which the drive signal φij is not applied at the predetermined potential VL.

The lower part of FIG. 5 shows the waveforms of the two-phase drive signals H1 and H2 applied to the electrodes of the HCCD 6. The horizontal drive signals H1 and H2 have waveforms that alternately change during the horizontal scanning period, and sequentially transfer the charges transferred from the VCCD to the HCCD 6 in the horizontal direction. The vertical blanking period VB
At K, the image signal is captured from the pixel matrix.

FIG. 7 shows how charges are transferred in the VCCD. The electrode arrangement in the VCCD is shown in the upper part of the figure. In the figure, the HCCD is arranged on the left side and the VCCD is arranged on the right side. Each electrode of the VCCD is indicated by the applied drive electrode. Time t is taken in the vertical direction in the figure, and V is time-series.
The electric potential and electric charge in CCD and HCCD are shown typically.

First, the state in which electric charges are taken into the VCCD from the photodiode is shown at time t0. The charges accumulated in the photodiode are taken into the well region W corresponding to each row. These charges are separated from each other by the barrier region B.

At the next timing t1, the drive voltage φ11 is changed in the positive direction and the potential is pushed down. Therefore, the barrier B1 disappears, and the charge Q1 accumulated in the well region W1 is transferred to the HCCD. When the drive voltage φ11 returns to the original state, the barrier B1 is restored.

Next, at timing t2, when the drive voltage φ21 changes in the positive direction, the potentials of the well W1 and the barrier B2 are both pushed down, and the charge Q2 stored in the well W2 is transferred to the well W1. After that, when the drive voltage φ21 is returned to the original state, the potentials of the well W1 and the barrier B2 are returned to the original state, and the state shown at t3 is formed.

In the state of t3, charge transfer is performed in the HCCD. The well W2 does not store electric charges, and the electric charges Q2 and Q3 are separated by one row.

Next, at timing t4, the two drive signals φ11 and φ12 simultaneously change in the positive direction,
The potential of the corresponding area in the VCCD is pushed down. Barrier B1
And B3 disappear, the charge Q2 is transferred to the HCCD and the charge Q3 is transferred to the well W2. Even in this state, the barriers B2 and B4 maintain the potential of blocking the charge transfer.

After that, when the driving voltages φ11 and φ12 return to the original state, the state at the timing t5 is realized, and the barriers B1 and B3 are restored. In this state, the transferred charge Q3 and the next charge Q4 are separated by the two barriers B3 and B4.

At the next timing t6, the drive voltages φ21 and φ22 change in the positive direction, pushing down the potential in the VCCD. Therefore, the barriers B2 and B4 disappear, and the charges Q3 and Q4 are transferred to the wells W1 and W3.

After that, when the drive voltages φ21 and φ22 are returned to the original states, the barriers B2 and B4 are restored and the timing t
Seven states are realized. In this state, the transferred charges Q3 and Q4 are separated from the adjacent charges by two barriers. Also, the charge in the HCCD is transferred during this time.

In this way, the charges read from all the pixels at once by the accordion transfer method are transferred from the VCCD to the HCCD and read via the HCCD.

As described above, the potential barrier and the potential well are automatically formed in the VCCD to give one control signal per row, thereby transferring the charge in the VCCD by the two-phase driving. You can

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations and the like can be made.

[0092]

As described above, according to the present invention,
V for reading out charges from photoelectric conversion elements arranged in a matrix
In the CCD, one control signal per row is sufficient to transfer the electric charges, and therefore, the number of elements required for the VCCD control circuit is almost halved.

By simplifying the configuration of the control circuit,
High integration of the solid-state imaging device is facilitated.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention. 1A is a schematic plan view showing the configuration, and FIG. 1B is a schematic diagram showing the potential in the VCCD.

FIG. 2 is a schematic plan view of a solid-state imaging device according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view for explaining the production of VCCD.

FIG. 4 is a schematic sectional view for explaining the production of a VCCD.

5 is a timing chart of control signals in the circuit of FIG.

FIG. 6 is a timing chart of control signals in the circuit of FIG.

FIG. 7 is a schematic potential diagram for explaining charge transfer in VCCD and HCCD.

FIG. 8 is a schematic diagram for explaining an accordion transfer method according to a conventional technique. FIG. 8A is a diagram showing a potential change, and FIG. 8B is a schematic plan view showing a pattern of charge transfer.

[Explanation of symbols]

1, 2, 3 VCCD 6 HCCD 8 drive circuit 9 potential holding circuit 10 switch circuit 12 shift register 21 p-type Si region 22 n ^- type region 23 SiO ₂ layer 24 1 polygate 25 n-type region 26 2 polygate 27 n-type region 28 1 Poly Gate 29 n ^- Type Region 30, 31 SiO ₂ Layer 32 2 Poly Gate P Photodiode E VCCD Electrode SW Switch S Scan Signal T Potential Holding Transistor φ Phase Signal VL Charge Holding Potential

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[Procedure amendment]

[Submission date] November 26, 1991

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (4)

[Claims] 1. Charges accumulated in a large number of photoelectric conversion elements arranged in a matrix are sequentially transferred to a plurality of columns of vertical CCDs arranged corresponding to each column of the photoelectric conversion elements, and each vertical CCD is A method for driving a solid-state imaging device, in which charges in the vertical CCD are sequentially transferred to a horizontal CCD, and charges in the horizontal CCD are sequentially transferred to read out signal charges, wherein one voltage is applied to the vertical CCD. By doing 1
Controlling one potential well and one potential barrier,
A method for driving a solid-state imaging device, which comprises driving a CD in two phases to transfer charges. 2. A voltage is applied to the horizontal CCD to control one potential well and one potential barrier, and the horizontal CCD is driven in two phases to transfer charges. The method for driving a solid-state imaging device according to claim 1. 3. A plurality of photoelectric conversion elements arranged in a matrix and a plurality of columns of vertical CCDs arranged corresponding to each column of the photoelectric conversion elements, wherein one potential is applied by one driving voltage. A vertical CCD configured to control the well and one potential barrier and to receive one control voltage per row; and a control circuit for generating one control signal for each row of the vertical CCDs in the plurality of columns. Solid-state imaging device. 4. The drive circuit applies a drive voltage to a range in which the control circuit gradually spreads in a vertical direction from a side closer to the horizontal CCD, and a charge retention voltage is applied to the vertical CCD in a range where the drive voltage is not applied. The solid-state imaging device according to claim 3, further comprising: