JPS6315753B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a charge transfer device.

Charge transfer devices, such as CCDs (charge coupled devices), have a wide range of uses in digital memories, analog memories, analog signal processing, etc., and have recently received particular attention.

In such a charge transfer element, charge transfer section 1
A general conventional method of inputting signal charges to the circuit is as follows. As shown in FIG. 1, the potential applied to the diffusion layer 2, which is the charge input source, is closer to the ground potential than the surface potential barrier section for giving directionality to the charge transfer direction under the first stage gate. In this method, charges are input by inputting a charge by lowering the input voltage, and when no charge is input, the potential applied to the input source is increased to be higher than the surface potential of the barrier portion.

Furthermore, in contrast to the charge input method by changing the potential of the input source, the charge is supplied from the input source to the cell to which the input signal φ _IN is applied, without changing the potential of the input source, and transferred to the successive transfer cells. There is also a method of inputting signal charges according to a digital input signal.

However, the conventional method has had a problem in that it is difficult to stably generate signal charges.

The present invention provides a charge transfer device that can stably generate transferred charges by providing a gate electrode in front of an input signal electrode. That is, a gate electrode, a signal input electrode, and a transfer electrode are sequentially provided following a source region provided on a semiconductor substrate, a barrier region and a charge storage region are provided for each electrode, an input signal is applied to the input signal electrode, and the source region A charge transfer device is obtained in which a DC voltage is applied to the gate electrode and a sampling voltage is applied to the gate electrode.

Next, one embodiment of the apparatus of the present invention will be described with reference to the drawings.

First, a case where the input signal is a digital signal will be explained.

That is, in the charge transfer element, the potential of the source region is fixed and pulses are repeatedly applied to the gate electrode to draw charges from the source region and supply excessive charges to the input signal electrode to which input is applied. The amount of charge in excess of the charge determined by the surface potential under the electrode is pulled back to the bottom of the gate electrode, a constant charge is formed as an input signal, and the input signal is a logic 1 below the continuous transfer electrode in the charge transfer region.
The charge is input only when .

A detailed explanation will be given below with reference to FIGS. 2 and 3. A source region 12 made of, for example, an n-type silicon layer having a conductivity opposite to that of the silicon substrate 11 is formed on the inner surface of a P-type silicon substrate 11 serving as a semiconductor substrate of one conductivity type. Further, on the silicon substrate, gate electrodes, input signal electrodes, and transfer electrodes 14 ₁ , 14 are continuously connected from the source region 12 via an insulating film 13 made of silicon dioxide or the like.
₂ , 14 ₃ , 14 ₄ , 14 ₅ to 14 ₈ are provided, and every two electrodes are connected in common, and the two electrodes work together to form a gate electrode or the like. A charge sampling signal φ _S and charge transfer clock signals φ ₁ and φ ₂ other than the input signal φ _IN are alternately applied to each of the above electrodes. The structure includes a barrier region and an accumulation region under each gate electrode, input signal electrode, and transfer electrode. On the other hand, the electrodes 14 ₁ , 14 ₃ , 14
P ⁺ high concentration regions 15 ₁ , 15 ₃ , 15 ₅ , 15 ₇ are provided in self-alignment by ion implantation or the like on the inner surface of the silicon substrate 11 below 5 _, 14 ₇ ,
This forms a barrier region. source area 1
2 is the sampling signal φ _S applied to the gate electrode.
The surface potential of the barrier region 14 ₁ under the electrode 14 1 is closer to the ground potential than the surface potential under the electrode 14 ₁ when the high level of is applied, and the surface potential of the barrier region 14 1 under the electrode 14 1 is closer to the ground potential when the low level of the sampling signal φ _S is applied to the electrode 14 ₁ . It can be maintained at any constant potential within a range higher than the potential.
The electrode 14 ₂ is longer than the electrodes 14 ₄ , 14 ₆ , 14 ₈ , and below the electrode 14 ₂ are the electrodes 14 ₄ , 14 .
₆ , 14 More charges are accumulated than can be accumulated under ₈ .

The operation of the charge transfer element configured in this way when clock signals φ ₁ , φ ₂ , sampling signal φ _S and input signal φ _IN as shown in FIG. 4 are applied to the charge transfer element will be explained in chronological order. . Now, at time t ₁ , φ _S and φ ₁ are at high level potential, and φ _IN ,
Assuming that φ ₂ is at a low level potential, the surface potential within the silicon substrate will be as shown in FIG. 2b. At this time, charge is input from the source region 12 through the barrier region forming electrode 14 ₁ which constitutes the gate electrode to the storage region forming electrode 14 ₂ , and then at time t ₂ when φ _S returns to the low level, the barrier region Charges determined by the difference in surface potential under the region forming electrode 14 ₁ and the storage region forming electrode 14 ₂ and the channel width are accumulated in the potential well below the storage region forming electrode 14 ₂ . At time _t3 , the input signal φ _IN applied to the input signal electrode becomes high level, and the charges accumulated under the storage region forming electrode ₁₄₂ of the gate electrode are transferred to the potential wells under the input signal electrodes ₁₄₃ and ₁₄₄ . will be forwarded to. At time _t4 , when the input signal φ _IN becomes low level, the amount of charge determined by the difference in surface potential between the barrier region and the storage region and the channel width is set as a signal charge ₁₄₄ below the input signal electrode, and the excess that cannot be accumulated is set as a signal charge. This charge is pulled back under the gate electrode. Next, Fig. 3 b and c show the surface potential and charge corresponding to times t ₅ and t _6. At time t ₇ , when the input signal φ _IN is at a low level, the gate electrode 14 ₂
The lower charge is not inputted below the input signal electrode ₁₄₄ (FIG. 3d), and a state with no charge is inputted to the charge transfer element in response to the low level of the input signal.

Conventionally, when opening and closing the input signal electrode of the first stage, the amount of charge sucked in from the source region is greater than the set value if the rising speed of the input signal electrode, that is, the operating speed is fast, and a constant signal charge is stably generated. There were design and reliability problems, such as the inability to do this, but once the transfer was carried out in this way, stable supply became possible.

In the above embodiment, in order to transfer excess charge from the gate electrode to the input signal electrode, the gate length of the charge storage region of the gate electrode is increased, but the size of the charge storage region is increased by widening the channel width of the gate electrode. A similar effect can also be obtained by increasing the size. It is also possible to obtain similar effects by combining the above methods. Furthermore, in the above embodiment, the surface potential of each part was set by controlling the concentration of the high concentration region (P ⁺ layer) by ion implantation, etc.
The surface potential may be set by changing the thickness of the insulating film 13 such as a silicon dioxide film. It goes without saying that the concentration of the high concentration region may be controlled as well as the thickness of the insulating film 13. Also, the above explanation is
Although this was done using a type semiconductor substrate, it is clear that when an n-type semiconductor substrate is used, the same effect can be achieved by changing the signals of each part to opposite signs.
Further, in the above embodiment, the charge transfer element driven by a two-phase drop clock was described, but it is of course applicable to other ME/B type charge transfer elements driven by a multi-phase drop clock. It is applicable not only to drop clock drive but also to push clock drive. It can also be applied to a buried channel type charge transfer element. As described above, the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist of the present invention.

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining the input of signal charges of a conventional element, Figs. 2 and 3 are diagrams showing an embodiment of the present invention, and Fig. 4 is a diagram for explaining the charge transfer of Figs. 2 and 3. FIG. 3 is a waveform diagram of a drive signal for an element. 11...Silicon substrate, 12...Source region,
13...Insulating film, ₁₄₁ , ₁₄₂ , to ₁₄₈ ...Electrode, ₁₅₁ , ₁₅₃ , ₁₅₅ , ₁₅₇ ...P ⁺ layer (high concentration region).

Claims (1)

[Claims] 1 a semiconductor substrate of one conductivity type; a source region formed on the surface of this substrate and of a conductivity type opposite to that of the substrate;
a plurality of transfer electrodes formed on the substrate with an insulating film interposed therebetween and arranged in a charge transfer direction apart from the source region; and a plurality of transfer electrodes formed on the substrate between the transfer electrodes and the source with an insulating film interposed therebetween. a gate electrode formed, an input signal electrode formed on the substrate between the gate electrode and the transfer electrode via an insulating film, and an input signal electrode formed under each of the gate electrode, the input signal electrode, and the transfer electrode. means for supplying a pulse signal for sampling charges to the gate electrode; means for supplying an input signal to the input signal electrode; and a clock signal of a predetermined phase to each of the plurality of transfer electrodes. 2. A charge transfer device, characterized in that the size of the charge storage region under the gate electrode is larger than the charge storage region under the input signal electrode and the transfer electrode.